JPH03168818A - Clock control system for computer - Google Patents

Abstract

PURPOSE:To reduce the power consumption of a computer in a key entry waiting state by supplying a constant-speed clock to the computer when the key entry waiting state is estimated, and at the time of confirming key entry, returning the clock speed to the original speed. CONSTITUTION:When the key entry waiting state of the computer is estimated, a selector 7 in a clock control circuit 2 selects the constant-speed clock of a constant-speed clock source 3 as a CPU clock and supplies the selected clock to a CPU 1. Since a key entry confirming function is called for a short period in a simple key entry waiting state, the CPU clock is fixed on the constant- speed clock during the period. When the key entry is confirmed and a keying code inputting function is called, the selector 7 restores the CPU clock to a rapid clock obtained from a rapid clock source 4. Consequently, the power consumption of the computer in the key entry waiting state can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a computer clock control method for reducing power consumption when the computer is waiting for key input. [Summary of the Invention] When a computer is estimated to be waiting for a key input, the clock speed is kept constant during that time to reduce power consumption. [Prior Art] Since the state in which a computer waits for a key input is a useless state in which no calculations are performed, it is desired to save power consumption during this time. For this reason, a method has been proposed in the past in which the clock speed of the computer is reduced while the computer is in a state of waiting for a key input, and the computer returns to normal operation after a key input. In this conventional method, a program waiting for key input is provided in the basic input/output system software (BIOS) installed in the computer in advance, and is used when necessary. Therefore, this effect was effective only when a program running on the computer used the BIOS key input waiting program.

[Problem to be Solved by the Invention] As described above, in the conventional method, the key input waiting program of the BIOS is not used, or the key input waiting program is called after confirming whether or not there is a person who can press the key. When a software program such as this runs on a computer, most of the waiting time for key human power is spent in that software program, which results in unnecessary CPU operations and reduces the clock speed. There is almost no time for this to occur, and the effect of reducing power consumption is almost negligible. Most of the application software programs currently in use are of this type, and the desired effects cannot be expected.

[Object of the Invention] Accordingly, an object of the present invention is to provide a clock control method that is effective in reducing power consumption in a computer while it is waiting for a key input.

[Means for Solving the Problems] In order to achieve the above object, the clock control method of the present invention has the following features:
means for estimating the key input waiting state of the computer;
The gist of the present invention is to include means for making the clock speed of the computer constant when a state of waiting for a key input is estimated, and means for restoring the speed of the clock after the estimated time of waiting for a key input has elapsed.

[Operation] When the state of waiting for a key input is estimated, a constant speed clock is supplied to the computer. Once key power is confirmed, the clock speed is restored.

[Examples] The present invention will be described below with reference to examples shown in the drawings. FIG. 1 shows an embodiment of a computer clock control system according to the present invention. In the same figure, engineering is the computer's C.
P.U. 2 is a clock control circuit, 3 is a constant speed clock source, 4
5 is a high-speed clock source, and 5 is a bus for signals corresponding to key inputs, etc. 6 is a clock input port of the CPU.

The clock control circuit 2 includes, for example, a clock selector 7 for changing the clock speed, and a counter 8 for counting the passage of time.
, a latch circuit 9 that latches the count output of the counter 8, and a register 10 in which an upper limit value for elapsed time is set.
, and the comparator circuit engineer 1 who compares the contents of the latch circuit 9 and the register 10.

Instructions for the clock control circuit 2 are generated, for example, by the basic input/output system software (BIOS), which takes effect according to the flowcharts shown in FIGS. 2 and 3. Figure 4 is a flowchart showing the key input waiting algorithm used by most general-purpose application software.As mentioned above, in the past, the key input waiting loop was on the application software side, and during that time unnecessary CPU operations were performed. It had already been done.

Therefore, in the present invention, the software (program of the computer itself) called by the BIOS call in the above algorithm includes a clock control circuit 2 as shown in FIG.
An instruction M is included to effectuate an order for the following.

When running general-purpose software as shown in Figure 4, the above command M! Activate the clock control circuit 2 by
A latch circuit 9 latches the count value corresponding to the time since the last activation by the counter 8, and a comparison circuit 1l compares the count value with the upper limit value of the elapsed time set in the register 10, As a result, when the count value is smaller than the upper limit value, the selector 7 selects the constant speed clock of the constant speed clock source 3 as the CPU clock and supplies it to the CPU I for the time of the count value.

When waiting for a simple key input, the key manual confirmation function is called in a short period of time, so the CPU clock is fixed to a constant speed clock during that time, and power consumption is reduced accordingly.

When the key input is confirmed and the key input code capture function is called, the counter clear command M2 is issued, and the selector 7 of the clock control circuit 2 receives the high-speed clock from the high-speed clock source 4 as the CPU clock. to be restored.

Therefore, the original computer processing after key manual input is processed by the normal high-speed clock, and the original computer processing can be performed without any influence.

Furthermore, even if some processing is inserted while waiting for a key input, the CPU clock will only be kept at a constant speed during the normal key input waiting time count defined by the enforcement and upper limit settings, and that process will cause the CPU clock to run at a constant speed. The clock never slows down.

[Effects of the Invention] As explained above, according to the present invention, the following excellent effects can be obtained. (i) Minimum period (1
Since the CPU clock speed is reduced by estimating the loop period), processes that require normal CPU clock speeds are not affected. (3i) Even if the general-purpose application software does not have this kind of support, it can automatically reduce power consumption. (iii) Since the expected time for waiting for key input can be made variable, the best reduction in power consumption can be expected in some cases.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIGS. 2 to 4 are flowcharts showing an algorithm for waiting for key input according to the present invention. 1........ CPU, 2........ Clock control circuit,.... Constant speed clock source, 4........ High speed clock

Claims (1)

[Claims] means for estimating the key input waiting state of the computer;
A computer comprising: means for making the clock of the computer constant when a state of waiting for a key input is estimated; and means for restoring the speed of the clock after the estimated time of waiting for a key input has elapsed. Clock control method.