JPH0316807B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an oscillation output device that outputs an output signal that matches the phase of an input signal.

The present invention is especially effective when the input signal is a burst signal, and furthermore, it provides a circuit device suitable for constructing a concrete circuit with an integrated circuit.

Hereinafter, the present invention will be explained based on illustrated embodiments.

FIG. 1 is a block diagram of essential parts for explaining the present invention. In FIG. 1, 1 is an input terminal that supplies an input signal, 2 is an output terminal that takes out an output signal,
4 is an oscillation circuit, 5 and 6 are phase comparison circuits each having the same configuration, and 7 is a phase shift circuit.

The oscillation circuit 4 outputs two or more output signals having different phases from each other, and sends each output signal to the phase comparator circuits 5 and 6.
and is supplied to the phase shift circuit 7. Here, to simplify the explanation, it is assumed that there are two output signals from the oscillation circuit 4, and the phase dependence thereof is 0° and 90°, respectively. Also,
It is assumed that the oscillation frequency matches or is very similar to the frequency of the input signal supplied to input terminal 1. The error varies depending on the system and design specifications in which the present invention is used, but for example,
It is about 10 ^-2 or less. A signal with a phase of 0° is supplied to a phase comparator circuit 5, and a signal with a phase of 90° is supplied to a phase comparator circuit 6.

On the other hand, the input signal supplied to input terminal 1 is a temporally continuous sine wave signal having a single frequency component, and this is supplied to phase comparator circuits 5 and 6. The phase comparator circuit 5 compares the phase of the input signal and a signal with a phase of 0°, and the phase comparator circuit 6 compares the phase of the input signal with a signal with a phase of 90°, and generates a control signal according to the phase difference between the two signals. Output.

The phase shift circuit 7 is supplied with two signals having phases of 0° and 90° from the oscillation circuit 4, and depending on the control signals from the phase comparison circuits 5 and 6, a signal with a phase of 0° and a signal with a phase of 90° are supplied. By changing the mixing ratio of the 180° signal or their inverted signal, that is, the 180° signal and the 270° phase signal, output a sine wave signal of a certain phase, for example, the same phase as the input signal, to the output terminal 2. . This operation will be explained in more detail with reference to FIG. It should be noted that the phase comparison circuits 5 and 6 can be constructed by well-known circuits, and a specific circuit diagram will be omitted.

FIG. 2 is an electric vector diagram for explaining the operation of the phase shift circuit 7. FIG. In the figure, 20 is a vector indicating an input signal, 21 is a vector indicating a signal with a phase of 0° among the output signals of the oscillation circuit 4, 22 is a vector indicating a signal with a phase of 90°, and 23 corresponds to the vector 21. A vector 24 indicates a signal obtained when the signal is controlled by the control signal output from the phase comparison circuit 5; A vector 25 indicating the obtained signal is a vector obtained by combining the vectors 23 and 24, and indicates the vector of the output signal obtained at the output terminal 2. The phase shift circuit 7 receives two signals with a phase of 0° and a phase of 90° from the oscillation circuit 4, that is, signals corresponding to vectors 21 and 22, and uses two control signals from the phase comparison circuits 5 and 6. are converted into signals corresponding to vector 23 and vector 24, respectively, and further synthesized into a signal corresponding to vector 20.

A specific example of the phase shift circuit 7 is shown in FIG. In the figure, 31 to 42 are transistors, 51 to 54 and 56 to 59 are signal input terminals, 60 is an output terminal, 61 and 62 are emitter resistors, 63 is a load resistor, and 65 is a DC power supply terminal. transistors 31 and 32, 33 and 34,
35 and 36, 37 and 38, 39 and 40, 41 and 4
2 form emitter-coupled differential amplifiers. These differential amplifiers can be emitter-coupled via emitter resistors as necessary for stability, gain adjustment, etc., but are omitted from the diagram. In addition, transistors 31 to 4
A DC bias voltage is applied to the base of 2 by a well-known circuit, but it is omitted in the figure.

Input terminals 51 and 53 are supplied with signals corresponding to vectors 21 and 22 in FIG. 2, that is, a signal with a phase of 0° and a signal with a phase of 90° from the oscillation circuit 4 in FIG.
It is transmitted to the bases of transistors 31 and 32. Input terminals 52 and 54 are supplied with a 180° phase signal and a 270° phase signal from oscillation circuit 4 in FIG. 1, and are transmitted to the bases of transistors 32 and 34, respectively. Transistors 31 and 32, 33 and 34 have common emitter resistors 61 and 6.
2, the input terminals 52 and 54 are
The same operation will occur even if the input signal is a fixed DC voltage. In any case, when the above signals are supplied to the input terminals 51 to 54, the transistor 31
~34 collectors have phases of 0°, 180°, 90°,
A signal current of 270° flows through transistors 35 and 36, 37 and 38, 39 and 40, 41 and 4.
2 emitters, respectively.

Input terminals 56 and 57 are supplied with a control signal from phase comparison circuit 5 of FIG. 1, and input terminals 58 and 59 are supplied with a control signal from phase comparison circuit 6 of FIG. 1, respectively. When the voltage supplied to input terminal 56 is higher than that of input terminal 57, more than half of the collector current of transistor 31 flows to transistor 35. Further, more than half of the collector current of the transistor 32 flows into the transistor 38, this current is transmitted to the load resistor 63, and the phase
A 180° output signal appears. This output signal is the second
This is a signal corresponding to vector 23 in the figure. Therefore, the magnitude of the vector 23 indicating the output signal changes depending on the input voltages of the input terminals 56 and 57, and depending on the magnitude relationship, a signal with a phase of 0° or a signal with a phase of 0° changes.
This is a vector indicating a 180° signal.

In exactly the same way, the second
An output signal corresponding to the vector 24 shown appears at the output terminal 60. Input terminals 57 and 59 have
Transistors 35 and 36, 37 and 38, 39 and 4
Since 0, 41 and 42 form a differential amplifier, the same operation can be achieved even with a fixed DC voltage. The load resistance 63 includes transistors 36, 38, 40, 4
2, the outputs of these transistors are added and combined to provide an output signal at output terminal 60 corresponding to vector 25 in FIG.

Phase comparator circuits 5 and 6 each have an input terminal 1
Compares the phase of the input signal supplied by the input signal with the phase of the signal at phase 0° (or 180°) and phase 90° (or 270°), and generates a signal related to the phase difference, such as a proportional voltage. This can be constructed using well-known techniques. Further, the output may be one or a pair obtained by using a suitable differential amplifier.

FIG. 4 is a block diagram of essential parts showing one embodiment of the present invention. Components having the same functions as those in FIG. 1 are given the same reference numerals. In FIG. 4, 8 and 9 are sample and hold circuits which are particularly important in the present invention, and signals to be held are supplied from phase comparator circuits 5 and 6, respectively, and their outputs are coupled to phase shift circuit 7. Reference numeral 3 denotes an input terminal for a sampling pulse which determines the period to be sampled and held, and is connected to sample and hold circuits 8 and 9. FIG. 5 is a waveform diagram showing signal waveforms of main parts for explaining the operation of FIG. 4, and the horizontal axis shows time.

Hereinafter, FIG. 4 will be explained in detail together with FIG. 5.

FIG. 5a is a diagram showing an input signal supplied to input terminal 1 of FIG. 4. The input signal is as shown in Figure 5b.
This is a so-called burst signal, which is extracted from _a sine wave signal having a single frequency as shown in _FIG . FIG. 5c is a diagram showing an output signal from the oscillation circuit 4, and shows, for example, a signal with a phase of 0°. FIG. 5d shows the sampling pulses supplied to the input terminal 3. In FIG. 4, the input terminal 1 is input to the phase comparator circuit 5 as shown in FIG.
The signals shown in are supplied, their phases are compared, and a signal corresponding to the phase difference is outputted from the phase comparison circuit 5 and transmitted to the sample and hold circuit 8. Since the input terminal 3 of the sample and hold circuit 8 is supplied with the sampling pulse shown in _{FIG .}
The signal from the phase comparator circuit 5 is transmitted to the phase shift circuit 7 only during this period. Furthermore, after time _t2 , the value at time _t2 is maintained and transmitted to the phase shift circuit 7. The phase comparator circuit 5 calculates the time required to generate a control signal according to the phase difference between the two input signals from time _t1 .
Since the control signal held by the sample and hold circuit 8 at time t ₂ is designed to be shorter than the period t ₂ , the control signal held by the sample hold circuit 8 at time t 2 is sufficient to output the desired signal at the output of the phase shift circuit 7. Has a value. The phase comparator circuit 6 and sample hold circuit 9 operate in exactly the same way, but this system operates only when the signal with a phase of 90° is output from the oscillation circuit 4.
Controls the phase shift circuit 7. The phase shift circuit 7 has exactly the same function and operation as the phase shift circuit 7 shown in FIG. 1, so that the phase shift circuit 7 shown in FIG. A signal equal to is obtained.

As described above, according to the present invention, a stable oscillation output that is phase synchronized with a burst input signal can be obtained with a relatively simple circuit configuration. In particular, since the phase shift circuit is constructed without using many components such as capacitors and coils, it provides a circuit device that is optimal for integrated circuits with a limited number of pins.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the main part of the oscillation output device for explaining the present invention, Fig. 2 is an electric vector diagram for explaining the operation of the phase shift circuit of the same device, and Fig. 3 is a diagram of the phase shift circuit of the same device. 4 is a main part block diagram of one embodiment of the present invention, and FIG. 5 a, b, c, and d are the fourth
It is a signal waveform diagram of each part in the figure. 1... Input terminal, 2... Output terminal, 4... Oscillation circuit, 5, 6... Phase comparison circuit, 7... Phase shift circuit, 8, 9... Sample hold circuit, 31-4
2...Transistor, 61, 62...Resistor, 63...
…Load resistance.

Claims (1)

[Scope of Claims] 1. An oscillation circuit, two or more phase comparator circuits each receiving as inputs two or more oscillation outputs having different phases from the oscillation circuit and a burst input signal supplied from the outside; , two or more sample and hold circuits each receiving an externally supplied sampling pulse and the output of the two or more phase comparator circuits, and two or more oscillation outputs having mutually different phases from the oscillation circuit. An oscillation output device comprising: a phase shift circuit controlled by the outputs of two or more sample and hold circuits. 2. The oscillation output device according to claim 1, wherein the phase shift circuit includes two or more sets of double-balanced differential amplifiers and a common output load resistance.