JPH03102879A - Electrically erasable and electrically programmable read only memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor memory devices, and more specifically to floating gate electrically erasable and electrically programmable memory devices. ROM (Read Only Memory) and the manufacturing method of such VT4.

Prior Art and Problems EPROM, or electrically programmable ROM,
This is a field effect B-type device with a floating gate structure. Generally E
The P R O M floating gate applies appropriate voltages to the source, drain, and control gate of each cell, and
It is programmed by creating a high current in the drain path and charging the floating gate with hot electrons. EPROM-type V4 devices are typically erased by ultraviolet light, which requires a device package with a crystal window on the semiconductor chip. This kind of package is l)RA
It is expensive compared to plastic packages commonly used for other memory devices such as dynamic random access memory (M). For this reason, EFROM
are generally more expensive than plastic packaged packaging. This type of EPROM device and its manufacturing method are described, for example, in U.S. Pat. No. 3,984.822, 4.1
No. 42.926, No. 4.258.466 Bow, No. 4.37
6.947 Bow, No. 4,326.331, No. 4,313
．． No. 362, or No. 4.373.248. U.S. Pat. No. 4,750,024 shows an EPROM formed in a manner similar to that of U.S. Pat. No. 4,258,466, but with a split gate structure, in which part of the floating gate is and a portion of the control gate are separated from the channel region by a thin dielectric (insulator).

E'EPROMs, electrically erasable and electrically programmable ROMs, are manufactured in a variety of processes and generally require larger cell dimensions than subtype Ia EPROMs. . The structure and manufacturing process are generally more complex. The EEPROM array can be packaged in an opaque plastic package, reducing the cost of the package. However, EEPROM arrays are more expensive per bit than EPROM arrays due to their larger cell size and more complex manufacturing process.

The split gate structure of U.S. Pat. No. 4,258,466 has been used in EEPROM arrays in which one or more floating gates are
over-erase) or put into a positively charged state, thus causing the associated memory cell or cells to conduct in the channel region under the floating gate.
Allows read, program, and erase operations to occur.

Compared to HEPROM arrays, EEPIIM arrays require a wider range of voltages to be applied to the bit lines for programming, reading, and erasing. Because the bit line is connected to many cells in the array other than the cell being programmed, read, or erased, a wider range of voltages can cause one or more other cells to be inadvertently programmed or erased. There is an increased possibility of damage. This is US Patent Application No. d 07/274.7
This is particularly problematic in so-called "virtual ground" 7-rays, as described in No. 18.

Flash EE-PROMs have the advantage of smaller cell size compared to standard QE-PROMs because the hills are not individually erased. Instead, the array of cells is erased en masse.

Modern flash EEPROMs require at least two external power supplies, one for programming and erasing and one for reading. Normally, a 12 volt power supply is used for programming and erasing, and a 5 volt power source is used for continuous firing operations.

However, it is desirable to use a single, relatively low voltage power supply for all program, erase, and expose operations. For example, if the memory cells of the array are
If designed to be programmed and erased with a relatively small l1f current, an on-chip charger can be used to generate higher voltages from a 5 volt source.
Bomb techniques may also be used. Generally, Fowler-Nordheim tunneling (F
owler-NOrdhCiiffi tunnel
For cells designed to use
Compared to the current when using the electron program,
The current required is relatively small.

Pending U.S. Patent Application No. 07/219.528;
No. 07/219.529, No. 07/219,530M
The EEPROM described in this article has a greatly improved structure and a smaller size. A method is provided for forming a cell that is easy to JA fabricate, resulting in a relatively low voltage (
A device is formed that requires one external power supply (possibly <+5V).

In these devices, Fowler-Nordheim tunneling is used for erasures and bunn-grams. However, these inventive devices require a split gate structure that allows the floating gate to be overerased without adversely affecting read, erase, or program operations. Unfortunately, sublit
The gate structure requires less space than traditional stacked gate structures. Almost no extra space is left on the one-way board.

As methods improve to eliminate problems with floating gate overerasure, a need has arisen for structures that eliminate the space requirements of split gates.

At the same time, non-split gate structures should have the advantages of buried bit lines and self-aligned structure process steps. These advantages include a reduced Hill voltage method and improved coupling of the voltage applied to the control gate to the floating gate. It would also be desirable to provide an electrically erasable, electrically programmable memory that can be packaged in a less opaque plastic package. Each hill of memory should be designed so that it can be scaled to smaller dimensions as improvements in process technology reduce dimensions. Preferably,
Nonvolatile memory should use a single low voltage external power supply for programming, erasing, and reading. The memory device should also be compatible with the programming on the board or in the circuit.

Means and Effects for Solving the Problems According to one embodiment of the present invention, the electrically extinguishable P
ROM or EEPROM is formed using a single transistor structure without a split gate structure which requires part of the tllll control gate and part of the floating gate to be disposed over the channel region. A floating gate transistor may have a small self-aligned tunnel window placed over the source away from the channel region, or the tunnel may be placed over the source near the channel region. The EhiPROM device has a contact-free cell layout, which facilitates manufacturing and reduces cell size. The device has a bit line (source/drain region) buried under a relatively thick silicon oxide to provide good coupling of the control gate voltage to the floating gate. Programming and erasing is performed using a tunnel window region, which allows programming and erasing to use a relatively small amount of current drawn from the charge bomb source. The tunnel window has a thinner dielectric than other areas of the floating gate, resulting in Fowler-Nordheim tunneling. By using dedicated drain and ground lines rather than a virtual ground circuit layout, and by using thick oxide for isolation between bit lines of cells in vA contact, floating gates are placed above adjacent bit lines and isolation areas. It extends. Therefore, the structure has excellent efficiency for coupling the control gate voltage to the floating gate during write and erase operations.

New features that seem to be characteristic of the present invention. Current features are set forth in the claims. However, the invention itself, as well as other objects and advantages of the invention, can be clearly understood from the following detailed description of the embodiments, as well as other objects and advantages of the invention. It will be understood.

Embodiments In FIGS. 1, 2a-2e, and 3, electrically erasable and electrically programmable memory
An array of cells 10 is formed on the surface of a silicon substrate 11. Although only a small portion of the substrate is shown in the drawing, it is understood that these cells are part of an array of many such cells. Several word lines 411 Ill gates 12 are formed by second level polycrystalline silicon (polysilicon) strips extending along the surface of the substrate 11, and bit lines 13 are formed by Ill gates 12 extending along the surface of the substrate 11. A thermal silicon oxide layer 14 is formed below. A buried bit line 13 forms a source region 15 and a drain region 16 for each cell 10. The floating gate 17 for each hill is formed by a first level polysilicon layer extending across the channel region between the source region 15 and drain region 16 and over the associated bit line 13. The two "horizontal" or X-direction ends of floating gate 17 for each cell are connected to word line 1
2 ends.

Program and erase tunnel area 19 (for each cell 1
Source 1 may be formed on the source 15 portion of source 1
This part of 5 is opposite the channel area. Optionally, the tunnel region 19 may be shaped as shown in FIGS. 5 and 6a, where the tunnel window is over a portion of the source region 15 near the channel region. The structure of FIGS. 5 and 6a is also incorporated in U.S. patent application Ser. No. 07/219.
．． No. 528, and No. 07/219.530. The silicon oxide of the tunnel window 19 is a channel! It is thinner than the dielectric coating 20 of about 350A in the region '1, which is about 10OA. Using this structure, programming and erasing can be performed with a relatively low externally applied voltage. The floating gate has bits 1i113 and thick oxide Ill
As compared to the coupling between the floating gate 17 and the source 15 or the base plate 11, the coupling between the cap 12 and H17 is more favorable because it extends across the area 22. Therefore, most of the program/erase voltage applied between control gate 12 and source 15 appears between floating gate 17 and source 15. Cell 10 is referred to as "contact free" because there is no need for source/drain contacts near the cell itself.

FIG. 7 shows yet another embodiment of the invention. The structure of FIG. 7 is similar to the structure of FIG. 2a, but the window 19 is placed over both the source region 15 and the drain region 16;
For example, the window 19 above the source 15 may be used to program, and the window 19 above the drain 16 may be used to erase.

In Figures 1 and 2b, territory IIi! 21 are used to divide the cells in the Y direction.

This area 21 corresponds to the aforementioned pending U.S. Patent Application No. 07
may be similar to region 21 of No. 1/219.530, or as shown in FIGS. The trench 23 may be replaced with a P-type impurity implanted. As is known, trench 23 may be filled with oxide, but this is not shown. LOGO
S thick field oxide strips 22 separate bit lines 13 between cells in the X direction. Please note that the array of cells is not a "virtual ground circuit" type.1
There are two bit lines 13 or column lines (one for the source and one for the drain), one for the source and one for the drain, with one bit line being a dedicated ground. The other line is the data input/output and sense line.

EE P of Figures 1, 2a to 2e, and 3
The R OM cell can be programmed with a charge bomb generation voltage of +15 to +20V for a given hill 10 source 15. For example, in FIG. 3, if cell 10a is selected to be programmed, a given word line 12, designated W L 1, will be +vp
A predetermined source, designated p and designated SO, is grounded.

A given drain 16 (designated Do in this example) is
It floats in these programmed states and therefore sees little or no current in the source-drain path. Fowler-Nordheim tunneling across tunnel oxide 19 (approximately 100A thick) is performed for a given cell 1
0a floating gate 17, which causes a shift to the threshold Ia voltage of about 3 to 6 volts after a pre-L1 gram pulse of about 10 milliseconds in length.

Certain cells of FIGS. 1, 2a-2e, and 3 apply a voltage Vee (originated internally) of approximately -10V to a certain word line/control gate 12, and approximately +5V.
can be erased by applying a voltage of 1 to the source 15 or the bit line 13. Drain 16 (other bit line 13
) floats.

During the erasing operation, f! Since II control gate 12 is negative with respect to source 15, electrons flow from floating gate 17 to source 15. During the erase operation, care must be taken to avoid over-erasing the cells. One way to avoid over-erasing is to apply successive erase pulses to the device, checking between erase operations to ensure that none of the voltage thresholds of the hills fall below a predetermined minimum threshold voltage. . Another method is to reinject electrons into the floating gates of any overerased cells.

In addition to this, (i) the predetermined source 15 is
, a larger negative voltage by a given control gate 12,
How to apply <-18V, (11) Probably<+
There is a method of applying 13V to a predetermined source 15, floating a predetermined drain 16, and connecting a predetermined control gate 12 to a reference potential or O volts. Using the latter method eliminates the need for a negative voltage source.

When "flash erasure" is performed (all 10 are erased at the same time), FIGS. 1, 2a to 2e,
and all drains 16 in the array of FIG. 3 are floating;
All of the sources 15 are at potential Vdd, and the word line
All of the control gates 12 are at potential -vee.

During the programming example (cell 10a is being programmed), in order to prevent write protection, the source 15 of an unselected cell, such as cell 10b, on the same word line WLI in FIG. All are held at a voltage Vb1 in the range of approximately +5 to +7 volts.The drains 16 of unselected cells, such as 10b, are floating, preventing source-drain current from flowing. The applied voltage vb1 prevents the electric field across the tunnel oxide 19 of the cell, including example cell 10b, from becoming large enough to initiate electron tunneling or charge the floating gate 17.

Another condition to avoid is "bit line stress" or deprogramming, which is associated with high electric fields across the tunnel oxide of a programmed cell when the cell's source is at a potential near b1. In order to prevent this pit line stress condition, the unselected one node line/control gate W1-0 and WL2 in FIG.
to +10 volts, thereby reducing the electric field across tunnel oxide 19 of each unselected programmed cell. A programmed cell such as 10C has a potential of approximately -2 to -4 volts on its floating gate, and therefore such a cell 10C
The electric field across the tunnel oxide tends to deprogram the cell when the voltage Vb1 on source S1 is in the range of +5 to +7 volts, but when the voltage on word line WL2 is +
In the range of 5 to +10 volts, the electric field decreases. However, the voltage on the word line/control gate is not large enough to cause a change in the threshold voltage Vt of a cell that has no charge on its floating gate.

The aforementioned cells can be read at low voltages. For example, for a row of cells, apply +3V to a given word line/control gate, zero volts to all other word lines/control gates, zero volts to all sources, and +1.5V to all drains. can be read with In this state, the cell source
The drain path is conductive with the cell in the erased state (a cell with a floating gate and no charge), ie, stores a logic one. A programmed cell (with a negative charge on the floating gate and 70 grams put into a high voltage threshold state) will not conduct, ie, will store a logic zero.

The method of manufacturing the device of FIGS. 1 and 2a-2e will be described in conjunction with FIGS. 4a-4d.

The initial material is a slice of P-type silicon, of which only a small portion is the substrate 11.

The slice is probably 6 inches in diameter, but the section shown in Figure 1 is only a few microns wide.

The transistors surrounding the array are formed through several process steps, all of which will not be described here.

For example, the memory device may be of the complementary field effect type, with an N-well and a P-well formed in substrate 11 as part of a pre-process to form peripheral transistors. The first step associated with the cell array of the present invention is to apply an oxide coating 30 and a silicon nitride coating 31 and pattern these coatings using photoresist, as shown in FIG. 4a. The process leaves behind the nitride that will become the channel region, source, drain, and bit line 13, while thick field oxide regions 22 (
21 if oxide separation is used instead of trench 23
12 -2 ) to expose the area to be formed. An ant boron implant of approximately 8X10 am is performed, and the field oxide 22 (and 21 if present) is
Form a P0 channel stop below. The field oxide is then exposed to steam at about 900 degrees Celsius for several hours and grown to a thickness of about 9000 Å. Thermal oxide grows below the edge of nitride 31, forming a "bird's beak" shape 22a rather than an abrupt transition.

In FIG. 4b, where nitride 31 is removed and bit line 13 is to be formed, an arsenic implant is applied at 135 KeV.
Then, about 6×10 15 am −2 It′ is performed using photoresist as an implant mask to form source/drain regions and bit lines.

Another thermal oxide 14 is then grown on the surface to a thickness of about 2500 to 3000 Å over the N+ buried bit lines, forming a heavily doped silicon region and a lightly doped silicon region. Due to the oxidation difference that occurs when oxidation is performed simultaneously, about 300 A of thermal oxide is grown on the channel region and oxidized on the source/drain region and bit line 13. ! Form Ili414. This oxidation is carried out in steam at about 800-900 degrees Celsius. In the transition region 18 where the bird's beak 22a is formed, the edge of the thermal oxide formed earlier masks the arsenic implant and therefore the S degree is lower and the oxide growth in that region is oxide 14 or oxide 22
less than the growth of.

In FIG. 4C, windows 19 are interspersed within the oxide in transition region 1418. Here, using photoresist as a mask, the oxide of the transition region 18 is etched down to the silicon, and then a thin oxide 19 is grown again as the tunnel window 19. During the oxidation of the tunnel window 19, the gate oxide 2
0 is somewhat long to about 350A. Optionally, tunnel window 1
A self-aligned N-type implant of 9 (eg phosphorus or arsenic) can be used for increased field plate breakdown voltage. Tunnel window 19 acts as a mask during this implant.

Since the surface of the transition region 18 is curved, the tunnel window 1
The width of 9 can be controlled by varying the length of time that the exposed area 1418 is etched.

A first N+ doped polysilicon layer is formed on the surface of the silicon slice. The first level polysilicon is defined using 7 photoresist to leave a strip extending in the X direction, some portion of which will become the floating gate 17. The ends of the polysilicon strips are
Covered with oxide by standard sidewall oxide process. Next, a coating 34 of oxide or nitride/oxide
is used to isolate floating gate 17 from υ1 control gate 12. A second polysilicon layer is deposited and N
+ doped and patterned in the X direction using photoresist to form the word line/Mtll gate 12. At the same time that the word line/control gate 12 is defined, the edges of the first level polysilicon are etched so that the X-extending edge of the floating gate is self-aligned with the edge of the control gate. It is noted that the drawings are not drawn to scale and thus the thickness of the first and second polysilicon layers is typically much thicker than the thickness of the oxide layers 19 and 20. sea bream.

If junction isolation is to be applied to the portion I1 region 23, a self-aligned ion implantation step may be applied to the overlapping polysilicon 1 and polysilicon 2, which are the word line/control gate 12 and floating gate 17. It is done using disease as a mask,
A separation region 23 is formed.

For this purpose, boron is
is injected in an amount of m-2. After annealing and oxidation, this implant forms a P0 region under ff[23, as does the channel stop implant under field oxide region 21.

As previously mentioned, one advantage of placing the tunnel window on the opposite side of the source from the drain is that mask alignment during fabrication is less critical compared to the method described in the previously mentioned application. . An additional important advantage is that the field plate junction between the buried N-t region and the substrate
The breakdown voltage is increased due to the fact that the overlying oxide is much thicker than the IOOA tunnel oxide across the N+ to P junction.

Additionally, the overall cell size can be reduced since tunnel alignment does not have to be considered. The 100A tunnel itself can be made narrower than the minimum dimension allowed by normal design rules.

The cell can also be "rescaled" upon substrate shrinkage or redesign.

Although the invention has been described with reference to embodiments, this description is not to be construed in any atypical sense. Various modifications of this embodiment, as well as other embodiments of the invention, will be apparent to those skilled in the art upon reference to this description. It is therefore intended that the appended claims cover any such modifications or embodiments that fall within the scope of the invention.

In connection with the above description, the following sections are further disclosed.

(1) An electrically erasable, electrically 70 grammable, floating gate memory cell comprising a source region and a drain region formed on the surface of a semiconductor substrate, each of said regions underlying a heavily doped region of the opposite conductivity type to that of the substance;
Each region is embedded under a relatively thick layer of silicon oxide on the surface, the source region is separated from the drain region by a channel region on the surface, and the cell is in the field. separated in one direction from adjacent cells by an oxide region, overlying the channel region, extending to silicon oxide over the source region, extending to silicon oxide over the drain region, and adjacent to the source and drain regions; a floating gate extending into the field oxide region, the floating gate being defined by a gate insulator to form a channel hole in the plane ft.
The tunnel g above the source region is separated from the force
a floating gate extending over the tunnel region;
Further, 11 of the tunnel insulators are separated from the resource region by a tunnel insulator, and the tunnel insulator is separated from the resource region by a tunnel insulator.
a control gate substantially thinner than the thickness of the gate insulator in the channel region and extending over and along the floating gate and over and along the source and drain regions; the gate is electrically erasable, including being separated from the floating gate by an insulating coating;
Electrically programmable floating gate memory
cell.

(2) In the memory cell described in item 1, the tunnel region is located on the channel side of the source region.

(3) For the memory sensor described in item 1 above. 1
3, the tunnel region overlies the source region at the intersection of the thick layer of silicon oxide and the field oxide.

(4) In the memory cell of paragraph 1 above, a tunnel region is on the source region at the intersection of the thick layer of silicon oxide and the field oxide, and a second tunnel region is , on the drain region where the thick layer of silicon oxide meets the field oxide.

(5) In the memory cell described in item 1 above, the semiconductor substrate is silicon, and the source ffi
The region and drain region are of N+ type.

(6) In the memory cell described in item 1 above, the floating gate and the control gate are polycrystalline silicon layers.

(7) In the memory cell of paragraph 1 above, the silicon oxide is significantly thicker than the gate insulator coating in the channel region.

(8) In the memory cell described in Section 7N, paragraph 1, the control gate is a part of a word line extending along the plane, and the source region and drain region are part of a word line extending perpendicularly to the word line. A portion of the bit line extending along the plane.

(9) In the memory cell described in item 1 above, the control gate is aligned at the edge of the floating gate.

(10) In the memory cell according to item 1 above, no contact is formed between the source or drain region and the overlying layer of conductor in the vicinity of the cell.

(11) In the memory cell described in the first rC4, the width U of the tunnel region can be adjusted by etching the oxide.

(12) In the memory cell described in item 1, the tunnel region is self-aligned.

(13) In the memory cell described in item 1 above,
The cell is separated from other cells in the other direction by a field oxide region.

(14) In the memory cell described in item 1 above,
The cell is separated from other cells in the other direction by a doped region under the trench.

(15) An erasable, electrically programmable, floating gate memory cell array comprising column lines in a face of the semiconductor body and row lines on said face, comprising: A layer of oxidation-resistant material is provided on the surface, and the structure is patterned, so that the source and drain regions of the surface and the channel region of the surface are covered, and the areas where the surface is not covered with the oxidation-resistant material are covered. growing an oxide coating on the surface, forming a first field oxide; growing a second field oxide on the surface; forming a thick thermal oxide coating on the source and drain regions; growing a gate oxide coating on the surface over the channel region to a first thickness that is significantly thinner than the first and second field oxides, and then forming a window in the gate oxide coating over the tunnel region. and regrowing a gate oxide on the window to a second thickness that is significantly less than the first thickness, thereby providing a tunnel window, the tunnel window forming a second field oxide layer over the source region. providing a first conductive layer adjacent to the surface and patterning the first conductive layer so as to overlie the channel region and overlie the second field oxide; also leaving a floating gate partially overlying the first field oxide, and a second conductive layer overlying the first conductive layer and insulated from the first conductive layer. forming an illtll gate on the floating gate, including column lines in the surface of the semiconductor body and row lines on the surface. (16) In the method described in item 15, the tunnel window is connected to the source f14k! ! The second field oxide on the channel side.

(17) In the method described in item 15 above, the Inaki tunnel window is above the source V4blt and between the first field oxide and the second field oxide.

(18) In the method described in the above item 15, the method described in the above 1
~ a tunnel window over the source region and between the first field oxide and the second field oxide; a second tunnel window over the drain region and between the first field oxide; and said second field oxide.

(19) In the h method described in item 15 above, the semiconductor is unused uP type silicon, and the impurity is N type silicon.

(20) In the method described in item 15 above, the first and second layers are polycrystalline silicon.

{21} The method of paragraph 15, wherein the first thickness is greater than the second thickness, and the first and second field oxide thicknesses are greater than the first thickness. Quite thick.

(22) In the method described in item 15 above, the impurity is separately implanted in the fls region below the tunnel window.

(23) An electrically erasable and electrically reprogrammable ROM or ct=p+<ov is formed using floating gate transistors without passes or split gates. The floating gate transistor may have a small self-aligned tunnel window (19) placed towards the opposite side of the source (15) from the channel and drain (16) in a contact free cell layout. , simplifying manufacturing and reducing cell dimensions. In this cell, the bit line (13) and the source/drain (15)
．． 16) The region is a relatively thick silicon oxide (14)
Buried below, the control gate (12) extends across both the thick silicon oxide (14) and the field oxide isolation region (22), which preferably couples the ilJl gate voltage to the floating gate (17). Ring. Programming and erasing is performed by the tunnel window area (19).

The tunnel window (19) has a thinner dielectric than the rest of the floating gate, causing Fowler-Nordheim tunneling.

[Brief explanation of drawings]

FIG. 1 is a top view of a small portion of a semiconductor chip with memory cells according to one embodiment. From FIG. 2a to FIG. 2e, one of the semiconductor devices in FIG. 1 is shown.
FIG. 3 is a front cross-sectional view taken along aa-a, bb, cc, dd, and ee. FIG. 3 is a schematic electrical wiring diagram of the cell shown in FIGS. 1 and 2a to 2e. Figures 4a to 4d show the second stage of the device in successive manufacturing stages of Figures 1 and 2a to 2e.
It is a front sectional view corresponding to figure a. FIG. 5 is a plan view of a small portion of a semiconductor chip with memory cells according to a second embodiment. 6a to 6b are front sectional views taken along lines aa and bb of the semiconductor device of FIG. 5. FIG. 7 is a front view of the arrangement, similar to the front view along line a--a of FIG. 1, but showing a tunnel window over both the source and drain regions. Explanation of main symbols 10; Memory cell 11: Silicon substrate 12: Word line/control gate 13: Bit i-line 15: Source T4 region 16: Drain region 17: Floating gate 18: i! i-transfer region 19: tunnel region 23: trench

Claims (1)

[Claims] (1) An electrically erasable, electrically programmable, floating gate memory cell comprising a source region and a drain region formed in a surface of a semiconductor body;
Each region is a heavily doped region of an opposite conductivity type to the underlying material of the substrate, and each region underlies a relatively thick layer of silicon oxide on the surface. embedded, the source region is separated from the drain region by a channel region on the plane, and the cell is separated in one direction from an adjacent cell by a field oxide region, overlying the channel region and having a source a floating gate extending into silicon oxide over the region, extending into silicon oxide over the drain region, and extending into the field oxide region adjacent the source and drain regions, the floating gate being bounded by a gate insulator to the field oxide region; a tunnel region over the source region, separated from a channel region of the source region;
a floating gate extends over the tunnel region and is separated from the resource region by a tunnel insulator, the thickness of the tunnel insulator in the tunnel region being substantially less than the thickness of the gate insulator in the channel region;
and a control gate extending along the plane above the floating gate and above the source and drain regions, the control gate being separated from the floating gate by an insulating coating. memory cell with a floating gate that is electrically programmable.