JPH0290243A - Microprogram logic verification method - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a microprogram logic verification method, and particularly to a microprogram emulation method suitable for verifying microprogram logic in various execution environments. be.

[Conventional technology]

Conventionally, in order to pseudo-execute H/W logic at the LSI gate level, as shown in FIG. After the processing of the microprogram 91 is converted by the conversion processing program 92, the microprogram is verified by a method of performing pseudo execution at the signal level.

In addition, related microprogram verification methods include:
For example, Japanese Patent Application Laid-Open No. 62-290944.

As described in Japanese Patent No. 62-293357, there is a known method of verifying the validity of logic by running a microprogram on a target computer system or a gate-level logic simulator.

[Problem to be solved by the invention]

The above conventional technology assumes the existence of a target computer system or gate-level logic simulator, and no consideration is given to microprogram verification before the system or simulator is completed, and even before the hardware logic specifications are determined. do not have.

The purpose of the present invention is to construct a pseudo hardware environment at the time when microprogramming specifications are determined, and to perform early logic verification of microprograms efficiently and with high precision, in view of the points that have not been considered in the past. The purpose of the present invention is to provide a microprogram logic verification method.

[Means to solve the problem]

To achieve the above objects, the present invention provides a microprogram logic verification method that runs a microprogram in a pseudo environment equivalent to a target computer system and performs logic verification. - It is characterized by having means for storing sources, means for storing microprogram specification information, means for setting a test environment, and means for pseudo-executing microprogram sources on an order-by-order basis.

Further, the above hardware information consists of control interface information between the hardware and the microprogram, hardware registers, latches, and memory, and the means for setting the above test environment is the means for storing the test program and the computer system. It is characterized by comprising means for interpretively pseudo-executing a group of instructions that are not subject to microprogram emulation.

Furthermore, the means for pseudo-executing the microprogram source on an order-by-order basis includes means for initializing settings based on hardware information, means for controlling the timing of the pseudo operation, and means for counting microprogram source steps. Another feature is that it includes means for registering executed source steps.

[Effect]

In the present invention, when pseudo-executing a microprogram, the microprogram source step is divided into orders, specification information corresponding to the microinstructions issued in each order is extracted, and pseudo processing at the data transfer level is performed accordingly. implement.

Thereby, the microprogram can be verified at the time when the microprogramming specifications are determined, without waiting for the hardware logic specifications to be determined. Furthermore, since processing is simulated on an order-by-order basis, microprograms can be verified in detail at the order level.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a microprogram logic verification system (microprogram emulation system) showing one embodiment of the present invention.

In FIG. 1, 11 is a test program file that stores a program for testing the target function, 12 is an instruction interpreter, 13 is an initial setting section that sets initial conditions (test environment), and 14 is a microprogram source. 15 is a post-processing unit that performs interrupt processing, updating orders, updating microprogram source step read addresses, etc.; 16 is a microinstruction simulation unit that executes operations when simulating each microinstruction; A processing control unit that has a function for specifying a function, a function for interacting with an operator, and performs various process controls.

17 is an interface information file that stores control interface information between the hardware and the microprogram, 18 is a microprogram source information file that stores the microprogram source, and 19 is a microprogram that stores the microprogram specification information. Specification information file, 20 is a pseudo register/latch realized by software as the register/latch of the target computer system, 21 is a pseudo memory realized by software as the memory of the target computer system, 22 is for interactively performing microprogram logic verification terminal, 23
is a printer that outputs the processing results.

FIG. 2 is a diagram showing an example of the contents of the interface information file 17 shown in FIG. 1.

As shown in FIG. 2, the interface information file 17 contains the mnemonic and instruction code corresponding to the target instruction,
Hardware setting information (initial values of pseudo registers/latches) for the instruction to be executed.

initial values of the pseudo memory), etc. are stored.

FIG. 3 is a diagram showing an example of the contents of the microprogram source information file 18 shown in FIG. 1.

The microprogram source information file 18 contains the third
As shown in the figure, the source steps of the microprogram (self address, branch address, process 1 (order 1), process 2 (order 2), . . . ) are described. This source information is not limited to this example, and can be written in a form depending on the microprogramming language used.

FIG. 4 is a diagram showing an example of the contents of the microprogram specification information file 19 shown in FIG. 1.

As shown in FIG. 4, the microprogram specification information file 19 contains microinstruction names and operation descriptions corresponding to each order. The microprogram emulation operation of this embodiment will be explained below.

After loading a program for testing the target function into the pseudo memory 21 from the test program files 1 and 1, when the instruction interpreter 12 issues a corresponding microprogram execution instruction to start pseudo execution, the initial conditions for executing the instruction are set to the interface. The information is extracted from the information file 17, and the initial setting unit 13 registers it in the pseudo register/latch 2o and the pseudo memory 21. Microinstruction simulator 14
Then, the microprogram source information is read out step by step from the microprogram source information file 18, divided into order units, and corresponding specification information is read out from the microprogram specification information file 19 in accordance with the microinstructions issued for each order. According to the specifications, data transfer of the pseudo register/latch 20 and the pseudo memory 21 is executed. The post-processing unit 15 performs interrupt processing when an interrupt factor occurs in the micro-instruction simulating unit 14, updates the order, and updates the micro-program source step read address, and when all the orders of the corresponding step are processed, the next micro When it is detected that the program source step read address has been set and the processing of all the relevant steps has been completed, control is returned to the instruction interpreter 12 as execution of the target instruction has ended. In the processing control unit 16, the terminal 22
In response to a request for human intervention from
Pseudo register/latch 20° at that point Pseudo memory 2
1 is output or written to the terminal 22 or printer 23.

FIG. 5 is a processing flowchart of the initial setting section 13 in FIG. The initial setting process will be described below according to the flow shown in FIG.

Step 501: Read the hardware environment setting information at the time of issuing the instruction from the interface information file 17.
), the corresponding pseudo register, latch, and pseudo memory are written (step 502).

FIG. 6 is a processing flowchart of the microinstruction simulator 14 in FIG. 1. The microinstruction simulation will be explained below according to the flow shown in FIG.

Step 601): Read the microprogram step from the microprogram source information file 18.
, this is divided into order units (step 602), the corresponding microinstruction operation specifications are sequentially read from the microprogram specification information file 19 (step 603), and data is transferred between pseudo registers, latches, and pseudo memories according to the operation specifications.

FIG. 7 is a processing flowchart of the post-processing section 15 in FIG. The post-processing will be explained below according to the flow shown in FIG.

The microinstruction simulator 14 determines whether an interrupt factor has occurred (Step 701), and if so, sets the interrupt flag (Step 702). After all orders are completed (Step 703), the interrupt flag is turned ON. If so (step 705).

Set the break-in destination address (step 710),
Finish the process. Further, it is determined whether all orders have been completed (step 703), and if all orders have not been completed, the order read address is updated (step 704). If the interrupt factor is OFF (step 705), it is determined whether all steps have been completed (step 706); if not all steps have been completed, the step read address is updated (step 707).

If all steps have been completed, the primary execution address is set to the next address of the target instruction (step 708), and control is returned to the instruction interpreter (step 709).

FIG. 8 is a processing flowchart of the processing control section 16 in FIG. 1. Processing control will be explained below according to the flow shown in FIG.

The addresses of the processing steps are registered in the processing order until the processing ends (step 8o1). If an operator intervention request or address conveyor stop state occurs (steps 802, 803), an operator request from the terminal (805
), processes such as conveyor stop address designation, pseudo register or latch information display, rewriting, pseudo memory information display, rewriting, etc., and further processing of test data from the processing steps registered in the process of step 801, microprogram. Processing such as performance value calculation and display processing and designation of data transfer timing during microinstruction simulation are executed (step 804).

In this manner, in this embodiment, the microprogram can be verified at the time when the microprogramming specifications are determined, without waiting for the hardware logic specifications to be determined.

〔Effect of the invention〕

As explained above, according to the present invention, the microprogram operating environment can be easily set when the microprogramming specifications are determined, so the microprogram can be executed regardless of the hardware logic development progress of the target computer system. It becomes possible to perform verification while operating, which enables earlier development of microprograms and more efficient and highly accurate verification compared to the past.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a microprogram logic verification method showing an embodiment of the present invention, FIG. 2 is a diagram showing an example of the contents of the interface information file shown in FIG. 1, and FIG.
4 is a diagram showing an example of the contents of the microprogram specification information file in FIG. 1. FIG. 5 is a processing flowchart of the initial setting section in FIG. Figure 6 is a processing flowchart of the microinstruction simulator in Figure 1;
7 is a processing flowchart of the post-processing section in FIG. 1, FIG. 8 is a processing flowchart of the processing control section in FIG. 1, and FIG. 9 is a diagram for explaining a conventional program logic verification method. 11: Test program file, 12: Instruction interpreter, 13: Initial setting section, 14: Micro instruction simulation section, 15: Post processing section, 16: Processing control section, 17: Interface information file, 18: Micro program source information file , 19: Microprogram specification information file, 20: Pseudo register/latch, 21: Pseudo memory, 22: Terminal, 23: Printer. Patent applicant: Hitachi, Ltd.

Claims (1)

[Scope of Claims] 1. A verification method in which a microprogram is run in a pseudo environment equivalent to a target computer system and logic verification is performed, which includes means for storing hardware information, means for storing microprogram source, and means for storing program specification information; means for setting a test environment;
A microprogram logic verification method characterized by comprising means for pseudo-executing microprogram source on an order-by-order basis. 2. The microprogram logic verification system according to claim 1, wherein the hardware information comprises control interface information between hardware and the microprogram, and hardware registers, latches, and memories. 3. The means for setting the test environment comprises means for storing a test program and means for interpretively executing a group of instructions that are not subject to microprogram emulation in the computer system. 2. The microprogram logic verification method according to claim 1. 4. The means for pseudo-executing the microprogram source on an order-by-order basis includes means for initializing based on hardware information, means for controlling the timing of the pseudo operation, and means for counting microprogram source steps. 2. The microprogram logic verification method according to claim 1, further comprising means for registering executed source steps.