JPH0287881A - Driving circuit of matrix type display device - Google Patents

Abstract

PURPOSE:To execute an interlace display in which a residual image of an indentation is not viewed even in the case of a moving image and to display an image whose vertical resolution is high and bright by writing one horizontal video signal in one field line during one horizontal period, and writing a signal obtained by changing a level of a video signal in the other field line. CONSTITUTION:The title circuit is provided with a data switching means 16 for switching video data from a first data holding means 12 and video data whose level is converted from second data holding means 13, 15 at every 1/2 horizontal period, and supplying them to a picture element line in the longitudinal direction of a display body 11. Accordingly, during one horizontal period, a video signal is written in a line corresponding to one field, a video signal whose signal level is changed is written in a line corresponding to the other field, and the lines of both the fields are displayed simultaneously in one horizontal period. In such a way, even in the case of a moving image, it is not displayed in indentation, and also, an image of a high quality whose resolution is high and bright can be displayed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a drive circuit for a 71-lix type display device suitable for performing interlaced display.

(Prior Art) Conventionally, a display device for displaying images is a CRT.
The mainstream was to use However, in recent years, small, lightweight, and thin flat display devices using plasma or liquid crystal have begun to be widely used for image display in personal computers, word processors, television receivers, and the like. Along with this, there is a demand for a display device that can display a screen with high resolution and high quality.

Generally, as a flat display device, one in which a matrix electrode is used in the display (hereinafter referred to as a matrix type display S device) is used. The display used in this device has wires running in the vertical and horizontal directions, and electrodes for forming images are placed at the intersections of the wires. These electrodes correspond to the pixels that make up the image, and when signals are applied to the vertical and horizontal wires, the signals are applied to the intersecting electrodes, causing the elements on the electrodes to emit light or transmit light, thereby displaying the image. In other words, the number of intersections between vertical and horizontal wiring is the horizontal and vertical solution! & Determine degree.

Therefore, if you want to increase the resolution, you just need to increase the number of vertical and horizontal wirings.

As an example, a case will be described in which an interlaced video signal such as an NTSC color television signal is to be displayed in high resolution on a matrix display device.

For example, when performing interlaced display on a display with 480 pixels vertically as shown in FIG. 4, the signals of the first field are 1, 3, 5, . ..., 479, and so on into the odd numbered horizontal lines, and the second field signal is 2, 4, 6, etc. ..., 480, etc., are written on even numbered horizontal lines.

In this way, one field of video consisting of 240 horizontal lines can be displayed with 480 full lines.

Next, regarding the display time of one field, in the case of a CRT, since the phosphor of the CRT is illuminated with an electron beam and the phosphor begins to emit light, the afterglow time of the phosphor is the display time. ·bawl. If the afterglow time of this phosphor is shorter than the time required to write one field, only one field will always be displayed. However, in the case of a matrix type display, the display time of one field is determined by the charge retention time of the electrode of each pixel, and in the case of a liquid crystal, etc., it is very long and takes more than the time to write one field. Therefore, when writing to one field, the other field is always displayed on the display, so the first field and the second field are displayed on the display at the same time.

For this reason, when displaying images on a matrix type liquid crystal display, for example, images with no movement such as still images will be displayed in high quality with very high resolution, but images with movement will be displayed in the first and second fields. Since there is a time difference between the fields, if they are displayed at the same time, the image displayed in the previous field will be displayed as an afterimage together with the image in the next field. FIG. 5 shows display examples for still images and moving images. In FIG. 5, (a) shows the display of a still image,
(b) shows the display of a moving image. The moving image shows a case in which an object moves 1h to the right, and this phenomenon in which a moving object is displayed in a jagged 1F is called the frame memory effect.

Therefore, as described in Japanese Patent Application Laid-Open No. 62-250776, when inputting and outputting a video signal to one field, if 1 is written so as to write a black level signal to the other field, which one Since only one field is displayed, the frame memory effect described above is eliminated.

However, in this display method, the video signal is always displayed on only half the area, so the brightness of the screen is reduced by half.

Furthermore, if the same metering signal is written in place of the black level signal in order to increase the brightness, the brightness will increase but the vertical resolution will decrease.

(Problem to be Solved by the Invention) As described above, in the conventional matrix display device, in order to eliminate the frame memory effect, 11 video signals are input into one field line, and the black level is input into the other field line. There was a problem in that when interlaced display was performed by writing a signal of .

SUMMARY OF THE INVENTION An object of the present invention is to solve this problem, and to provide a drive circuit for a matrix display device that can display a high-quality image with no afterimage, high vertical resolution, and high brightness when performing interlaced display. That is.

[Structure of the Invention] (Means for Solving the Problems) A drive circuit for a matrix display device of the present invention includes a display body configured by arranging a plurality of pixels in a matrix shape vertically and horizontally, and an image for one horizontal period. a first data holding means for sampling and holding a signal at a predetermined clock; a level converting means for outputting a video signal with a changed level of the video signal; and a video signal with a changed signal level from the level converting means. second data holding means for sampling and holding the video data from the first data holding means and the second data holding means at a predetermined clock;
The level-converted video data from the data holding means of
data switching means that switches and supplies data to the vertical pixel lines of the display body every 1/2 horizontal period; line selection means for sequentially selecting each period and displaying the video data from the data switching means and the level-converted video data alternately one line at a time in the horizontal pixel lines; Ru.

(Function) In the present invention, during one horizontal period, a video signal is written to a line corresponding to one field, and a video signal with a changed signal level is written to a line corresponding to the other field. The lines of both fields are 1.
Since the images are displayed simultaneously in the horizontal period &:, even in the case of moving images, they will not be displayed jaggedly.

Furthermore, the brightness of the screen can be made brighter compared to when a black level signal is written in, and the resolution can also be increased compared to when the same video signal is written to two lines. Therefore, a bright, high-quality image with high resolution can be displayed.

(Example) Hereinafter, the present invention will be explained based on the example shown in the drawings.

FIG. 1 is a block diagram showing a driving circuit of a matrix type display device according to an embodiment of the present invention.

The drive circuit shown in this figure includes the liquid crystal panel 11. First sample and hold circuit 12. Second sample and hold circuit 1
3. Level conversion circuit 14. Data holding circuit 15. Signal switching circuit 16. First Y-controlled shift register circuit 17.
It is composed of a second Y-controlled shift register circuit 18. The liquid crystal panel 11 is constructed using electrodes arranged in a matrix, and the first sample bold circuit 1
2 is a circuit that holds the video signal (video) of one horizontal line, and the second sample hold circuit 13 is
This is a circuit that holds a signal obtained by changing the level of a line video signal (Video).

The level conversion circuit 14 is a circuit that converts the level of the video signal (V i deo) by adjusting the gain and supplies it to the second sample hold circuit 13 .

The data holding circuit 15 is a second number hold circuit 1
This circuit temporarily holds the video signal from the second sample and hold circuit 13 in order to shift the output of the second sample and hold circuit 13 from time to time with respect to the output of the first sample and hold circuit 14. The signal switching circuit 16 is the first sample hold circuit 1
This circuit switches between the 1-line video signal from the data holding circuit 15 and the 1-line video signal from the data holding circuit 15. 1st Y
Control shift 1 to register circuit 17 control the vertical write line of the first field, and control the vertical write line of the first field.
it, II Ijll shift register circuit 18 is the second
The vertical writing line of the field is 1tlj I
II.

In the above device, the video signal @ (Video) corresponding to each pixel of one horizontal line is clocked at 5PCK.
Sampling is performed by I and held in the first number hold circuit 12. Further, the video signal (Video
) is converted by the level conversion circuit 14, and the video signal corresponding to each pixel is sampled by the sample clock 5PGK2 and held in the second sample hold circuit 13. The video signal held in the second sample hold circuit 13 is transferred to the data hold circuit 15 by the signal VHOLD. First lean pull hold circuit 12
The output of VOE and the signal output from the data holding circuit 15 are input to the signal switching circuit 16, and when the signal VOE is at the logic H level, the output from the sample hold circuit 12 is selected.
Further, when the signal 5vOE is at the logic H level, the signal from the data holding circuit 15 is selected and output. In addition, the signal VOE
When signal 5VOE is not at H level, it becomes a high impedance output. The signal output from the signal switching circuit 16 is input to the vertical wiring of the liquid crystal panel 11, and becomes display data for one horizontal line. The first and second Y control shift register circuits 17 and 18 determine the horizontal line for video writing, and write start signals YST1. YST2 is shifted by shift clock YCK. Output signal Y1
゜Y2. Y3. ... is input to the horizontal wiring of the liquid crystal panel 11 to write horizontal lines.

Next, the above circuit operation will be explained in detail with reference to FIG. 2, which shows the write timing. Writing to the liquid crystal panel 11 is performed by writing one horizontal line of the video signal and one horizontal line obtained by converting the level of the video signal in a time corresponding to one horizontal scanning period (1H). The video signal (Video) for one horizontal line has a sample clock of 5PCK1.5P.
GK2 samples the first data as hold data.
゜Holded in the second sample and hold circuit 12.13. Then, this hold data (shaded area) is not read out during a period corresponding to approximately the horizontal blanking period. The output of the first sample and hold circuit 12 and the signal obtained by holding the output of the second sample and hold circuit 13 in the -H data holding circuit 15 are input to the signal switching circuit 16, and writing to the liquid crystal panel 11 is performed. It will be done. In the m writing of the first field, 1 horizontal video signal is supplied to the vertical wiring by the signal VOE, written to the Yl horizontal line, and then the level-converted signal of the video signal is sent to the vertical wiring by the signal 5VOE. Supply to the wiring and write to the horizontal line of Y2. Similarly, Y3, Y5. One horizontal video signal is also written for each horizontal line, and Y
4. Y6. . . . The level-converted signal of the video signal is also inserted into the horizontal lines. In writing the second field, 1 horizontal video signal is supplied to the vertical wiring by the signal VOE, written to the Y2 horizontal line, and then the level-converted signal of the video & signal is sent to the vertical wiring by the signal 5VOE. and write to the horizontal line of Yl. Similarly, Y4. One horizontal video signal is also written to the horizontal lines of Y6, . . .
3. Y5. A signal obtained by converting the level of the video signal is also applied to the horizontal line. In other words, when writing to the first field, a signal obtained by converting the level of the video signal is written to the second field, and when writing to the second field, a signal obtained by converting the level of the video signal is written to the first field. do.

The timing of the signal VOE is such that the sample and hold circuit 12 holds one horizontal video signal and outputs it until the next video signal, and stores the hold data in the wiring capacitance of the vertical wiring of the liquid crystal panel 11.

Change this to Y fill III shift register 17.1
8 output signal Y1.8. Y2. Y3. Writing is performed by ..., but writing requires (+/2) H period time, and a signal is output during that period. In addition, the signal 5VOE
Similarly, the data holding circuit 15 stores the level-converted video signal in the wiring capacitance, and the signals Y1, Y2 .
Y3. ... is output and written for (1/2)l-(period.

FIG. 3 is a graph showing the relationship between the level conversion ratio of the video signal and the screen T(degree and !l!DCW? image degree) in the above-mentioned actual example.The horizontal axis represents the gain of the level conversion of the circuit 14. The IIl axis shows resolution and measurement.The gain is 100% when the video signal level is maximum and 0% when it is minimum, and the measurement is when the video signal is added to 2 lines (gain 1).
00% case) is set as 100%, and a case where the video signal is added only to one line (when the gain is 0%) is set as 0%. Regarding the resolution, the resolution when the gain was 0% was defined as 100%, and the resolution when the gain was 100%, which was the addition of the video signal to 2 lines, was defined as 0%. As you can see from this graph, when the gain is 0%, the resolution is maximum, but the brightness is minimum, and the gain is maximum (10%).
0%), the brightness is maximum, but the resolution is reduced. Therefore, if you want to increase the brightness by 1, increase the gain, and if you want to increase the resolution, decrease the gain. The gain of this level conversion is 10% to 90% depending on the display usage conditions.
It is best to decide between

[Effect of the invention] As described above, according to the present invention, in the darkness of one horizontal period,
Write one horizontal video signal to one field line,
Since a signal with a different level of the video signal is input to the other field line, interlaced display without visible jagged J afterimages is possible even in moving images, and vertical resolution is achieved.
& Can display high quality and bright images.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a drive circuit for a matrix display device according to an embodiment of the present invention, FIG. 2 is a timing diagram for explaining the operation of the circuit shown in FIG. 1, and FIG. FIG. 4 is an explanatory diagram for explaining the interlaced display, and FIG. 5 is an explanatory diagram for explaining the drawbacks of the conventional interlaced display. . 11...Liquid crystal panel, 12.13...Sample hold circuit, 14...Level conversion circuit, 15...Data holding circuit, 16...
Signal switching circuit, 17.18...Y till 'ml shift register circuit. Y5 (Y6) A, and I3@2 feel in parentheses indicates the 4th case in the display.

Claims (1)

[Scope of Claims] A display body configured by arranging a plurality of pixels in a matrix shape vertically and horizontally; a first data holding means for sampling and holding a video signal of one horizontal period at a predetermined clock; a level converting means for outputting a video signal with a changed level of the video signal; a second data holding means for sampling and holding the video signal with a changed signal level from the level converting means at a predetermined clock; The video data from the first data holding means and the second data holding means
The level-converted video data from the data holding means of
data switching means that switches and supplies data to the vertical pixel lines of the display body every 1/2 horizontal period; Line selection means for sequentially selecting each period and displaying the video data from the data switching means and the level-converted video data alternately, one line at a time, on the horizontal pixel lines. A drive circuit for a matrix type display device.