JPH027558A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce occurrence of stress on oxidation by using diffusion from BSG and PSG and using the BSG and PSG used for diffusion as a field oxide film. CONSTITUTION:A P-well 2 and an N-well 3 are already formed on a substrate 1, a BSG 10 and a CVDSiO2(1)11 are continuously accumulated to form a field oxide film within the P-well 2 and is etched leaving an isolating region, and then a PSG 12 and a CVDSiO2(2)13 are continuously accumulated to form the field oxide film of the N-well 3 and is etched leaving a separation area. A CVDSiO2(3)14 is accumulated over the entire surface for performing entire- surface etching and a side wall 15 is formed to prevent the PSG and BSG from becoming a diffusion source at areas except those needed and entering and reduction of film on etching from occurring. Also, since a channel stopper 9 is naturally diffused by the succeeding heat treating, after heat treatment is not required in many cases, thus eliminating oxidation process for a long time and reducing occurrence of stress which becomes a problem in the selection oxidation method, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to the structure of a semiconductor integrated circuit device and its manufacturing method, and in particular to a highly integrated complementary metal oxide silicon (0MO8) semiconductor having fine device dimensions. The present invention relates to the structure of the device and its manufacturing method.

(Prior art) MO3 semiconductor integrated circuit devices require regions to separate each device.
ld), and a high diffusion layer region called a channel stopper is usually formed in the underlying silicon layer. Hereinafter, a conventional example of a method for forming this isolation region will be explained with reference to the drawings. Figure 2 shows selective oxidation (LOGO8
) method for forming a field oxide film and a channel stopper layer.

In FIG. 2(a), a P well 2 and an N well 2 are placed on an N substrate 1.
After the well 3 is formed and the base oxide film 4 and 5i3N45 are formed, 5i is formed according to the prescribed pattern of resist (1) 6.
3N45 is etched and P" (phosphorus) ions are implanted. At this time, an N well does not necessarily have to be formed.

Next, in FIG. 2 (b5, only the N-well region is exposed to resist (
2) After protection by 7, B'' (boron) is ion-implanted. At this time, B''' is implanted at a concentration of 5 to 10 times the P+ concentration, so the area where Si and N45 in the P-well region have been etched is the P-well. The target region of the N-well region becomes a darker N-type than the N-well.

Next, in FIG. 2(c), when resist (1) 6 and resist (2) 7 are removed and oxidized, and 5L3N45 is removed, field oxide film 8 and channel A stopper 9 is formed.

(Problems to be Solved by the Invention) ■ A conventional example in which a field oxide film and a channel stopper layer can be formed using the ocos method with the minimum number of steps is 1.5
It was a method with high utility value up to ~2.0 μm design rule, but +1. Since channel stopper ions are implanted before field oxidation, they are deeply diffused by heat treatment during oxidation, and B (boron) in particular is segregated. This reduces the oxide film interface concentration.

b. Stress occurs on Si3N4 edges during oxidation, which tends to cause leakage.

There is a problem. If the amount of ion implantation is increased to increase the concentration of the channel stopper, the channel stopper will also enter the channel portion, causing a problem that the threshold voltage will become unstable.

Furthermore, the problem with stress during oxidation becomes greater as the degree of integration increases and as the structure becomes finer.

(Means for solving problems) In order to solve the above problems, the present invention.

a. Diffusion from BSG (boron glass) and PSG (phosphorus glass) is used to prevent the impurity concentration at the oxide film interface from decreasing.

b. To reduce the number of masks and eliminate errors,
BSG and PSG used for diffusion are used as field oxide films.

By using a C6 deposited oxide film, stress generation is reduced.

(for production) BSG as a means to solve the above problems.

Since diffusion from PSG is used and there is no oxidation step, the concentration and depth of the channel stopper layer can be optimized.
Furthermore, the occurrence of heat stress and oxidative stress is reduced.

(Example) An example of the present invention will be described below with reference to the drawings. In this example, in order to prevent impurities from diffusing outside the desired regions, BSG, PSG, and C.
VD (Chemical Vapor Deposition) Sin2 is used as a two-layer film, and sidewalls are also formed to cover the sides.

In FIG. 1(a), a P well 2 and an N well 3 have already been formed on a substrate 1, and first, in order to form a field oxide film in the P well 2, BS G 10 (+0
000-500n and CV D 5lot (1) 11
(200 to 600 nm) is shown continuously deposited and etched leaving one isolated region.

Next, in FIG. 1(b), in order to form the field oxide film of the N well 3, P S G12 (100 to 500
nm) and CV DSi02(2)13(200-500
A continuous deposition of 100 nm) is shown followed by etching leaving isolated regions. Although the order of P-well 2 and N-well 3 may be reversed, in this example, P-well 2 is etched first because PSG has the fastest etching speed and can reduce the film loss of CV D 5102 (1). I made it.

In Figure 1(c), the entire surface! : CV D Sin□(3
) 14 is deposited to a thickness of 300 to 700 nm, and the entire surface is etched (etched back) to form sidewalls 15. This sidewall will be made of PSG in the subsequent process.
This is to prevent BSG from becoming a diffusion source in areas other than necessary, and at the same time to prevent it from entering during etching and from reducing the film. This sidewall formation will be referred to as LDD
(Low impurity concentration drain) If there is a forming step, it is carried out in exactly the same way, so it does not necessarily have to be done immediately. Furthermore, since the channel stopper 9 naturally diffuses during subsequent heat treatment, immediate heat treatment is often unnecessary. Furthermore, C.V.
Si, N, or a film can also be used instead of DSiO2 (1), (2), or (3), or in combination with these.

(Effects of the Invention) As described above, in the present invention, by using BSG and PSG as the diffusion source of the channel stopper, it is possible to form a shallow diffusion layer with a relatively high concentration, and at the same time, CV D 5i
Since the field oxide film is constituted by the N2 film, a long oxidation process is not necessary, and stress, which is a problem in selective oxidation, is less likely to occur.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the present invention, and FIG. 2 shows a conventional example. Fig. 1...Substrate, 2...P well, 3...N well, 4... Base oxide film, 5...Si3N4゜6
...Resist (1), 7...Resist (2)
. 8...Field oxide film, 9...Channel stopper, 10-BSG, 11"・CV DS
iO□(1), 12...PSG, 13...CV
D5iO□(2), 14=-CV 03j02(3),
15-...Side wall. Patent applicant: Matsushita Electronics Co., Ltd. Figure 2

Claims (3)

[Claims] (1) A region having a second conductivity type and a region having a first conductivity type are formed in a semiconductor substrate having a first conductivity type, and each region has the conductivity type. 1. A semiconductor device, wherein an element isolation portion therein is comprised of a silicon oxide film containing an impurity having the same conductivity type as the region, and a diffusion layer diffused from the silicon oxide film. (2) The semiconductor device according to claim 1, wherein the silicon oxide film containing impurities is covered on the top and both sides by silicon oxide films containing no impurities. (3) Step of forming a P-well, an N-well, or both a P-well and an N-well on a semiconductor substrate, depositing boron glass and silicon oxide films above both wells and etching them according to a predetermined pattern. or a step of depositing phosphorus glass and a silicon oxide film and etching it according to a predetermined pattern; or a step of depositing a silicon oxide film again and etching the entire surface, leaving only the sidewalls at the stepped portions. A method for manufacturing a semiconductor device.