JPH027459A - Semiconductor package - Google Patents
Semiconductor packageInfo
- Publication number
- JPH027459A JPH027459A JP63157561A JP15756188A JPH027459A JP H027459 A JPH027459 A JP H027459A JP 63157561 A JP63157561 A JP 63157561A JP 15756188 A JP15756188 A JP 15756188A JP H027459 A JPH027459 A JP H027459A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- capacitors
- semiconductor
- semiconductor chip
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H10W72/536—
-
- H10W72/5363—
-
- H10W72/5449—
-
- H10W90/753—
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体パッケージに関し、特に、リードフレ
ームを用いたプラスチックモールド封止によるパッケー
ジの補遺に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to semiconductor packages, and more particularly to package supplements with plastic mold encapsulation using lead frames.
従来の技術
従来、リードフレームを用いたプラスチックモールド封
止のパッケージは、１個の半導体チップをリードフレー
ムにマウントし、その半導体チップよりボンデングワイ
ヤによりリード部へ接続されていた。2. Description of the Related Art Conventionally, in a plastic mold-sealed package using a lead frame, one semiconductor chip was mounted on the lead frame, and the semiconductor chip was connected to lead portions by bonding wires.
発明が解決しようとする課題
しかしながら、広帯域増幅器等、アナログＩＣでは、そ
の回路中、又は入出力に比較的大容量のコンデンサを必
要とするが、半導体チップ上に大容量のコンデンサを形
成することは内錐であり、パッケージの外部にチップコ
ンデンサ等を用いて回路を構成していた。Problems to be Solved by the Invention However, analog ICs such as wideband amplifiers require relatively large capacitors in their circuits or for input and output, but it is difficult to form large capacitors on semiconductor chips. It was an inner cone, and the circuit was constructed using chip capacitors etc. on the outside of the package.
本発明は従来の上記実情に鑑みてなされたものであり、
従って本発明の目的は、従来の技術に内在する上記課題
を解決することを可能とした新規な半導体パッケージを
提供することにある。The present invention has been made in view of the above-mentioned conventional situation,
Accordingly, an object of the present invention is to provide a novel semiconductor package that makes it possible to solve the above-mentioned problems inherent in the conventional technology.
発明の従来技術に対する相違点
上述した従来の半導体パッケージに対し１本発明は、チ
ップコンデンサをも半導体パッケージに内蔵するという
相違点を有する。Differences between the present invention and the prior art The present invention differs from the conventional semiconductor package described above in that a chip capacitor is also built into the semiconductor package.
課題を解決するための手段
前記目的を達成する為に１本発明に係る半導体パッケー
ジは、リードフレーム上にチップコンデンサを搭載し、
半導体チップ上より前記チップコンデンサ上ヘボンデン
グワイヤで接続して構成される。Means for Solving the Problems In order to achieve the above object, a semiconductor package according to the present invention includes a chip capacitor mounted on a lead frame,
The chip capacitor is connected from the semiconductor chip to the chip capacitor using a bonding wire.
実施例
次に１本発明をその好ましい各実施例について図面を参
照して具体的に説明する。Embodiments Next, preferred embodiments of the present invention will be specifically explained with reference to the drawings.
第１図は本発明による第１の実施例を示し、プラスチッ
クモールド樹脂封入前のリードフレームの平面図である
。FIG. 1 shows a first embodiment of the present invention, and is a plan view of a lead frame before being encapsulated with a plastic mold resin.
第１図を参照するに、チップマウント部１１上へ半導体
チップ１２がマウントされ、２ＷＪ所のり−ド１３」二
へチップコンデンサ１４がマウントされ、それらのコン
デンサ１４は半導体チップ１２にボンデングワイヤ１５
にて接続されている。ここでチップコンデンサ１４は、
セラミックコンデンサ等、小型で比較的大容量を有する
ものであり、上面及び底面を電極としているものを使用
する。Referring to FIG. 1, a semiconductor chip 12 is mounted on a chip mount part 11, and chip capacitors 14 are mounted on a board 13'' at 2WJ.
It is connected at Here, the chip capacitor 14 is
A small capacitor with a relatively large capacity, such as a ceramic capacitor, whose top and bottom surfaces are used as electrodes is used.
本節１の実施例では、増幅器の入出力結合コンデンサあ
るいは高周波接地用コンデンサとしての利用に適してい
る。The embodiment of Section 1 is suitable for use as an input/output coupling capacitor of an amplifier or a high frequency grounding capacitor.
第２図は本発明による第２の実施例を示し、プラスチッ
クモールド樹脂封入前のリードフレームの平面図である
。FIG. 2 shows a second embodiment of the present invention, and is a plan view of a lead frame before being encapsulated with a plastic mold resin.
第２図を参照するに、ここでは、チップコンデンサ１４
は、チップコンデンサマウント部１６上にマウントされ
て、それぞれに半導体チップ１２上よりボンデングワイ
ヤ１５により接続されている。Referring to FIG. 2, here, the chip capacitor 14
are mounted on the chip capacitor mounting section 16, and connected to each other from above the semiconductor chip 12 by bonding wires 15.
本節２の実施例は、多段増幅器の股間結合コンデンサ等
の利用に適したものである。The embodiment of Section 2 is suitable for use as a crotch coupling capacitor of a multi-stage amplifier.
発明の詳細
な説明したように、本発明の半導体パッケージを使用す
ることで、プリント基板上への実装時に部品点数を減ら
すことが可能であり、また第２の実施例では、パッケー
ジのピン数を減らす効果もあり、パッケージのより小型
化が可能となる。As described in detail, by using the semiconductor package of the present invention, it is possible to reduce the number of parts when mounting on a printed circuit board, and in the second embodiment, the number of pins of the package can be reduced. This also has the effect of reducing the amount of heat, making it possible to further downsize the package.
第１図は本発明による第１の実施例を示す平面図、第２
図は本発明による第２の実施例を示す平面図である。
１１、、、チップマウント部、１２．、、半導体チップ
、１３、、、リード部、１４．、、チップコンデンサ、
１５．、。
ボンデングワイヤ、 １６．、、チップコンデンサマウ
ント部FIG. 1 is a plan view showing a first embodiment of the present invention, and FIG.
The figure is a plan view showing a second embodiment according to the present invention. 11. Chip mount section 12. , , Semiconductor chip 13 , , Lead part 14 . ,,chip capacitor,
15. ,. Bonding wire, 16. ,,Chip capacitor mount part
Claims (1)
体チップ上より直接前記チップコンデンサへボンデング
ワイヤで接続したことを特徴とする半導体パッケージ。A semiconductor package characterized in that a chip capacitor is mounted on a lead frame and is directly connected to the chip capacitor from above the semiconductor chip with a bonding wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63157561A JPH027459A (en) | 1988-06-24 | 1988-06-24 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63157561A JPH027459A (en) | 1988-06-24 | 1988-06-24 | Semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH027459A true JPH027459A (en) | 1990-01-11 |
Family
ID=15652372
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63157561A Pending JPH027459A (en) | 1988-06-24 | 1988-06-24 | Semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH027459A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999034444A1 (en) * | 1997-12-25 | 1999-07-08 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method for manufacturing the same |
| US6713836B2 (en) * | 2001-06-22 | 2004-03-30 | Advanced Semiconductor Engineering, Inc. | Packaging structure integrating passive devices |
| JP2010135737A (en) * | 2008-10-30 | 2010-06-17 | Denso Corp | Semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5856452B2 (en) * | 1979-05-21 | 1983-12-15 | 三菱電機株式会社 | Fuse operation detection device |
| JPS5972757A (en) * | 1982-10-20 | 1984-04-24 | Fujitsu Ltd | Semiconductor device |
-
1988
- 1988-06-24 JP JP63157561A patent/JPH027459A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5856452B2 (en) * | 1979-05-21 | 1983-12-15 | 三菱電機株式会社 | Fuse operation detection device |
| JPS5972757A (en) * | 1982-10-20 | 1984-04-24 | Fujitsu Ltd | Semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999034444A1 (en) * | 1997-12-25 | 1999-07-08 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method for manufacturing the same |
| US6713836B2 (en) * | 2001-06-22 | 2004-03-30 | Advanced Semiconductor Engineering, Inc. | Packaging structure integrating passive devices |
| JP2010135737A (en) * | 2008-10-30 | 2010-06-17 | Denso Corp | Semiconductor device |
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