JPH027451A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To form an interlayer insulating film of high flatness by a method wherein, when a coated film is piled up on insulating film formed by a vapor growth method and is etched back, an inert seed element is implanted in order to make an etch-back rate of the coated film and the insulating film uniform. CONSTITUTION:A silicon oxide film 104 formed by a vapor growth method is coated with a silica film; a baking operation is executed; a coated film 105 is formed. An atom is accelerated in a gas plasma of argon; argon is implanted into the silicon oxide film 104 at an energy of 80 to 100keV. The whole surface of the coated film 105 is etched back; the coated film on a wide wiring layer 103a is removed completely. A silicon oxide film 106 is formed again by the vapor growth method. An opening 108 is made in a prescribed position; after that, an aluminum layer is formed on an insulating layer and on the whole surface of the opening part; after that, second-layer wiring part layers 107a, 107b are formed. When ions of argon are implanted, a bond of atoms inside the silicon oxide film 104 is divided; an etch rate becomes high and its value is nearly identical to an etch rate of the coated film; accordingly, a uniform etch-back operation can be executed; while the flatness is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and particularly to a method for planarizing an interlayer insulating film.

[Conventional technology]

Conventionally, as a method for planarizing an interlayer insulating film between wiring layers of a semiconductor integrated circuit device, there is a method of leaving a coating film (SOG (spin-on glass) film) thickly on the concave portions of steps and thinly on the convex portions. Furthermore, there is a method in which a CVD film is formed above or below the above-mentioned coating film, or both, and planarization is achieved by a combination of the coating film and the CVD film. Furthermore, there is a method of planarizing the coating film by etching it back after forming the coating film.

A typical planarization method described above will be explained with reference to the drawings. As shown in FIG. 3, a 1.0 μm silicon oxide film 302 is grown on a silicon substrate 301, and a 0.5 μm aluminum layer is formed by sputtering. Then, first wiring layers 303a to 303C are formed by a photolithography process.

Next, a 0.2 μm silicon oxide film 3 is formed by vapor phase growth.
After forming a coating film 305 by coating and baking a silica film, wiring II 303 a to 303
Etching back is performed until the silicon oxide film 304 above C is exposed, and the interlayer insulating film is planarized. Subsequently, a 0.5 μm silicon oxide film 306 is formed by vapor phase growth.
, with openings at predetermined positions, and 10.0 μm on the entire surface.
After forming an aluminum layer of m by a sputtering method, a second wiring layer 30 is formed by a photolithography process.
7a and 307b are formed.

[Problem to be solved by the invention]

In the above-mentioned method of achieving planarization by combining a silicon oxide film and a coating film, in a semiconductor device where a wide wiring layer and a narrow wiring layer exist at the same time, the coating film remaining on the wide wiring layer is becomes thicker than the coating film remaining on the narrow wiring layer. Therefore, in the etch-back process after coating, if the etch-back is carried out for a time sufficient to remove the thick coating film on the wide wiring layer, the thin coating film on the narrow wiring layer will be removed in a shorter time. In order to
After the coating film is removed, the silicon oxide film will be etched back. However, if you compare the etch rates of the coated film and the silicon oxide film, the coated film is faster, so only the coated film in the recesses between the wiring layers is significantly etched back, and the shape is smaller than that immediately after baking the silica film. This has the disadvantage that the surface area deteriorates and flattening cannot be achieved sufficiently.

[Means to solve the problem]

The present invention provides a method for manufacturing a semiconductor integrated circuit device having a multilayer wiring structure, including a step of forming an insulating film on a wiring layer by a vapor phase growth method, a step of forming a coating film, and a step before or after forming the coating film. Thereafter, the method includes a step of implanting an inert species element into the insulating film and then etching it back, and a step of flattening the interlayer insulating film.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(c) are longitudinal cross-sectional views of semiconductor chips arranged in the order of steps for explaining a first embodiment of the present invention.

First, as shown in FIG. 1(a), a silicon substrate 101
A silicon oxide film 102 with a thickness of 1.0 μm is grown on
A 1.0 μm thick aluminum layer is formed by sputtering. Thereafter, using the photoresist as a mask, the aluminum layer is etched in a CC4-based gas plasma to form the first wiring layers 103a and 103b.

103C is formed.

Next, a silicon oxide film 104 with a thickness of 0.5 μm is formed by vapor phase growth, and then a silica film is applied under the condition that the thickness is 1100 nm when the base is flat.
Baking is performed at 50° C. for 60 minutes to form a coating film 105. Thereafter, atoms are accelerated in an argon gas plasma, and argon is injected into the silicon oxide film 104 at an energy of 80 to 100 ke. After that, Figure 1 (b
), the entire surface of the coating film 105 is etched back to completely remove the coating film on the wide wiring 4103a. At that time, the wiring layer 103b has a narrow width.

A portion of the silicon oxide film 104 on 103C is also etched back. Thereafter, as shown in FIG. 1(c), a silicon oxide film 106 having a thickness of 1.0 μm is formed again by vapor phase growth.

Next, after providing an opening 108 at a predetermined position, on the insulating layer,
After forming an aluminum layer of 1.5 μm on the entire surface of the opening, the aluminum layer is etched in CC, 124-based gas plasma using a photoresist as a mask to form second wiring layers 107a and 107b. .

By implanting argon ions, the bonds of atoms in the silicon oxide film are broken, and the etch rate during etchback becomes high, almost the same as the etch rate of the coated film, making it possible to etch back uniformly. Flatness after etchback is improved. Although the etch rate of a coated film is somewhat higher, it cannot be said to be as dense to begin with, so a silicon oxide film produced by the CVD method is not suitable. Further, the insulating film underlying the coating film is not limited to a silicon oxide film, but may be a silicon nitride film or a PSG film.

FIGS. 2A to 2C are vertical cross-sectional views of semiconductor chips arranged in the order of steps for explaining a second embodiment of the present invention.

This embodiment is the same as the first embodiment except that the inert species element is implanted before the coating film is formed.

As shown in FIG. 2(a), the first
After forming the third wiring layer, it is grown to a thickness of 0.05 cm by vapor phase growth.
A silicon oxide film 204 with a thickness of 5 μm is formed. After this, the atoms are accelerated to 70 k in an argon gas plasma.
Argon is implanted into the silicon oxide film 204 with an energy of eV.

After that, as shown in FIG. 2(b), the thickness of the flat part is 11
Apply a silica film under the conditions of 00n, and
A beta test for 160 minutes at °C is performed to form a coating film 205. Then, as shown in FIG. 2(c), the entire surface of the coating film is etched back to completely remove the coating film on the wiring layer 203a having a wide wiring width. At this time, the narrow wiring layer 203b
, 203C is also slightly removed and becomes thinner. Next, in the same manner as in the first embodiment, a silicon oxide film with a thickness of 1.0 μm is grown by vapor phase epitaxy to complete the formation of the interlayer insulating film.

The subsequent method of forming the second layer wiring is the same as in the first embodiment.

This embodiment improves the problem that in the first embodiment, almost no argon was injected because a thick coating film remained on the silicon oxide film on the wide wiring layer.
The difference is that argon is uniformly injected into all parts. Therefore, even if over-etching is performed, the shape does not deteriorate, so there is an advantage in that the amount of etchback can be given a margin compared to the first embodiment.

The coating film used in these Examples is not limited to a silica film, but may be any insulating film (such as SOG) that can be formed by spin coating.

〔Effect of the invention〕

As explained above, in the present invention, when a coated film is stacked on an insulating film by vapor phase growth and etched back, the coated film and the insulating film are etched by injecting an inert species element into the above-mentioned insulating film. By performing etch back after making the back rate uniform, a highly flat interlayer insulating film can be formed, which has the effect of improving the reliability of the semiconductor integrated circuit device.

[Brief explanation of the drawing]

FIGS. 1(a) to (c) and FIGS. 2(a) to (c) are longitudinal cross-sections of semiconductor chips arranged in the order of steps for explaining a first embodiment and a second embodiment of the present invention, respectively. The top view and FIG. 3 are longitudinal sectional views of a semiconductor chip for explaining a conventional example. 101.201,301...Silicon substrate, 102
202.302...Silicon oxide film, 103a-10
3C1203a~203C1303a~303C...
Wiring layer, 104, 204, 304... Silicon oxide film, 105, 205. 305... Coating film, 106, 20
6,306...Silicon oxide film, 107a, 107b
, 207a, 207b FIG.

Claims (1)

[Claims] A method for manufacturing a semiconductor integrated circuit device having a multilayer wiring structure includes a step of forming an insulating film on the wiring layer by vapor phase growth, a step of forming a coating film, and a step of forming the insulating film before or after forming the coating film. 1. A method for manufacturing a semiconductor integrated circuit device, comprising the steps of implanting an inert species element into the surface and etching back the interlayer insulating film.