JPH02730B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interface conversion device, and particularly to an interface conversion device for connecting a new processing device and a conventional input/output device.

In a computer system, the main bodies of input/output devices, input/output controllers, etc., and input/output channels, etc.
They are coupled by an input/output interface. The input/output devices of large systems either have a built-in controller such as a microprocessor, or a separate control device is installed to control the CPU.
Everything can be controlled independently without being controlled. In contrast, small systems
Normally, input/output devices are directly controlled by the CPU using an internal interface.

Nowadays, when a user connects an input/output device of a large system to a CPU of a small system, or connects an input/output device of a small system to a large system's CPU,
When connecting to a CPU, etc., it is impossible to connect with the internal interface as it is, so conventionally an interface conversion device is used for the connection.

Conventional interface conversion devices include those that are program-controlled and those that are hardware-controlled. Although this has been improved, it has the drawback of increasing the amount of metal.

The object of the present invention is to eliminate such drawbacks and to provide a cost-effective interface conversion device for combining input/output devices with conventional input/output interfaces under a new series of processing devices. Our goal is to provide the following.

The interface conversion device of the present invention includes a data transfer control circuit for transmitting and receiving data, request signals and response signals for the data, a memory that stores instructions for processing start signal report signals, etc., and a memory that controls the sequence of the instructions. The invention is characterized in that it has a circuit for executing the instructions and means for setting, resetting or testing interface signals.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an interface converter according to the present invention.

The interface conversion device according to the present invention is roughly divided into three blocks, one of which is the interface control register 11, address register 12, input data register 13, output data register 14, and EXATR. Signal (register selection signal) 15, INBUS signal (input bus signal) 16, OUTBUS signal (output bus signal)
17, a B-side (processing device side) interface circuit consisting of a TRAP signal (branch signal) 18 and an ACK signal (confirmation signal) 19. The other one is the interface control latch 21, the INTAG signal (input tag signal) 22, and the OUTTAG signal (output tag signal) 2.
3, BUSIN signal (bus input signal) 24,
BUSOUT signal (bus output signal) 25, SRVIN
This is an A-side (input/output device side) interface circuit consisting of a signal (service input signal) 26 and an SRVOUT signal (service output signal) 27. In addition, the remaining ones are an instruction memory 32, a sequence controller 31, a test signal A33, and a test signal B3.
6. Set signal A34 and set signal B35
This is an instruction execution circuit consisting of:

The main functions of an input/output interface can be roughly divided into the operation of selecting one of multiple input/output devices connected to one interface, and the operation of giving commands to the input/output device for reading, writing, and winding. It can be divided into a startup operation that instructs a specific operation such as return, data transfer for the original purpose of input/output, and a status report or status change report from the input/output device upon completion of the input/output operation. can. Among these operations, data transfer is the one that requires high-speed operation, so in the present invention, data transfer is processed by hardware to increase the speed, and other operations such as startup and status reporting are The amount of hardware is reduced by processing it programmatically.

The instruction memory 32 in FIG. 1 is a memory that stores instructions necessary for controlling the interface, and the sequence controller 31 uses the test signal A3.
3 and test signal B36, the address branch of the instruction is executed, the execution address of the instruction is calculated by the +1 adder, and the execution address of the subsequent instruction is calculated. The test signal A33 is a signal for testing and displaying the result of the interface control latch 21 based on the operand of the instruction, and the test signal B36 is a signal for testing and displaying the state of the interface control register 11 based on the operand of the instruction. This is a signal to be displayed. The set signal A34 is a signal that instructs the interface control latch 21 to be set or reset based on the operand of the instruction, and the set signal B35 is a signal that instructs the interface control register 11 to be set or reset based on the operand of the instruction. . In addition, the set signal B35
sends the BUSIN signal 24 to the address register 12.
Take in the address of or send BUSOUT signal 2
It also performs the function of sending the data of address register 12 to address register 12.

FIG. 2 is a peripheral circuit diagram of the interface control register in FIG. 1.

In FIG. 2, the interface control register 11 is composed of eight flip-flops.
When selected by the EXTAR signal 15 indicating the address of the register to which the data of the OUTBUS signal 17 is to be written, the data of the OUTBUS signal 17 is taken into the flip-flop of the interface control register 11. Interface control register 1
The result of the output of 1 is tested according to the test condition B38 according to the operand of the instruction, and if the result satisfies the condition, the test signal B36 is activated.
Note that 361 indicates an INI signal, and this signal means activation.

That is, data is written to the interface control register 11, the flip-flop corresponding to the INI signal 361 is set, and its output INI
When signal 361 is selected by test condition B38, test signal 36 will be activated.

At startup, when the address register 12 is selected by the EXTAR signal 15, which is a register selection signal, the data on the OUTBUS signal 17 is stored in the address register 12 as the startup address using the same method as before setting the INI signal described above. and commands are written to the output data register 14, respectively.

Test signal B36 is activated by the program testing INI signal 361, and when activation is detected, set signal A34 and test signal A
33 activates the A side interface circuit.

FIG. 3 is a peripheral circuit diagram of the interface control latch in FIG. 1.

In FIG. 3, interface control latch 2
The set signal A34 is input to 1, and
SELOUT signal (selection output signal) 231,
HLDOUT signal (hold output signal) 232,
ADROUT signal (address output signal) 233,
A CMDOUT signal (command output signal) 234 is output. Further, from the input/output side, an ADRIN signal (address input signal) 221 and a STAIN signal (stator input signal) 222 are input.

When the program detects activation by the A-side interface, it sets the interface control latch 21 using the set signal A34, and sends the SELOUT signal 231 to select one of the multiple input/output devices to start data transfer. and
Stores the HLDOUT signal 232. This selects the input/output device, but at the same time, the program places an address on the BUSOUT signal 25 using the set signal B35, and sets the interface control latch 21 using the set signal A34.
ADROUT signal 233 to indicate that the activation address is asserted on BUSOUT signal 25.
Send out. When this sends an address to the I/O device, the I/O device receives this address and indicates that it received the startup address correctly.
It responds with the ADRIN signal 221.

The program is ADRIN due to test condition A37.
When signal 221 is tested, test signal A33 is activated as a result.

When the program detects a response to the ADRIN signal 221, it regards this as acceptance of the address and sends the SELOUT signal 231 in the same manner as described above.
HLDOUT signal 232 and ADROUT signal 23
3 and also inhibits the sending of address register 12 on BUSOUT signal 25.
The input/output device resets the ADRIN signal 221.

When the program detects the reset of the ADRIN signal 221 by the test signal A33, the program continues.
Output data register 14 to BUSOUT signal 25
After sending the above command, the BUSOUT signal 25
indicates that the command is activated above
Sends OMDOUT signal 234. When the input/output device receives the CMDOUT signal 234, it sends a STAIN signal 2 indicating that the command was correctly received.
22.

The program detects STAIN signal 222 and
After suppressing the sending of commands on the BUSOUT signal 25, the CMDOUT signal 234 is dropped.

Since the input/output device suppresses the STAIN signal 222 due to the absence of the CMDOUT signal 234, the program detects this and completes a series of startup operations.

Through the above operations, a command defining the operation of the input/output device is instructed to the input/output device corresponding to the address from the A-side interface indicated by the address register 12. The data transfer subsequent to the above startup operation is executed without the intervention of microprogram processing. That is, as shown in Figure 1, the SRVIN and SRVOUT signals necessary for controlling data transfer are directly exchanged between the input/output device and the host device, and are thereby transferred to the BUSIN and BOSOUT. data is transferred. Next, the reception operation of the data transfer operation will be explained with reference to FIGS. 3 and 2.

When an input/output device is activated and needs to initiate a data transfer, it raises the SRVIN signal 26 to request data transfer service. for example,
In the case of a reception operation, data is sent out on the BUSIN signal 24. Indicates that transfer data is activated on the BUSIN signal 24. The data on the BUSIN signal is set in the input data register 13 by the SRVIN signal 26, and at the same time, the TRAP signal 18, which is a service request signal, is sent to the B-side interface.

When the host device detects the TRAP signal 18,
Input data to INBUS16 to EXTAR signal 15.
The contents of the input data register 13 are received via the INBUS signal 16 by sending a register selection pattern that requests the contents of the register 13 to be activated. Thereafter, when the interface converter responds with an ACK signal 19 indicating that the transferred data has been correctly received, the ACK signal 19 becomes an SRVOUT signal 27 indicating the end of the data transfer service and is sent to the input/output device.

Note that in the case of transmission, the direction of data is different from that in the case of reception, but it goes without saying that the same hardware can be used.

As explained above, according to the present invention, the startup operation and reporting operation that do not affect throughput can be executed by programming complex processing, thereby reducing the hardware required. The data transfer operation has the advantage that high throughput can be ensured by implementing it with simple logic hardware.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram of an interface conversion device showing an embodiment of the present invention, FIG. 2 is a detailed diagram of the B-side interface circuit in FIG. 1, and FIG. 3 is a detailed diagram of the A-side interface circuit in FIG. 1. FIG. 11: Interface control register, 12: Address register, 13: Input data register, 14: Output data register, 21: Interface control latch, 31: Sequence controller, 32: Instruction memory.

Claims (1)

[Scope of Claims] 1. An interface conversion device that controls data transfer between an input/output device and a host device, comprising: an input data register, an output data register, and an input/output register connected to each of these and connected to the input/output device. An input bus (BUSIN) and an output bus (BUSOUT) that connect to the host device; an address register that is connected to the input bus and the output bus; and an address register that is connected to the input/output device and that is transmitted by the input bus and output bus. A microprogram includes an interface control latch that inputs and outputs a signal indicating the type of information, and a process for starting data transfer of the input/output device, including setting and reading information to the address register, control register, and interface control latch. Control lines (SRVIN, SRVOUT) that directly connect the control unit that executes based on An interface conversion device comprising: