JPH0262067A - Semiconductor package - Google Patents
Semiconductor packageInfo
- Publication number
- JPH0262067A JPH0262067A JP63213973A JP21397388A JPH0262067A JP H0262067 A JPH0262067 A JP H0262067A JP 63213973 A JP63213973 A JP 63213973A JP 21397388 A JP21397388 A JP 21397388A JP H0262067 A JPH0262067 A JP H0262067A
- Authority
- JP
- Japan
- Prior art keywords
- heat
- chip
- cooling
- package
- heat pipe
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体チップ（以下チップと略す）を搭載する
半導体パッケージに係り、特にチップの発熱量が多い場
合の冷却構造に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor package on which a semiconductor chip (hereinafter abbreviated as a chip) is mounted, and particularly to a cooling structure when the chip generates a large amount of heat.
従来の技術
近年、半導体の微細加工技術の進歩によりチップの集積
度・機能が飛躍的に向上してきた。それに伴いチップの
発熱量、チップ・サイズ、入出力ピン数も増加してきて
いる。従来このようなチップに対しては多ピン対応とい
うこともあり第５図に示すセラミックＰＧＡＰＡパッケ
ージ、あるいは、これのフィンが無いもの、また、第３
図や第４図に示すようにマルチチップにして水冷等の複
雑な冷却構造をもったパッケージを用いてきた。BACKGROUND OF THE INVENTION In recent years, advances in semiconductor microfabrication technology have dramatically improved the degree of integration and functionality of chips. Along with this, the amount of heat generated by the chip, the chip size, and the number of input/output pins are also increasing. Conventionally, such chips are compatible with a large number of pins, so a ceramic PGAPA package as shown in Figure 5, a package without fins, or a 3-pin package has been used.
As shown in Fig. 4, multi-chip packages with complex cooling structures such as water cooling have been used.
発明が解決しようとする課題
しかし、従来の技術では、第３図や第４図の構造では複
雑になり過ぎてしまう。第３図の場合、チップ３６で発
生した熱はバネ３４でチップ３６に押しつけられピスト
ン３５を通り、ハツト３３、冷却板３１と伝達して冷却
水３２に逃げる。Problems to be Solved by the Invention However, in the conventional technology, the structure shown in FIGS. 3 and 4 becomes too complicated. In the case of FIG. 3, the heat generated in the chip 36 is pressed against the chip 36 by the spring 34, passes through the piston 35, is transmitted to the hat 33 and the cooling plate 31, and escapes to the cooling water 32.
ピストン３５は先端が丸くなっていてバネ３４によって
チップに押しつけられているため、チップして確実な接
触を得ている。また、第４図では、冷却水４２を伝熱板
に吹きつけ、チップ４５で発生した熱を奪い、熱を吸収
した冷却水４２はクーリングへラダ４１の中を通って外
部へ出る。第３図と第４図どちらも冷却水を使い、チッ
プと冷却部の接触方法を工夫していて、空冷に比べ冷却
効果はかなり良い。ところが、とれらはチップと接触す
る特別な部品、冷却水の循環路、水の冷却装置等複雑で
かなり大規模な装置になってしまう。Since the piston 35 has a rounded tip and is pressed against the tip by the spring 34, the piston 35 tips and secures contact. Further, in FIG. 4, cooling water 42 is sprayed onto the heat exchanger plate to remove the heat generated by the chip 45, and the cooling water 42 that has absorbed the heat passes through the cooling ladder 41 and exits to the outside. Both Figures 3 and 4 use cooling water, and the method of contact between the chip and the cooling part is devised, and the cooling effect is much better than that of air cooling. However, these devices require complicated and fairly large-scale equipment, including special parts that come into contact with the chip, a cooling water circulation path, and a water cooling device.
特に、冷却の必要なチップ数が少ない場合は冷却装置の
体積がチップの体積に比べて大きくなってしまい、実装
密度は低くなってしまう。In particular, when the number of chips that require cooling is small, the volume of the cooling device becomes larger than the volume of the chips, resulting in a lower packaging density.
一方、第５図のセラミックＰＧＡパッケージは第３図や
第４図に比較し大幅に簡単な構造である。チップ５５で
発生した熱は、一部は金属キャップ５４や入出力ピン５
３から放出されるが、大部分はセラミック基板５２の中
心部を通りフィン５６に伝って、フィン５６の表面から
空気中へ放出される。そのため、第５図のパッケージで
はセラミック基板５２やフィン５６の材質のもつ熱伝導
率以上にチップ５５とフィン５６の表面との間の熱抵抗
を下げることは不可能である。フィン５６の形状を工夫
しフィン５６自体の冷却効率を上げてもフィン５６の表
面まで熱が十分伝わらなければパッケージ全体の冷却効
率は上がらない。On the other hand, the ceramic PGA package shown in FIG. 5 has a much simpler structure than those shown in FIGS. 3 and 4. Part of the heat generated by the chip 55 is transferred to the metal cap 54 and the input/output pin 5.
3, most of it passes through the center of the ceramic substrate 52, travels to the fins 56, and is emitted into the air from the surface of the fins 56. Therefore, in the package shown in FIG. 5, it is impossible to lower the thermal resistance between the chip 55 and the surface of the fins 56 beyond the thermal conductivity of the materials of the ceramic substrate 52 and the fins 56. Even if the shape of the fins 56 is devised to improve the cooling efficiency of the fins 56 themselves, if heat is not sufficiently transferred to the surface of the fins 56, the cooling efficiency of the entire package will not improve.
本発明は以上の点を考慮し、簡単な構造で冷却効率の向
上を目的としたものである。The present invention takes the above points into consideration and aims to improve cooling efficiency with a simple structure.
課題を解決するための手段
本発明は、キャビティ・ダウン型のセラミックＰＧＡバ
ッ゛ケージにおいて、ダイエリアをヒート・パイプの一
端で構成し、前記ヒート・パイプの他端が入出力ピンと
反対側の面、から突出している半導体パッケージである
。Means for Solving the Problems The present invention provides a cavity-down type ceramic PGA package in which the die area is configured with one end of a heat pipe, and the other end of the heat pipe is connected to the surface opposite to the input/output pins. It is a semiconductor package that protrudes from the .
作 用
ヒート・パイプは等価な銅よりも１桁以上熱伝導率が高
い。このため、発熱源のチップと放熱部のフィン表面と
の間の熱経路で最も多量の熱が通過する部分にヒート・
バイブを用いることで、この部分の熱経路の熱抵抗を大
幅に下げ、より多くの熱をフィン等のヒート・シンクま
で伝えることができる。更に、パッケージの一部にヒー
ト・パイプを組み込むだけ簡単な構造であり、パッケー
ジの製造において従来の方法から大きな変更を必要とし
ない。Working Heat pipes have an order of magnitude higher thermal conductivity than their copper equivalents. For this reason, heat is generated in the part where the largest amount of heat passes through the heat path between the heat source chip and the fin surface of the heat dissipation part.
By using a vibrator, the thermal resistance of the heat path in this area can be significantly lowered, allowing more heat to be transferred to a heat sink such as a fin. Furthermore, the structure is as simple as incorporating a heat pipe into a part of the package, and does not require any major changes from conventional methods in manufacturing the package.
実施例
請求項１に対応する本発明の一実施例の断面を第１図に
示す。セラミック基板２．入出力ピン３、金属キャップ
４は周知の技術で組み立てられており、いわゆるキャビ
ティ・ダウン型のＰＧＡパッケージを構成している。ヒ
ート・バイブ１の一部はセラミック基板に埋め込まれ、
周知の技術でセラミック基板２に気密封止されている。Embodiment A cross section of an embodiment of the present invention corresponding to claim 1 is shown in FIG. Ceramic substrate 2. The input/output pins 3 and the metal cap 4 are assembled using a well-known technique, and constitute a so-called cavity down type PGA package. A part of Heat Vibe 1 is embedded in a ceramic substrate,
It is hermetically sealed to the ceramic substrate 2 using a well-known technique.
セラミック基板２に埋め込まれたヒート・バイブ１の一
端がダイエリアを構成しており、チップ５をダイボンデ
ィングしている。パッケージ外に露出しているヒート・
パイプの部分にはフィン６を取り付け、効率良（熱を空
気中に逃がしている。フィン６はチップ５の発熱量に応
じて表面積や形状を変え、最適なものを用いること、ま
た、他の冷却部品を必要に応じて取り付けるのは言うま
でもない。One end of the heat vibe 1 embedded in the ceramic substrate 2 constitutes a die area, and the chip 5 is die-bonded thereto. Heat exposed outside the package
Fins 6 are attached to the pipe to improve efficiency (heat is released into the air).The surface area and shape of the fins 6 can be changed depending on the amount of heat generated by the chip 5, and the optimal one can be used. It goes without saying that cooling parts should be installed as necessary.
請求項２に対応する一実施例を第２図に示す。An embodiment corresponding to claim 2 is shown in FIG.
セラミック基板１２、入出力ピン１３、金属キャップ１
４はキャビティ・アップ型のＰＧＡパッケージを構成し
ている。ヒート・バイブ１１の一部はセラミック基板１
２に埋め込まれており、その一部がダイエリアを構成し
てチップ１５をダイボンディングしている。ヒート・バ
イブ１１の中間部分はセラミック基板１２の配線領域１
７を貫通し、入出力°ピン１３とは反対側の面から他端
が突出している。ヒート・バイブ１１の露出している部
分にはフィン１６が取り付けられている。なお、フィン
１６の表面積や形状はチップ１５の発熱量に応じて最適
のものを採用すること、また、他の冷却装置を接続でき
ることは言うまでもない。Ceramic board 12, input/output pin 13, metal cap 1
4 constitutes a cavity-up type PGA package. A part of the heat vibe 11 is the ceramic substrate 1
2, a part of which constitutes a die area, and the chip 15 is die-bonded thereto. The middle part of the heat vibe 11 is the wiring area 1 of the ceramic substrate 12
7, and the other end protrudes from the surface opposite to the input/output pin 13. A fin 16 is attached to the exposed portion of the heat vibe 11. It goes without saying that the surface area and shape of the fins 16 should be optimal depending on the amount of heat generated by the chip 15, and that other cooling devices can be connected.
発明の効果
鋼よりも１桁以上高い熱伝導率を持つヒート・パイプを
使って、チップとフィン等の冷却装置との間に熱径路を
形成することで、従来より多（の熱量を運んでパッケー
ジの外へ放出し、冷却効率を上げることができる。この
ことは、チップの温度を下げることになり、チップの正
常な動作や高速化はもちろんのこと、チップの寿命を伸
ばすことにも大いに寄与する。更に、セラミック基板の
加工も特別なものではなく、ヒート・バイブの取り付け
も周知の技術で可能であり、パッケージの信頼性は問題
ない。このように、従来の技術を用いて要項でき、構造
も簡単であるためコスト的に有利で、なおかつ、高い冷
却効率を得ることができ、実用上大いに有用である。Effects of the invention By using a heat pipe, which has thermal conductivity one order of magnitude higher than that of steel, to form a thermal path between the chip and a cooling device such as a fin, it is possible to carry more heat than before. It can be emitted outside the package and increase cooling efficiency.This lowers the temperature of the chip, which not only helps the chip operate normally and speeds up, but also greatly extends the life of the chip. Moreover, the processing of the ceramic substrate is not special, and the heat vibrator can be attached using well-known technology, so there is no problem with the reliability of the package. Since the structure is simple, it is advantageous in terms of cost, and high cooling efficiency can be obtained, making it very useful in practice.
第１図、第２図は各々本発明の半導体パッケージの一実
施例の断面構造図、第３図、第４図、第５図は従来例の
断面構造図である。
１・・・・・・ヒート・パイプ１．２・・・・・・セラ
ミック基板、３・・・・・・入出力ピン、４・・・・・
・金属キャップ、５・・・・・・チップ、６・・・・・
・フィン。
代理人の氏名 弁理士 粟野重孝 ほか１２第
図
第
図
第
図1 and 2 are cross-sectional structural views of one embodiment of the semiconductor package of the present invention, and FIGS. 3, 4, and 5 are cross-sectional structural views of a conventional example. 1... Heat pipe 1.2... Ceramic board, 3... Input/output pin, 4...
・Metal cap, 5... Chip, 6...
·fin. Name of agent: Patent attorney Shigetaka Awano and 12 other figures
Claims (2)
ージにおいて、ダイエリアをヒート・パイプの一端で構
成し、前記ヒートパイプの他端が入出力ピンとは反対側
の面から突出していることを特徴とする半導体パッケー
ジ。(1) A semiconductor characterized in that, in a cavity-down type ceramic PGA package, the die area is constituted by one end of a heat pipe, and the other end of the heat pipe protrudes from the surface opposite to the input/output pins. package.
ージにおいて、ダイエリアをヒート・パイプの一端で構
成し、前記ヒート・パイプの中間部が前記ＰＧＡパッケ
ージの配線領域を貫通して、前記ヒート・パイプの他端
が入出力ピンとは反対側の面から突出していることを特
徴とする半導体パッケージ。(2) In a cavity-up type ceramic PGA package, the die area is formed by one end of a heat pipe, and the middle part of the heat pipe penetrates the wiring area of the PGA package, and the die area is formed by one end of the heat pipe. A semiconductor package characterized by an end protruding from the side opposite to the input/output pins.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63213973A JPH0262067A (en) | 1988-08-29 | 1988-08-29 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63213973A JPH0262067A (en) | 1988-08-29 | 1988-08-29 | Semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0262067A true JPH0262067A (en) | 1990-03-01 |
Family
ID=16648131
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63213973A Pending JPH0262067A (en) | 1988-08-29 | 1988-08-29 | Semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0262067A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008131587A1 (en) * | 2007-04-28 | 2008-11-06 | Jenshyan Chen | Heat pipe and manufacturing method thereof |
| WO2016013072A1 (en) * | 2014-07-23 | 2016-01-28 | 日本軽金属株式会社 | Radiator |
| JP2023114236A (en) * | 2022-02-04 | 2023-08-17 | 株式会社デンソー | semiconductor equipment |
-
1988
- 1988-08-29 JP JP63213973A patent/JPH0262067A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008131587A1 (en) * | 2007-04-28 | 2008-11-06 | Jenshyan Chen | Heat pipe and manufacturing method thereof |
| WO2016013072A1 (en) * | 2014-07-23 | 2016-01-28 | 日本軽金属株式会社 | Radiator |
| JP2023114236A (en) * | 2022-02-04 | 2023-08-17 | 株式会社デンソー | semiconductor equipment |
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