JPH025633A - Selective calling receiver - Google Patents

Abstract

PURPOSE:To reduce the current consumption of the title receiver so that the battery of the receiver can be extended in service life by operating the receiver with high-speed clocks only when it is detected that the receiver itself is called during the receiving period of the group to which the receiver itself belongs, with the receiver being operated with low-speed clocks while the receiver itself is not called. CONSTITUTION:A control circuit 40 outputs ON/OFF control signals to a battery saving circuit 10 after acquisition of synchronism is completed to set a radio circuit 2 and demodulator circuit 3 to reception operating states during the receiving period of its own group 2 only. The control circuit 40 leads in and uses low-speed clocks generated from the 2nd clock oscillator 29 as operating clocks through the full period of one frame unless a call to its own receiver is detected. Upon detecting a call to its own receiver as a result of collation to individual number coding, the circuit 40 switches the operating clocks from the low-speed clocks to high-speed clocks generated by a 1st clock oscillator 91. Thereafter, message codes are decoded synchronously to the high-speed clocks and, upon completing the decoding, the operating clocks are returned to the low-speed clocks.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a selective call receiver with a message display function.

(Prior Art) In recent years, as a new type of selective calling system, a system has been proposed that not only makes a call notification but also transmits and displays a message code. FIG. 3 shows an example of an FA configuration to which this type of system is applied. This calling method is
One frame is divided into multiple groups (
The time division is divided into n groups (in the figure), and these groups are divided into (n groups in the figure).
As shown in b), a synchronization word and a plurality of call words (
In the figure, the time is divided into [n words]. When a calling party sends a call request and message to any selective call receiver, the base station selects an empty call word in the group to which the selective call receiver belongs as shown in (c). A selective calling signal consisting of an individual number code for identifying the calling receiver and a message code is inserted and transmitted.

On the other hand, FIG. 4 shows an example of the configuration of a selective call receiver, in which the selective call receiver first receives a selective call signal sent from the base station through an antenna 1 and a radio circuit 2 constituting a receiving circuit.
After being received and demodulated by the demodulation circuit 3, the signal is introduced into the control circuit 4. Then, this control circuit 4 compares the individual number code in the selective call signal with the individual number code of the own machine, which is stored in advance in the ROM 5, and if both codes match, a call to the own machine has occurred. It recognizes this and supplies a ringing signal to the speaker 7 via the drive circuit 6, thereby generating a ringing tone and notifying the subscriber of the occurrence of a call. At the same time, the received message code is subjected to error correction and decoded, and the decoded message is supplied to a display 8, such as a liquid crystal display, for display.

By the way, selective call receivers generally perform battery saving in order to reduce power consumption and extend battery life. This battery saving method, for example, operates the receiving circuit to receive a selective call signal only during the receiving period of the group to which the device belongs in one frame after synchronization, and stops power supply to the receiving circuit during the receiving period of other groups. This is to prevent the reception operation from being performed. In this way, when one frame is composed of n groups, the power consumption can be reduced to about 1/n compared to the case where reception is always performed, and battery consumption can be reduced accordingly. can.

(Problem to be Solved by the Invention) However, although this type of conventional receiver performs battery saving, it does not perform battery saving during the reception period of a group other than the group to which the receiver belongs. It is necessary to perform control operations, etc., which consumes current. Furthermore, during the reception period of the group to which the own machine belongs, current is consumed equally whether or not the individual number code for the own machine is inserted in the selective call signal. For this reason, there is still a large amount of wasteful current consumption, which has been a major problem in extending battery life.

The present invention focuses on this point, and makes it possible to reduce the current consumption when the individual number code for the own machine is not inserted even during the receiving period of the group to which the own machine belongs, thereby reducing unnecessary current consumption and conserving the battery. Our objective is to provide a selective calling receiver that can extend its service life.

Another object of the present invention is to reduce the current consumption in the group to which the device belongs, as well as to reduce unnecessary current consumption even during periods other than the group to which the device belongs, thereby further extending the life of the battery. The object of the present invention is to provide a selective call receiver that can be extended.

[Structure of the Invention] (Means for Solving the Problems) The present invention requires a high-speed clock in the decoding operation of message codes that require error correction, but the present invention provides a method for collating individual number codes that does not require special error correction. Focusing on the fact that a high-speed clock is not necessary for operation and a low-speed clock is sufficient, we constructed a control circuit that performs tasks such as matching individual number codes and decoding message codes so that it can operate using multiple clocks with different speeds. The control circuit also includes a clock generation circuit that supplies a first clock at a predetermined speed and a second clock at a slower speed than the first clock, and the control circuit generates the first clock at a predetermined speed when collating individual number codes. A verification operation is performed in synchronization with the second clock, and only when a call to the own machine is detected as a result of this verification, the operating clock is switched to the first clock and a message code decoding operation is performed. be.

In another aspect of the present invention, the control circuit performs a verification operation in synchronization with the second clock during a reception period other than the group to which the own device belongs and when identifying an individual number code, and as a result of this verification, the control circuit performs a verification operation in synchronization with the second clock. Only when a call is detected, the operating clock is switched to the first clock to perform the message code decoding operation.

(Function) As a result, the control circuit operates using the high-speed first clock only when a call to the own machine is detected during the reception period of the group to which the own machine belongs, and operates using the low-speed second clock at other times. Since the control circuit operates based on the clock, the control circuit operates with a low current using the low speed clock unless a call to its own device occurs. This makes it possible to reduce current consumption compared to the conventional system, which used a high-speed clock to match individual number codes and decode message codes, thereby further extending battery life. Become.

According to another aspect of the present invention, the control circuit operates at a low current using a low-speed clock not only during the reception period of the group to which the device belongs, but also during the period of groups other than the group to which the device belongs. Therefore, the current consumption during non-receiving operation is further reduced than in the past, thereby further extending the battery life.

(Embodiment) FIG. 1 shows the configuration of a selective call receiver 1d in an embodiment of the present invention. In this figure, the same parts as those in FIG. 4 are given the same reference numerals and detailed explanations will be omitted.

The selective calling receiver of this embodiment uses a two-clock type microcomputer as the control circuit 40.
Further, a clock generation circuit 9 for supplying an operating clock to the control circuit 40 is provided. This clock generation circuit 9 includes a first clock oscillator 91 that generates a high-speed clock necessary for decoding the message code.
and a second clock oscillator 92 that generates a low-speed clock necessary and sufficient to verify individual number codes at a slower speed than the high-speed clock. Note that 10 is a battery saving circuit for turning on and off the power supply to the radio circuit 2 and the demodulation circuit 3 according to instructions from the control circuit 40.

Further, the control circuit 40 is equipped with clock switching control means in addition to normal functions such as individual number code verification means, message code decoding means, call notification control means, message display control means, and battery saving control means. . This clock switching control means generates an operating clock from the second clock oscillator 92 as an operating clock during the entire reception period of a group other than the group to which the device belongs and during the reception period of the group to which the device belongs. A low-speed clock is selectively introduced into the control circuit 40. Also, during the receiving period of the group to which the device belongs, a high-speed clock generated from the first clock oscillator 91 is introduced for decoding the message code only when a call to the device is detected.

Next, the operation of the selective call receiver configured as described above will be explained. If the group to which your machine currently belongs is group 2
Assuming that, after the synchronization pull-in is completed, the control circuit 40 outputs an on/off control signal to the battery saving circuit 10, thereby causing the wireless circuit 2 to operate only during the reception period of group 2 to which the own device belongs, as shown in FIG. And it performs so-called battery saving control in which the demodulation circuit 3 is set to a receiving operation state. Further, the control circuit 40 introduces and uses the low-speed clock generated from the second clock oscillator 92 as an operating clock during the entire period of one frame, unless a call to the own machine is detected.

Therefore, the control circuit 40 performs battery saving control during the reception period of each group to which the own device does not belong, and an individual number code verification operation during the reception period of Group 2 to which the own device belongs, respectively, in synchronization with the low-speed clock. It turns out. Therefore, the current consumption of the control circuit 40 is reduced compared to a conventional selective call receiver that executes various controls in synchronization with a high-speed clock for the entire period of one frame.

Note that since the verification of the individual number code does not require z' correction and does not require high-speed operation, no problem will occur even if a low-speed clock is used as described above.

On the other hand, when a call to the own device is detected as a result of the above-mentioned individual number code verification, the control circuit 40 at this point changes the operating clock from the low-speed clock generated from the second clock oscillator 92 as shown in FIG. The high speed clock generated by the first clock oscillator 91 is switched to. Thereafter, the message code is decoded in synchronization with this high-speed clock, and when this decoding is completed, the operating clock is returned to the low-speed clock generated from the second clock oscillator 92.

As described above, in this embodiment, the high-speed clock generated from the first clock oscillator 91 is used only when decoding a message code that requires high-speed operation, and the high-speed clock generated from the second clock oscillator 92 is used during the waiting period. Since the control circuit 40 is operated using a low-speed clock, the current consumption of the control circuit 40 can be reduced compared to a conventional receiver that uses a high-speed clock throughout the period. By reducing the power consumption of the receiver, the battery life can be extended accordingly.

Note that the present invention is not limited to the above embodiments. For example, in the above embodiment, a high-speed clock was used for decoding the message code, and a low-speed clock was used for other control purposes, but this low-speed clock was further divided into two parts, and the faster one was used to check the individual number codes. Alternatively, the lower speed may be used for battery saving control. Further, in the above embodiment, the high-speed clock oscillator and the low-speed clock oscillator were provided separately, but by providing a reference oscillator and a variable frequency divider, and changing the division ratio of the variable frequency divider to n, the clock It is also possible to perform switching. In addition, the control means and control contents of the control circuit, the configurations of the clock generation means, the clock switching means, etc. can be modified in various ways without departing from the gist of the present invention.

[Effects of the Invention] As detailed above, according to the present invention, the control circuit that performs verification of individual number codes, decoding of message codes, etc.
The above-described clock generator is configured to be operable by a plurality of clocks having different speeds, and includes a clock generation circuit that supplies a first clock having a predetermined speed and a second clock slower than the first clock to the control circuit, respectively. The control circuit performs a verification operation in synchronization with the second clock when verifying the individual number code, and switches the operating clock to the first clock only when a call to the own machine is detected as a result of this verification. By decoding the message code, it is possible to reduce current consumption when the individual number code for the own machine is not inserted even during the reception period of the group to which the own machine belongs, thereby reducing wasted current consumption. It is possible to provide a selective call receiver that can reduce battery life and extend battery life.

According to another aspect of the invention, the control circuit performs a verification operation in synchronization with the second clock when verifying reception periods and individual number codes for groups other than the group to which the own device belongs, and as a result of this verification, By switching the operating clock to the first clock and decoding the message code only when a call is detected, in addition to reducing the current consumption in the group to which the device belongs, it also reduces the current consumption in the group to which the device belongs. It is possible to provide a selective call receiver that can reduce current consumption even during this period, thereby further extending battery life.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing the configuration of a selective call receiver in an embodiment of the present invention, FIG. 2 is a timing diagram used to explain the operation of the receiver, and FIG. 3 is an example of the configuration of a selective call signal. FIG. 4 is a circuit block diagram showing the configuration of a conventional selective call receiver. DESCRIPTION OF SYMBOLS 1... Antenna, 2... Radio circuit, 3... Demodulation circuit, 40... Control circuit, 5... ROM, 6... Drive circuit, 7... Speaker, 8... Display, 9...
Clock generation circuit, 91... first clock oscillator for high speed clock generation, 92... second clock oscillator for low speed clock generation, 10... battery saving circuit. One meal with applicant's representative, patent attorney Takehiko Suzue

Claims (2)

[Claims] (1) Out of one frame transmitted from the base station, the receiving circuit receives only the group to which the own machine belongs, and the control circuit converts the individual number code in the selective call signal inserted into this group into the individual number of the own machine. In the selective calling receiver, the selective calling receiver notifies the occurrence of a calling by an annunciator when both codes match, and also decodes the message code in the selective calling signal and displays it on a display. The circuit is configured to be operable by a plurality of clocks having different speeds, and includes a clock generation circuit that supplies the control circuit with a first clock having a predetermined speed and a second clock having a lower speed than the first clock. , the control circuit performs a verification operation in synchronization with the second clock when verifying individual number codes, and changes the operating clock to the first clock only when a call to the own machine is detected as a result of this verification.
1. A selective call receiver characterized in that a message code decoding operation is performed by switching to a clock of . (2) When the control circuit performs a verification operation in synchronization with the second clock when verifying the receiving period and individual number code of a group other than the group to which the own device belongs, and as a result of this verification, a call to the own device is detected. 2. The selective call receiver according to claim 1, wherein the message code decoding operation is performed by switching the operating clock to the first clock.