JPH0246777A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0246777A JPH0246777A JP63197665A JP19766588A JPH0246777A JP H0246777 A JPH0246777 A JP H0246777A JP 63197665 A JP63197665 A JP 63197665A JP 19766588 A JP19766588 A JP 19766588A JP H0246777 A JPH0246777 A JP H0246777A
- Authority
- JP
- Japan
- Prior art keywords
- film
- poly
- trench
- gate
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000004065 semiconductor Substances 0.000 title claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 229910008484 TiSi Inorganic materials 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Landscapes
- Non-Volatile Memory (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明はトレンチ・ゲートＭＯ３ＦＥＴのトレンチ・ゲ
ートにおける多層８１ゲートイ荷造の製造方法に関する
。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a multilayer 81-gate structure in the trench gate of a trench-gate MO3FET.
［従来の技術］
従来、トレンチ・ゲートＭＯ５ＦＥＴのゲト構造に多層
Ｓｉゲート構造を取ると云う提案はなく、又、゛実例も
なく、単層Ｓｉゲートのみであった・
［発明が解決しようとする課題）
しかし、上記従来技＆Ｆｉによると、トレンチ・ゲート
によるフローティング・ゲートＭＯ３ＦＥＴが製作でき
ないと云う課題があった。[Prior Art] Conventionally, there has been no proposal to use a multilayer Si gate structure as the gate structure of a trench gate MO5FET, and there has been no actual example, and only a single layer Si gate has been proposed. Problem) However, according to the above-mentioned conventional technique &Fi, there was a problem that a floating gate MO3FET using a trench gate could not be manufactured.
本発明は、かかる従来技（・トｉの課題を解決するたぬ
に、トレンチ・ゲー１−ＭＯ３ＦＥＴによるフローティ
ング・ゲートＭＯＳ ＦＥＴの電気的書き込み可能及
び電気的書き込み・消去可能な読み出し専用記憶装置の
製作を可能とする製造方法を提供する事を目的とする。In order to solve the problems of the prior art, the present invention provides an electrically writable and electrically writable/erasable read-only memory device using a floating gate MOS FET using a trench gate MO3FET. The purpose is to provide a manufacturing method that enables production.
［課題を解決するための手段］
上記課題を解決するために、本発明は半導体装置の製造
方法に関し、８１基板表面からトレンチをドライエツチ
ングにより形成し、該トレンチ（β１１面にゲート絶！
！膜を形成し、該ゲート絶縁膜上にＣＶＤ法により第１
のポリ８１膜を形成し、該第１のポリＳｌ膜上に絶縁膜
を形成し、該絶縁膜上に第２のポリ膜を形成する手段を
取る。[Means for Solving the Problems] In order to solve the above problems, the present invention relates to a method of manufacturing a semiconductor device, in which a trench is formed from the surface of an 81 substrate by dry etching, and the trench (gate cutoff on the β11 plane) is formed by dry etching.
! A first film is formed on the gate insulating film by a CVD method.
A poly 81 film is formed, an insulating film is formed on the first poly Sl film, and a second poly film is formed on the insulating film.
〔実 施 例ｊ 以下、実施例により本発明を詳述する。[Example of implementation] Hereinafter, the present invention will be explained in detail with reference to Examples.
第１図は本発明の一実施例を示すトレンチ・ゲート部の
断面図である。FIG. 1 is a sectional view of a trench gate portion showing an embodiment of the present invention.
いま、８１基板ｌの表面からホト・リソグラグイ−とド
ライ・エツチングによりトレンチ部２を設ける。この場
合、Ｓｉ基板１の表面には予じめフィールド酸化膜が形
成されている場合がある。Now, a trench portion 2 is provided from the surface of the substrate 81 by photolithography and dry etching. In this case, a field oxide film may be formed on the surface of the Si substrate 1 in advance.
次に、熱酸化等により前記トレンチ部２の少な（とも側
壁を含む内面に第一の絶縁膜３を薄く形成する。Next, a first insulating film 3 is formed thinly on the inner surface (including the sidewalls) of the trench portion 2 by thermal oxidation or the like.
次に、ＣＶＤ法等により第１のポリＳｉ膜４を０．１μ
ｍｗ０．３μｍ厚程度形成する。この場合、第１のポリ
５ｉｌｌ！４はＳｉ基板１の表面に形成された絶縁膜上
にて所望の形状にホト・エツチングされる場合がある。Next, a first poly-Si film 4 of 0.1 μm is formed using a CVD method or the like.
It is formed to have a thickness of about mw0.3 μm. In this case, the first poly5ill! 4 may be photo-etched into a desired shape on an insulating film formed on the surface of the Si substrate 1.
更に、第１のポリＳｉ膜４の表面にＴｉＳｉやＷＳｉ等
のシリサイド膿が形成される場合がある。尚、この第１
のポリＳｉ膜４はフローティング・ゲートとして使用さ
れる場合が多い。Furthermore, silicide pus such as TiSi or WSi may be formed on the surface of the first poly-Si film 4. Furthermore, this first
The poly-Si film 4 is often used as a floating gate.
次に、前記第１のポリ５ｉＩｌｉ４の表面に、熱酸化あ
るいはＣＶＤ法等により第２の絶縁膜５が形成され、該
第２の絶縁膜５の表面に第２のポリＳｉ膜６がＣＶＤ法
等により形成されるが、該第２のポリ５ｉｌｉ６は必ず
しもポリＳｉ膜である必要はな（、ＷｌｌやＴｉＳｉあ
るいはＷＳｉ等であったり、これらの膜をポリＳｊｌ！
表面に形成した構造になる場合もある。この様にして形
成された第２のポリ５ｉＩｌ１６はトレンチ内部を埋め
る形で形成され、その後、所望の形状にホト・エツチン
グされるものである。Next, a second insulating film 5 is formed on the surface of the first poly 5iIli 4 by thermal oxidation or CVD, and a second poly-Si film 6 is formed on the surface of the second insulating film 5 by CVD. However, the second poly 5ili6 does not necessarily have to be a poly-Si film (eg, Wll, TiSi, WSi, etc., or these films can be formed by poly Sjl!).
It may also be a structure formed on the surface. The second poly 5iIl16 thus formed is formed to fill the inside of the trench, and is then photo-etched into a desired shape.
尚、第１の絶縁ｌｌｌ３は、通常１００人程程度厚みに
形成されるが、トレンチ内壁の一部の絶縁膜厚な２ＯＡ
程度に薄く形成してトンネル電流の通路となしても良い
。The first insulating layer 3 is normally formed to a thickness of about 100 mm, but the first insulating layer 3 is formed to have a thickness of about 100 mm.
It may be formed as thin as possible to serve as a tunnel current path.
更に、第２のポリＳｉ膜６のホト・エツチング後、自己
整合形にて、第１のポリＳｉ膜４迄−気にホト・エツチ
ングされる場合もある。Further, after the second poly-Si film 6 is photo-etched, the first poly-Si film 4 may also be photo-etched in a self-aligned manner.
〔発明の効果１
本発明によりトレンチ・ゲートＭＯＳ ＦＥＴのトレ
ンチ・ゲート部に多層ゲート構造を形成できる効果があ
り、トレンチ・ゲートＭＯ５ＦＥＴによるフローティン
グ・ゲートＭＯＳ ＦＥＴ構造をもった電気的書き込
み、及び電気的書き込み・消去可能な読み出し専用記憶
装置を製作することができる効果がある。[Effect of the invention 1] The present invention has the effect of forming a multilayer gate structure in the trench gate part of a trench gate MOS FET, and enables electrical writing and electrical writing with a floating gate MOS FET structure using a trench gate MO5FET. This has the effect of making it possible to manufacture a read-only storage device that can be written and erased.
６、％２のホ゛す５１只費6. 51 fee due to %2
第１図は本発明の一実施例を示すトレンチ・ゲート部の
要部の断面図である。
Ｓｉ基板
トレンチ部
第１の絶縁膜
第１のポリＳｉ膜
第２の絶４１ Ｉｔ！
第２のポリＳｉ膜
第１図FIG. 1 is a sectional view of a main part of a trench gate portion showing an embodiment of the present invention. Si substrate trench section first insulating film first poly-Si film second isolation 41 It! Second poly-Si film Fig. 1
Claims (1)
成され、該トレンチ側面にゲート絶縁膜が形成され、該
ゲート絶縁膜上にＣＶＤ法により第１のポリＳｉ膜が形
成され、該第１のポリＳｉ膜上に絶縁膜が形成され、該
絶縁膜上に第２のポリＳｉ膜が形成されて成る事を特徴
とする半導体装置の製造方法。A trench is formed from the surface of the Si substrate by dry etching, a gate insulating film is formed on the side surface of the trench, a first poly-Si film is formed on the gate insulating film by a CVD method, and a first poly-Si film is formed on the first poly-Si film. 1. A method of manufacturing a semiconductor device, characterized in that an insulating film is formed on the insulating film, and a second poly-Si film is formed on the insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63197665A JPH0246777A (en) | 1988-08-08 | 1988-08-08 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63197665A JPH0246777A (en) | 1988-08-08 | 1988-08-08 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0246777A true JPH0246777A (en) | 1990-02-16 |
Family
ID=16378294
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63197665A Pending JPH0246777A (en) | 1988-08-08 | 1988-08-08 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0246777A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5411905A (en) * | 1994-04-29 | 1995-05-02 | International Business Machines Corporation | Method of making trench EEPROM structure on SOI with dual channels |
| US8868029B2 (en) | 2010-01-29 | 2014-10-21 | Alcatel Lucent | Method and apparatus for managing mobile resource usage |
-
1988
- 1988-08-08 JP JP63197665A patent/JPH0246777A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5411905A (en) * | 1994-04-29 | 1995-05-02 | International Business Machines Corporation | Method of making trench EEPROM structure on SOI with dual channels |
| US8868029B2 (en) | 2010-01-29 | 2014-10-21 | Alcatel Lucent | Method and apparatus for managing mobile resource usage |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3043135B2 (en) | Manufacturing method of nonvolatile semiconductor memory | |
| JPH03211885A (en) | Semiconductor device and manufacture thereof | |
| JPH11135654A (en) | Split-gate flash memory cell structure | |
| JP3362970B2 (en) | Nonvolatile semiconductor memory device and method of manufacturing the same | |
| JP2005524994A (en) | High coupling ratio floating gate memory cell | |
| US7939878B2 (en) | Nonvolatile semiconductor memory and method of manufacturing the same and manufacturing method thereof | |
| US6475894B1 (en) | Process for fabricating a floating gate of a flash memory in a self-aligned manner | |
| US7473601B2 (en) | Method of fabricating flash memory device using sidewall process | |
| US6426257B1 (en) | Flash memory and manufacturing method therefor | |
| JPH0677493A (en) | Semiconductor device and its manufacture | |
| JP2980171B2 (en) | Manufacturing method of split gate type flash memory cell | |
| JPH0246777A (en) | Manufacture of semiconductor device | |
| JPH10289990A (en) | Method for manufacturing semiconductor device | |
| JPH10112511A (en) | Semiconductor nonvolatile memory and method of manufacturing the same | |
| JPH05218329A (en) | Semiconductor device and its manufacture | |
| CN114823685B (en) | Split gate flash memory unit and preparation method thereof | |
| JP2634492B2 (en) | Manufacturing method of nonvolatile semiconductor memory device | |
| TW455933B (en) | Manufacture method of floating gate in flash memory | |
| US6362047B1 (en) | Method of manufacturing EEPROM memory points | |
| JPH0223672A (en) | semiconductor storage device | |
| JPH04356969A (en) | Nonvolatile semiconductor device | |
| JPH0774274A (en) | Method for manufacturing semiconductor device | |
| JPS62113478A (en) | Nonvolatile semiconductor memory | |
| TW441109B (en) | Low voltage flash memory cell and method of making | |
| JPH05335588A (en) | Non-volatile memory device and manufacture thereof |