JPH0245907Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a circuit that determines display priority among windows in a display device that can display a plurality of windows on one screen.

[Prior Art] Recent display devices tend to adopt a multi-window system that can display a plurality of different images on one screen. In the multi-window method, the problem is how to handle overlapping of windows on the screen. An immediate idea would be to assign a priority to each window in advance, and in a location where two or more windows overlap, only the window with the highest priority among them would be displayed. However, with the conventional method, if you wanted to change the window priority later, you had to rewrite the contents of the image memory. This rewriting requires priority calculation and address calculation, so the CPU
It put a considerable burden on the.

[Object of the invention] Therefore, an object of the invention is to provide a window priority circuit that can arbitrarily change the priority order of a plurality of windows without rewriting the image memory.

[Summary of the invention] The window priority circuit according to the invention has a plurality of priority registers that can arbitrarily set the identifier of each window from the outside, and selectively controls each window display signal according to the settings of these priority registers. a window selection circuit that outputs a corresponding identifier in response to a window display signal with the highest priority among the one or more window display signals that have passed through the first multiplexer; It consists of a decoder that decodes the identifier, and a second multiplexer that outputs the image information of the window that has the identifier decoded by the decoder.

[Description of Embodiment] An embodiment of the present invention is shown in FIG. Each window is given a unique window identifier WID. If the length of WID is n bits, up to 2 ⁿ windows can be displayed simultaneously. The circuit of FIG. 1 consists of ²ⁿ priority registers 10, which can load any WID from the CPU (not shown),
12, 14, and ²ⁿ multiplexers 16, 1 each receiving a display signal corresponding to each window.
8, 20, and a window selection circuit 22 consisting of a combination of AND gates, OR gates, and inverters interconnected to pass only the contents of particular priority registers in response to the outputs of these multiplexers; a decoder 24 that specifies a window to be displayed from the output of the selection circuit 22;
and a multiplexer 26 that passes only the image information of the window designated by the decoder 24. Each of the above circuit elements will be specifically explained below.

The priority registers 10, 12, and 14 are each loaded with the identifier WID of each window from the CPU when the system is initialized or when the priority order is changed.
Therefore, the CPU outputs the WID and the address of the priority register into which this WID should be loaded. The register address is determined by the address decoder 30 in FIG.
, thereby generating a load signal to the corresponding priority register. For example, when the first priority register load signal is generated from the address decoder 30, the first priority register 10 is activated by the CPU.
Receive WID from. other priority registers 12,
The same applies to 14. 2 ⁿ priority registers 10,1
2 and 14 have a fixed priority order, with the first priority register 10 having the highest priority, and the following second priority registers 1 and 14.
The priority registers decrease in the order of the second and third priority registers (not shown), and the second ^n-th priority register 14 is the lowest. Therefore, the WID loaded into these priority registers
By changing , you can freely change the display priority of windows even after the system is initialized.

Multiplexers 16, 18, and 20 are provided corresponding to the priority registers 10, 12, and 14, respectively, and are used to control the first window W1 to the second ⁿ window.
W2 Receives display signals up to ⁿ . These display signals are generated in synchronization with the raster scan of a display device (not shown) and when the corresponding window is to be displayed, regardless of priority. Therefore, two or more window display signals may be generated simultaneously. This example will be explained with reference to FIGS. 3 and 4.

FIG. 3 shows an example in which the first window W1 and the second window W2 are displayed on the display screen 32 at the same time. In this example, the first window W1 has a higher display priority. Therefore,
In the overlapping portion indicated by diagonal lines, only the image of the first window W1 is actually displayed. The display position of each window is determined by the coordinate values of its upper left end and lower right end.

FIG. 4 shows a circuit for generating window display signals to be applied to the multiplexers 16, 18, and 20, using a well-known horizontal counter 34 and vertical counter 36 that count up in synchronization with raster scanning. are doing. The W1 range detector 38 detects the coordinate range in which the first window W1 is displayed, and in the example of FIG. 3, start coordinates (x1, y1) and end coordinates (x2, y2) are loaded. Similarly, the W2 range detector 40 is
In order to detect the display coordinate range of the second window W2, start coordinates (x3, y3) and end coordinates (x4,
y4) is loaded. As is clear from FIG. 3, in the W1 range detector 38, the count value of the horizontal counter 34 is between x1 and x2,
and the count value of the vertical counter 36 is from y1 to y2
If it is within this range, a W1 display signal is generated that enables display of the first window W1. W2 range detector 40 generates a W2 indication signal when the horizontal count value is between x3 and x4 and the vertical count value is between y3 and y4. W1
The display signal and the W2 display signal are generated simultaneously in the shaded area of Figure 3, when the horizontal count value is between x3 and x2 and the vertical count value is between y3 and y2. be. The same applies when the number of windows displayed simultaneously is three or more.

In the example of FIG. 3, the identifier of the first window W1 is loaded into the first priority register 10, and the identifier of the second window W2 is loaded into the second priority register 12. Therefore, when the W1 indication signal is generated, the multiplexer 16 selects n numbers corresponding to the first priority register 10 of the window selection circuit 22.
Condition the AND gates 10a-10n. Similarly, multiplexer 18 partially conditions the n AND gates 12a-12n corresponding to second priority register 12 when the W2 indication signal is generated. The same applies to other multiplexers. Of course,
If the window identifier WID loaded into the priority registers 10, 12, 14 changes, the window display signals passed by the multiplexers 16, 18, 20 also change accordingly. Multiplexer 1
Reference numerals 6, 18, and 20 are composed of a decoder that decodes the window identifier, and a gate circuit that passes the corresponding window display signal according to the decoding result.

The window selection circuit 22 has priority register 1
They are provided corresponding to 0, 12, and 14, respectively. 2 ⁿ sets of AND gates 10a to 10n, 12a
~12n, 14a~14n, and 2 ⁿ -1 inverters 16a, 18 that invert the outputs of multiplexers other than the lowest priority multiplexer 20, respectively.
a, 19a and n OR gates 28a to 28n for sending the n-bit window identifier WID passed through a set (n) of AND gates conditioned by a multiplexer to the decoder 24. Since this configuration is basically the same as that of a well-known fixed priority circuit, details of the operation will be omitted. Note that each AND gate gates a corresponding one bit of the n-bit WID.

Decoder 24 decodes one window identifier WID selected by window selection circuit 22 and informs multiplexer 26 of the result.

The multiplexer 26 receives the image information of each window and outputs only the image information of the window decoded by the decoder 24. Image information here refers to image information in a broad sense, ie, all image information associated with each window, including memory addresses for reading the actual image from image memory, window background color, cursor, etc.

[Effects of the Invention] According to the above configuration, the display priority of each window on the display screen can be freely changed by simply changing the window identifier loaded into the priority register. Furthermore, by loading the same window identifier into all priority registers, display of other windows can be prohibited.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an address decoder for loading priority registers, FIG. 3 is a diagram showing an example of a window display on a display screen, and FIG. The figure shows a circuit for generating a window display signal.

Claims (1)

[Claims for Utility Model Registration] A plurality of priority registers in which the priority order is determined in advance and the identifier of each window can be arbitrarily set from the outside; a plurality of first multiplexers that receive a display signal indicating that a window should be displayed for each window and pass only the display signal of the window having an identifier set in a corresponding priority register; a window selection circuit that is connected to one multiplexer and outputs an identifier set in a corresponding priority register in response to a display signal of a window having the highest priority among the one or more display signals that have passed through the first multiplexer; , a decoder that decodes the identifier output from the window selection circuit, and a second multiplexer that receives the image information of each window and outputs the image information of the window whose identifier was decoded by the decoder. window priority circuit.