JPH0236201Y2 - - Google Patents

Description

[Detailed Description of the Invention] This invention relates to a reversible interlock circuit that prevents phase-to-phase short circuits in the main circuit during forward and reverse operation of a reversible electromagnetic contactor or solid state contactor.

FIG. 1 shows a conventional reversible interlock circuit. In FIG. 1, X1 and X2 are command contacts, _MCF is a forward contactor, and _MCR is a reverse contactor. Conventionally, the interlock when using a magnetic contactor is an electrical interlock that mutually inserts the auxiliary B contact into the main circuit, and a forced restriction on the operation of the crossbar of the magnetic contactor to prevent simultaneous ON. Mechanical interlocks are often used to prevent this. This is because electrical interlock alone may cause a short circuit between phases depending on the operation timing of the auxiliary b contact.

Furthermore, solid state contactors and the like cannot be provided with mechanical interlocks.

The present invention was developed in view of the conventional problems mentioned above, and its purpose is to create an electrical circuit that can reliably prevent phase-to-phase short circuits with a simple circuit suitable for reversible solid-state contactors, etc. The object of the present invention is to provide a reversible interlock circuit.

In order to achieve the above object, this invention controls the driving element 18a on and off using the output signal of the gate A2 which inputs the input signal A1 and the output signal B4 of the timer circuit 14b, and also controls the drive element 18a with the input signal B1 and the output signal B4 of the timer circuit The driving element 18b is controlled on/off by the output signal B2 of the gate 12b which receives the output signal A4 of the gate 14a, and the timer circuit 1
4a is the input signal A1 and the output signal B of the gate 12b.
2, and the time limit circuit 14b is operated with the input signal B1 and the output signal A2 of the gate 12a, thereby interlocking them.

Hereinafter, preferred embodiments of the present invention will be described based on the drawings.

FIG. 2 shows the configuration of the reversible interlock circuit according to this invention, and the time chart in FIG. 3 shows its operation.

An input signal A1 for a forward rotation command and an input signal B1 for a reverse rotation command are provided from transistors 10a and 10b, respectively. A forward rotation command is when the transistor 10a is turned on and the input signal A1 is at the L level, and a reverse rotation command is when the transistor 10b is turned on and the input signal B1 is at the L level.

Input signal A1 is connected to NOR gate 12a and time limit circuit 1
4a, and the input signal B1 is input to the NOR gate 12.
b and is input to the time limit circuit 14b. noah gate 1
The output signal B4 of the time limit circuit 14b is also input to 2a, and the output signal A2 thereof controls on/off the drive transistor 18a of the normal rotation side load 16a. Similarly, the output signal A4 of the timer circuit 14a is also input to the NOR gate 12b, and the output signal B2 thereof turns on/off the drive transistor 18b of the reverse side load 16b. Further, the output signal B2 of the NOR gate 12b is input to the time limit circuit 14a, and the output signal A2 of the NOR gate 12a is input to the time limit circuit 14b.
is input.

The timer circuit 14a and the timer circuit 14b have exactly the same configuration, and the NOR gate G1 receives the above two inputs.
, a capacitor C1 which is charged by the output of this via a diode D1 and a resistor R1, and a capacitor C
It consists of one discharging resistor R2, not gates G2 and G3 and resistors R3 and R4 for binarizing and shaping the voltage of the capacitor C1.

When either of the two inputs of NOR gate G1 is at H level, its output becomes L level, and capacitor C1 is discharged through resistor R2. When the two inputs of NOR gate G1 both go to L level and its output goes to H level, capacitor C1 is instantly charged. When the charging voltage of the capacitor C1 exceeds a certain level, the timer circuits 14a, 14
The output signals A4 and B4 of b are at the H level, and when the level is lower than that, the output signals A4 and B4 are at the L level. Even if the output signal of the NOR gate G1 changes from the H level to the L level, the output signals A4 and B4 do not immediately go to the L level because there is a discharge time for the capacitor C1, but after a certain period of time t, they reach the L level. Change. This time t is the interlock time.

In the above configuration, when both input signals A1 and B1 are at H level (off), the NOR gate 1
Output signals A2 and B2 from transistors 2a and 12b are both at L level, and drive transistors 18a and 18b are off. Also, at this time, both time limit circuits 14a and 14b
The output signals A4 and B4 are both at L level.

Therefore, when only the input signal A1 becomes L level (ON), the output signal A2 of the NOR gate 12a becomes H level, and the drive transistor 18a is turned on. At the same time, the capacitor C1 of the timer circuit 14a is charged, and its output signal A4 becomes H level.
The NOR gate 12b on the reverse side enters the prohibited state.

In the above state, input signal B1 is also at L level (on)
Even if the output signal A4 of the timer circuit 14a becomes H
Therefore, the output signal B2 of the NOR gate 12b remains at the L level, and the drive transistor 18
b is not turned on.

Next, assume that the input signal A1 becomes H level (off) while the input signal B1 remains at the L level (on). At this time, the output signal A2 of the NOR gate 12a immediately becomes L level, and the drive transistor 18a
turns off. Further, in response to A2=L and B1=L, the output signal B4 of the timer circuit 14b becomes H level, and the NOR gate 12a is inhibited. In the time limit circuit 14a, the capacitor C1 begins to be discharged, and the output signal A4 becomes L level after a delay of the interlock time t. Only at this time does the output signal B2 of the NOR gate 12b go high.
level, and the drive transistor 18b is turned on. The above operations are performed completely symmetrically on the forward rotation side and the reverse rotation side. Here, the interlock time t is effective when a command input from normal rotation to reverse rotation or from reverse rotation to normal rotation is given. In other cases, there is no delay in operation due to the interlock time t, and therefore inching only on the forward rotation side or only on the reverse rotation side (short-term intermittent drive) as shown in Figure 3.
can be done without any problem.

As explained in detail above, according to this invention, a reliable and good reversible interlock function can be realized with a simple electric circuit without relying on mechanical interlock, and it is suitable for solid state contactors etc. It becomes suitable.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional reversible interlock circuit, FIG. 2 is a block diagram of a reversible interlock circuit according to an embodiment of the invention, and FIG. 3 is a time chart showing its operation. Identical members in each figure are given the same reference numerals, A1, B
2 is an input signal, 12a, 12b are NOR gates, 1
4a and 14b are timer circuits, 16a and 16b are loads, and 18a and 18b are drive transistors.

Claims (1)

[Scope of utility model registration request] Input signal A1 and output signal B4 of time limit circuit 14b
The driving element 18a is controlled on/off by the output signal A2 of the gate 12a, which receives the input signal A2, and the driving element 18b is controlled by the output signal B2 of the gate 12b, which receives the input signal B1 and the output signal A4 of the timer circuit 14a. Configured for on/off control,
The time limit circuit 14a operates with the input signal A1 and the output signal B2 of the gate 12b as input,
When A1 is on and B2 is off, the output is turned off for a certain period of time after A1 changes from that state to off, and the output 14b of the time limit circuit is configured to output the input signal B1 and the above output signal. It operates with the output signal A2 of the gate 12a as input, and B
When 1 is on and A2 is off, and from that state B
1. A reversible interlock circuit characterized in that it is configured to turn off an output for a certain period of time after a signal 1 changes to OFF.