JPH023191A - Non-volatile memory circuit device - Google Patents

Abstract

PURPOSE:To decrease a consumption current and to improve the power source margin of a sense amplifier by impressing a potential, which is lower than a power source potential, to the gate of a transistor for column selection and precharging a node, for which the sense amplifier is connected, to the power source potential. CONSTITUTION:An intermediate potential generating circuit 8 generates a constant potential VDD which is lower than a power source voltage VCC and higher than a ground potential VSS and supplies it to a column decoder 9. The decoder 9 selectively supplies the potential VDD to the gate of a transistor 2 for column selection based on a column address. A sense amplifier 10 to be composed of NOR gate circuits 11 and 12 is connected to a node A. When a reading signal is 'H', a transistor 1 for precharge is turned on and the node A is precharged up to the potential VCC. Thus, since the circuit 8 only drives the gate of the transistor 2, the consumption current is decreased and the power source margin of the sense amplifier 10 is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a nonvolatile memory circuit device using nonvolatile transistors as memory cells.

(Prior Art) In recent nonvolatile memory circuit devices, if a power supply voltage is directly supplied to the drain of a memory cell when reading data, the memory cell may be destroyed or erroneous writing may occur. Therefore, in this type of memory circuit, it is necessary to keep the drain voltage of the memory cell low when reading data, and even in this case, it is necessary to ensure reliability during reading.

FIG. 8 is a circuit diagram showing the configuration of a conventional nonvolatile memory circuit device. Note that the writing circuit and the like are omitted for clarity of explanation. An intermediate potential output circuit 30 that outputs a potential lower than the potential VCC is provided between the positive power supply potential VCC and the node A. Further, one end of a plurality of column selection transistors 31 is commonly connected to the node A, and a bit line 32 is connected to the other end of each of these transistors 31. A plurality of word lines 33 are provided to intersect with these bit lines 32, and memory cells 34 made of nonvolatile transistors are arranged at positions where each bit line and word line intersect. The drain of each memory cell is connected to the corresponding bit line 32, the gate is connected to the corresponding word line 33, and the source of all memory cells is connected to the ground potential V.
Connected to SS.

Further, a sense amplifier 35 consisting of a voltage comparator configured by an analog circuit is connected to the node A. A potential slightly lower than the output potential of the intermediate potential output circuit 30 is supplied to the sense amplifier 35 as a reference potential V rel'.
outputs data Dout by comparing the potential of the node A with this reference potential V rer.

In the memory circuit having such a configuration, the potential of the node A is always set to the power supply potential V by the intermediate potential output circuit 30. It is set to a lower potential than C. Therefore, this low potential is applied to the drain of the selected memory cell when reading data, and the destruction of the memory cell and the occurrence of erroneous writing as described above are prevented.

However, the provision of the intermediate potential output circuit 30 limits the potential amplitude of the node A, and it is necessary to use a voltage comparator type sense amplifier with a complicated configuration using an analog circuit as the sense amplifier 35. Such a sense amplifier has problems in that it has a low power supply margin, is difficult to drive at a low voltage, and consumes a large amount of current.

Also, the memory cell 34 selected at the time of reading data
turns on, power supply potential VCC and ground potential VSS
Since a DC through current flows between the two, the current consumption further increases. Furthermore, there is a problem that the intermediate potential output circuit 30 requires a large current capacity, making its circuit configuration complicated.

(Problem to be Solved by the Invention) In this way, in conventional nonvolatile memory circuit devices, the potential to be detected by the sense amplifier itself is lowered to prevent memory cell destruction and erroneous writing, so low voltage It has drawbacks such as not being able to be driven with high power and high current consumption.

This invention was made in consideration of the above circumstances, and its purpose is to provide a nonvolatile memory circuit device that can be driven at low voltage and consumes low current without reducing reliability during reading. It's about doing.

[Structure of the Invention] (Means for Solving the Problems) A nonvolatile memory circuit device of the present invention includes a memory cell array provided with a plurality of memory cells made of nonvolatile transistors, and a drain of the memory cell connected to the memory cell array. a plurality of column selection transistors each having one end connected to each of the plurality of column lines and the other end commonly connected to a first node; a first polarity precharge transistor inserted between the node of the first polarity, a second polarity discharge transistor inserted between the source of the memory cell and the second potential, and an address input and a sense amplifier connected to the first node; and a sense amplifier connected to the first node. .

(Function) In the nonvolatile memory circuit device according to the present invention, the drain potential of the memory cell is kept low by applying a potential lower than the power supply potential to the gate of the column selection transistor. The potential supply circuit that supplies the gate potential to the column selection transistor only needs to charge the gate capacitance of the column selection transistor, and the current capacity of this potential supply circuit can be reduced (and the configuration can be simplified).

Furthermore, in this invention, the first node connected to the sense amplifier is precharged to the power supply potential by a precharge transistor, and when a memory cell is selected, the source of each memory cell is discharged by a discharge transistor. No DC through current is generated, and current consumption can be reduced. Moreover, since the first node to which the sense amplifier is connected is precharged to the first potential, which is the power supply potential, the potential amplitude of the first node becomes sufficiently large, and this first The connected sense amplifier can be configured using a logic gate circuit. Therefore, it is possible to improve the power supply margin and reduce current consumption in the sense amplifier.

(Examples) Hereinafter, the present invention will be explained by examples with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of a nonvolatile memory circuit device according to the present invention. Note that in this case as well, the writing circuit and the like are omitted for clarity of explanation. A precharging transistor 1 consisting of a P-channel MO3) transistor is inserted between the positive power supply potential VCC and the node A, which is a data detection node. A precharge signal P is supplied to the gate of this transistor 1. An upper node A1 is commonly connected to one end of a plurality of column selection transistors 2 made up of N-channel MOS transistors. A bit line 3 is connected to the other end of each column selection transistor 2. A plurality of word lines 4 are provided to intersect with these bit lines 3. These word lines 4 are connected to the row address is selectively driven by the output of the row decoder 5 to which the bit lines 3 and word lines 4 intersect.Memory cells 6 each made of a nonvolatile transistor having a floating gate structure are arranged at the intersections of each bit line 3 and each word line 4. The drain of each memory cell is connected to the corresponding bit 1913, and the gate is connected to the corresponding word line 4.The sources of all memory cells 6 are N-channel transistors (MO5). It is connected to the drain of the discharge transistor 7. The source of the discharge transistor 7 is connected to the ground potential VSS.

Reference numeral 8 denotes an intermediate Tl1i generation circuit which generates a constant potential VOO lower than the electric potential VCC and higher than the ground potential VSS. The potential vDD generated here is supplied to a column decoder 9 to which a column address is supplied. The column decoder 9 selectively outputs the potential vDD to the gate of the column selection transistor 2 based on the column address.

A sense amplifier IO is connected to the node A.

This sense amplifier 10 is composed of a flip-flop formed by cross-connecting the input and output of two CMOS type NOR gate circuits 11 and 12, and one of the NOR gate circuits 11 has the potential of the node A. The comparison potential V ref output from the comparison potential generation circuit 13 is supplied to the other NOR gate circuit 12 .

The comparison potential generation circuit 13 is composed of a transistor equivalent to the column selection transistor 2, and includes a transistor 14 whose gate is supplied with a potential equal to the constant potential VDD when selecting a memory cell, and the precharge transistor 1. A transistor 15 which is configured of a transistor equivalent to , and whose gate is supplied with the precharge signal Pr.
, a dummy cell 16 made of a non-volatile transistor similar to the memory cell 6 and set so that the source-drain current is approximately half that of the memory cell 6; It is composed of a transistor equivalent to the discharge transistor 1, and is composed of a transistor 17 whose gate is supplied with the precharge signal Pr.

Next, a data read operation in the memory circuit having such a configuration will be explained with reference to the timing chart of FIG. 3. First, the read control signal Rd is
” level, the precharge signal Pr is “L” level.
'' level, and the precharge transistor 1 is turned on.

As a result, node A is precharged to power supply potential VCC (precharge period Tp). At this time, the discharge transistor 7 is turned off, and the power supply potential V
No DC through current flows between CC and ground potential VSS. On the other hand, within the comparison potential generation circuit 13, the transistor 15 is turned on and the transistor 17 is turned off.
Node B connected to sense amplifier 10 is at power supply potential VC
Precharged to C. In this case, since nodes A and B are both at the VCC level, that is, the ``H'' level, the output data Dout of the sense amplifier 10 is at the ``L'' level.

Next, the column and row addresses ADD are supplied to the column decoder 9 and the row decoder 5, and the precharge signal P changes from the L level to the H2 level.

When the precharge signal Pr changes to the "H° level, the transistor 7 is turned on, and a period in which data is read begins (discharge period Td). First,
Each memory cell 6 is turned on by turning on the transistor 7.
The source of is set to ground potential. Further, one of the column selection transistors 2 is selected by the column decoder 9 according to the column address, and a constant potential vDD from the intermediate potential generation circuit 8 is applied to the gate of the selected transistor 2. This turns on the column selection transistor 2, but since its gate potential is lower than the power supply potential VCC, the bit line 3' connected to the column selection transistor 2 has a voltage lower than the power supply potential VCC. A potential is output. On the other hand, one of the word lines 4 is selected by the row decoder 5 according to the row address. As a result, a drive signal of "H# level" is applied to the gate of the memory cell 6 connected to the selected word line 4.

As a result, the memory cell arranged at the intersection of the selected word line and the bit line to which a potential lower than the power supply potential VCC is output is selected. If the threshold voltage of this selected memory cell is programmed to be low, this memory cell is turned on and the bit line 3 and node A are discharged to the ground potential VSS. If the threshold voltage of the selected memory cell is programmed to be high, this memory cell will be in an off state and bit line 3 and node A will not be discharged.

On the other hand, in the comparison potential generation circuit 13, when the precharge signal Pr changes to "H" level, the transistor I7 is turned on, and the column selection transistor 2
When any one of them is selected, the intermediate potential vDD is simultaneously supplied to the gate of the transistor 14. As a result, the potential of node B is discharged from VCC. Here, if the threshold voltage of the selected memory cell 6 is low and the potential of the node A is discharged, the current between the source and drain of the dummy cell 16 of the comparison potential generation circuit 13 is about half that of the memory cell 6. Therefore, the potential of node A approaches Vss faster than the potential of node B, and the output data D out of the sense amplifier 10 is inverted from 'L' level to 'H' level. If the threshold voltage of the selected memory cell 6 is high,
Since the potential of the node A is not discharged and the potential of the node B is discharged, the output data D out of the sense amplifier 10 remains unchanged at the original "L" level. In this way, data is read from the selected memory cell.

Here, since a potential lower than the power supply potential VCC is applied to each bit line 3, destruction of memory cells and erroneous writing can be prevented as in the prior art.

In addition, during the data read period, the first node A is precharged to the power supply potential by transistor 1, and then,
The source of each memory cell 6 is discharged to the ground potential by the transistor 7, and no DC through current is generated between the power supply potential and the ground potential. Therefore, current consumption can be reduced.

Furthermore, since the intermediate potential generation circuit 8 that generates a potential lower than the power supply potential only needs to drive the gate of the column selection transistor 2, the current capacity is small, reducing current consumption and simplifying the configuration. can be achieved.

Moreover, the potential of node A is the power supply potential V. Since the sense amplifier 10 changes between C and the ground potential VSS, a simple configuration using a logic gate circuit consisting of NOR gate circuits 11 and 12 as shown in the figure can be used, and the current consumption is also reduced. You can do less. Furthermore, if a CMOS configuration is used as the NOR gate circuits 11 and 12, the current consumption will be further reduced. Logic circuits constructed using the flip-flop method have advantages such as stable circuit operation over a wide voltage range, low power consumption, and low voltage driving.

FIG. 2 is a circuit diagram showing the configuration of another embodiment of the nonvolatile memory circuit device of the present invention. In this embodiment circuit, an intermediate potential VDD is connected to the gate between a node A, which is a common connection end of a plurality of column selection transistors 2, and the other end of the precharge transistor 1, one end of which is connected to the first potential. A level-down transistor 18 to which the bit line 3 is supplied is inserted, and the bit line 3 is selectively
is configured to supply a potential lower than the power supply potential VCC, which is the first potential. Accordingly, the power supply potential Vcc is supplied to the gate of the comparison potential generation circuit 13 between the dummy cell 16 and the transistor 14, and
A transistor 19 equivalent to the column selection transistor 2 is inserted.

The NOR gate circuit 11 in the sense amplifier 10 is configured to be supplied with the potential of the connection node C between the precharge transistor 1 and the level down transistor 18.

The data read operation in the embodiment shown in FIG. 2 is similar to the timing chart shown in FIG. 3 above. Also,
The device according to the embodiment shown in FIG. 2 is further superior in terms of the degree of integration. 1, that is, in the embodiment shown in FIG. 1, the intermediate potential VDD is supplied to the column decoder 9. Therefore, in the column decoder 9, a buffer (not shown) consisting of a CMO3 circuit or the like is installed in order to supply a potential lower than the first potential, power supply potential VCC, to each gate of the column selection transistor 2. Therefore, the pattern area tends to increase. In the embodiment shown in FIG. 2 above, it is sufficient to provide one level-down transistor 18 for a plurality of column selection transistors, so the pattern area is increased compared to when many buffers are provided as described above. is small.

Furthermore, since the capacitance and resistance of the column decoder increase as the capacity increases, there is an advantage that operational reliability is improved by reducing the number of delay elements such as buffers.

FIG. 4, FIG. 5, and FIG. 6 are circuit diagrams showing specific configurations of the intermediate potential generation circuit 8 used in each of the above embodiment circuits.

In the circuit shown in FIG. 4, a switching transistor 20 consisting of a P-channel MOS transistor and two resistors 21 and 22 are connected in series between the power supply potential Vcc and the earth potential VSS, and the switching transistor 20 is set to "L" when data is read. Signal to be leveled, e.g. read control signal Rd
The conduction is controlled by the reverse phase signal Rd.

In this circuit, the transistor 20 is turned off except during the data control period, and no current is consumed. On the other hand, during the data read period, the transistor 20 is turned on,
A potential VDD lower than VCC, which is resistance-divided by two resistors 21 and 22, is output.

In the circuit of FIG. 5, a switching transistor 23 consisting of a P-channel MOS transistor and a plurality of P-channel MO3) transistors 24 are connected in series between the power supply potential VCC and the earth potential VSS, and the switching transistor 23 is connected in series with the above signal Rd. It is designed to control conduction. In this circuit as well, the transistor 23 is turned off during periods other than the data read period, and no current is consumed. Further, during the data read period, the transistor 23 is turned on, and the switching transistor 23 and the plurality of transistors 24
A potential VOO lower than VCC, which is resistance-divided by , is output.

In the circuit of FIG. 6, a switching transistor 25 consisting of a P-channel MO transistor 5) and a depletion type N-channel M
An OS transistor 26 and an indolinic type (threshold approximately OV) N-channel MO3) transistor 27 are connected in series, and the output node D is connected to the transistor 26.
The switch transistor 25 is connected to the signal Rd.
The conduction is controlled by . Even in this circuit,
The transistor 25 is in an off state except during data read JtA, and no current is consumed. Further, during the data read period, the transistor 25 is turned on, and the drain voltage of the switching transistor 25 is changed to the transistor 2.
A voltage vDD lower than VCC divided by an on-resistance of 6.27 is output to node D. According to this configuration, since each gate of the transistors 26 and 27 and the node D are short-circuited, a constant intermediate potential is always output even if the power supply potential VCC fluctuates to some extent.

It goes without saying that the present invention is not limited to the above-mentioned embodiments, and that various modifications can be made. For example, the sources of each memory cell may be commonly connected to a discharge transistor 7, and this discharge transistor 7 may be shared by all memory cells, or
As shown in the circuit diagram of FIG. 7, an independent discharge transistor 7 may be provided for each memory cell 6. Furthermore, the intermediate potential generation circuit 8 and the sense amplifier 1
0 etc. are not limited to the illustrated configuration, and various circuit configurations can be used.

[Effects of the Invention] As detailed above, according to the present invention, a non-volatile memory circuit device is realized that simplifies the circuit without reducing the reliability during reading, consumes low power, and is driven at low voltage. can be provided.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a non-volatile memory circuit device according to the present invention, FIG. 2 is a circuit diagram showing the configuration of another embodiment of the non-volatile memory circuit device according to the present invention, and FIG. 1 and 2; FIGS. 4 to 7 are circuit diagrams showing partial configurations of the circuits in FIGS. 1 and 2, respectively; FIG. 8; 1 is a circuit diagram showing the configuration of a conventional nonvolatile memory circuit device. DESCRIPTION OF SYMBOLS 1... Precharge transistor, 2... Column selection transistor, 3... Bit line, 4... Word line, 5... Row decoder, 6.18... Memory cell, 7
. . . Discharge transistor, 8. Intermediate potential generation circuit, 9. Column decoder, 10. Sense amplifier, II. 12...NOR gate, 13...Comparison potential generation circuit, 14°17...N channel MO8) transistor, 1
5...P channel MOS transistor. 18... Level down transistor. Applicant's Representative Patent Attorney Takehiko Suzue

Claims (4)

[Claims] (1) A memory cell array including a plurality of memory cells made of non-volatile transistors; a plurality of column lines to which the drains of the memory cells are connected; one end of each column line is connected to each of the plurality of column lines, and the other end thereof is connected to the plurality of column lines; a plurality of column selection transistors commonly connected to the first node; and a first column selection transistor inserted between the first potential and the first node.
a polarity precharging transistor, a second polarity discharging transistor inserted between the source of the memory cell and a second potential, and a second polarity discharging transistor inserted between the source of the memory cell and the second potential; A nonvolatile memory circuit device comprising: potential supply means for selectively supplying a potential lower than the first potential; and a sense amplifier connected to the first node. (2) The nonvolatile memory circuit device according to claim 1, wherein the sense amplifier is constituted by a flip-flop consisting of a CMOS logic gate circuit that compares the potential of the first node with a comparison potential. (3) a memory cell array provided with a plurality of memory cells made of non-volatile transistors; a plurality of column lines to which the drains of the memory cells are connected; one end of each is connected to each of the plurality of column lines; a plurality of column selection transistors whose ends are commonly connected to the first node; a first polarity precharge transistor inserted between the first potential and the second node; and a source of the memory cell. and a second polarity discharge transistor inserted between the first node and the second node, the discharge transistor being inserted between the first node and the second node and having the gate connected to the first node when reading from the memory cell. A nonvolatile memory circuit device comprising: a level-down transistor of a second polarity to which a potential lower than the potential of is supplied; and a sense amplifier connected to the second node. (4) The nonvolatile memory circuit device according to claim 3, wherein the sense amplifier is constituted by a flip-flop consisting of a CMOS logic gate circuit that compares the potential of the second node with a comparison potential.