JPH02292818A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02292818A JPH02292818A JP11381089A JP11381089A JPH02292818A JP H02292818 A JPH02292818 A JP H02292818A JP 11381089 A JP11381089 A JP 11381089A JP 11381089 A JP11381089 A JP 11381089A JP H02292818 A JPH02292818 A JP H02292818A
- Authority
- JP
- Japan
- Prior art keywords
- mask
- junction
- ions
- semiconductor device
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 150000002500 ions Chemical class 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 8
- 238000005530 etching Methods 0.000 abstract description 6
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 239000010408 film Substances 0.000 abstract description 4
- 239000010409 thin film Substances 0.000 abstract description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、ＰＮ接合を有する半導体装置の製造方法に関
するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor device having a PN junction.
（従来の技術）
従来、エッチングにより段差のないマスクを形成し、こ
のマスク上方からイオン注入し，ＰＮ接合を形成する方
法が知られている。(Prior Art) Conventionally, a method is known in which a step-free mask is formed by etching, and ions are implanted from above the mask to form a PN junction.
この種の従来の半導体装置の製造方法について、第２図
により説明する。A conventional method of manufacturing this type of semiconductor device will be explained with reference to FIG.
同図は従来の半導体装置のＰＮ接合領域を示す要部拡大
断面図で、Ｐ形シリコンで構成された半導体基板１の表
面に、選択的なエッチングによりマスク２を形成した後
、Ｎ形の不純物イオンを注入し、Ｎ形拡敗層３を形成し
て、ＰＮ接合を構成していた。This figure is an enlarged cross-sectional view of the main part showing the PN junction region of a conventional semiconductor device. After forming a mask 2 by selective etching on the surface of a semiconductor substrate 1 made of P-type silicon, an N-type impurity is added. Ions were implanted to form an N-type diffusion layer 3 to form a PN junction.
（発明が解決しようとする課題）
しかしながら、上記の製造方法ではＰＮ接合面が円筒面
となり、平坦な接合面に比べ耐圧が低くなるという問題
があった。(Problems to be Solved by the Invention) However, in the above manufacturing method, there was a problem in that the PN bonding surface was a cylindrical surface, and the withstand voltage was lower than that of a flat bonding surface.
本発明は上記の問題を解決するもので、耐圧性の高いＰ
Ｎ接合の半導体装置の製造方法を提供するものである。The present invention solves the above problems and uses P
A method for manufacturing an N-junction semiconductor device is provided.
（課題を解決するための手段）
上記の課題を解決するため、本発明は、マスクに階段状
の段差をつける工程と、このマスクの上方から斜めにイ
オン注入する工程を備えるものである。(Means for Solving the Problems) In order to solve the above problems, the present invention includes a step of forming a step-like step on a mask, and a step of obliquely implanting ions from above the mask.
（作 用）
上記の構成により、マスクに階段状の段差をつけたマス
クを用い、斜め方向からイオン注入するため、形成され
るＰＮ接合面の円筒形状が緩和されるため、耐圧が高ま
る。(Function) According to the above configuration, since ions are implanted from an oblique direction using a mask having stepped steps, the cylindrical shape of the formed PN junction surface is relaxed, and the withstand voltage is increased.
（実施例）
本発明の実施例について、第１図（ａ）ないし（ｅ）の
主要工程のＰＮ接合領域を示す要部拡大断面図により説
明する。(Example) An example of the present invention will be described with reference to enlarged cross-sectional views of main parts showing the PN junction region in the main steps of FIGS. 1(a) to 1(e).
まず，第１図（ａ）に示すように、Ｐ形シリコンで構成
された半導体基板１の上に，マスク用薄膜４を形成した
後、第１図（ｂ）に示すように、エッチングにより開孔
部を有する第１マスク５を形成する。次に、第１図（ｃ
）に示すように第１マスク５を含む半導体基板１を覆う
マスク用厚膜６を化学的気相成長法（ＣＶＤ法）等によ
り形成した後、第１図（ｄ）に示すように，リアクティ
ブイオンエッチング（ＲＩＥ）等で異方性エッチングを
行い、第２マスク７と第１マスク５とで階段形状を構成
するように第２マスク７を形成する。次に第１図（ｅ）
に示すように、第１マスク５および第２マスク７の上方
から垂直に対して左右にそれぞれｌＯ度以上傾けた、矢
印Ａおよび矢印Ｂ方向から、それぞれイオン注入するこ
とによりＮ形拡散層３を形成する。First, as shown in FIG. 1(a), a masking thin film 4 is formed on a semiconductor substrate 1 made of P-type silicon, and then, as shown in FIG. 1(b), it is opened by etching. A first mask 5 having holes is formed. Next, Figure 1 (c
) As shown in FIG. 1(d), after forming a mask thick film 6 covering the semiconductor substrate 1 including the first mask 5 by chemical vapor deposition (CVD) or the like, as shown in FIG. Anisotropic etching is performed using active ion etching (RIE) or the like, and the second mask 7 is formed so that the second mask 7 and the first mask 5 form a step shape. Next, Figure 1(e)
As shown in FIG. 2, the N-type diffusion layer 3 is formed by implanting ions from above the first mask 5 and the second mask 7 from the directions of arrows A and B, respectively, which are tilted by more than 10 degrees to the left and right with respect to the vertical. Form.
これにより，第１マスク５の暎厚が薄く且つ斜め方向か
ら注入されるため、第１マスク５を通して浅く且つ第２
マスク７の端から外側に延びた形でイオンが注入され、
第１マスク５の開孔部に注入されてできるＰＮ接合の円
筒形状が緩和される。As a result, since the first mask 5 has a small depth and is implanted from an oblique direction, the first mask 5 has a shallow depth and the second
Ions are implanted extending outward from the edge of the mask 7,
The cylindrical shape of the PN junction formed by injection into the opening of the first mask 5 is relaxed.
これにより耐圧を１５％以上高めることができた。This made it possible to increase the breakdown voltage by 15% or more.
なお、第１マスク５の膜厚は、注入直後に第１マスク５
の下に形成されるＰＮ接合深さが、開孔部に形成される
ＰＮ接合深さの半分程度になるように選択する必要があ
る。Note that the film thickness of the first mask 5 is the same as that of the first mask 5 immediately after implantation.
It is necessary to select a depth such that the depth of the PN junction formed under the hole is about half of the depth of the PN junction formed in the opening.
また，本実施例では、Ｐ形シリコンで摘成された半導体
基板１にＮ形拡散層を形成したが，Ｎ形シリコンで構成
された半導体基板にＰ形拡敗層を形成してもよい。Furthermore, in this embodiment, the N-type diffusion layer is formed on the semiconductor substrate 1 made of P-type silicon, but the P-type diffusion layer may be formed on the semiconductor substrate made of N-type silicon.
（発明の効果）
以上説明したように、本発明によれば、階段状の段差を
設けたマスクを形成し、このマスクの上方から斜めにイ
オン注入しＰＮ接合を，形成することにより耐圧性の高
い半導体装置の製造方法が得られる。(Effects of the Invention) As explained above, according to the present invention, a mask having stepped steps is formed, and ions are implanted obliquely from above the mask to form a PN junction, thereby improving voltage resistance. A highly efficient method of manufacturing a semiconductor device can be obtained.
第１図（ａ）ないし（ｅ）は本発明による半導体装置の
製造方法の主要工程を示す要部拡大断面図、第２図は従
来の半導体装置の要部拡大断面図である。
１ ・・・半導体基板、 ２ ・・・マスク、 ３Ｎ形
拡敗層、 ４ ・・・マスク用薄膜、５・・・第１マス
ク， ６ ・・・マスク用厚膜、７・・・第２マスク。
第
図
特許出願人 松下電子工業株式会社FIGS. 1A to 1E are enlarged sectional views of main parts showing the main steps of the method of manufacturing a semiconductor device according to the present invention, and FIG. 2 is an enlarged sectional view of main parts of a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Mask, 3N type spreading layer, 4... Thin film for mask, 5... First mask, 6... Thick film for mask, 7... Second mask. Figure Patent Applicant Matsushita Electronics Industries Co., Ltd.
Claims (1)
の段差をつける工程と、このマスクの上方から斜めにイ
オン注入する工程を含むことを特徴とする半導体装置の
製造方法。1. A method for manufacturing a semiconductor device, which includes the steps of forming a step-like step on a mask and obliquely implanting ions from above the mask when forming a PN junction on a semiconductor surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11381089A JPH02292818A (en) | 1989-05-08 | 1989-05-08 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11381089A JPH02292818A (en) | 1989-05-08 | 1989-05-08 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02292818A true JPH02292818A (en) | 1990-12-04 |
Family
ID=14621627
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11381089A Pending JPH02292818A (en) | 1989-05-08 | 1989-05-08 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02292818A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6221779B1 (en) | 1992-07-28 | 2001-04-24 | Micron Technology, Inc. | Self-aligned process for making contacts to silicon substrates during the manufacture of integrated circuits therein |
-
1989
- 1989-05-08 JP JP11381089A patent/JPH02292818A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6221779B1 (en) | 1992-07-28 | 2001-04-24 | Micron Technology, Inc. | Self-aligned process for making contacts to silicon substrates during the manufacture of integrated circuits therein |
| US6414392B1 (en) | 1992-07-28 | 2002-07-02 | Micron Technology, Inc. | Integrated circuit contact |
| US6573601B2 (en) | 1992-07-28 | 2003-06-03 | Micron Technology, Inc. | Integrated circuit contact |
| US7276448B2 (en) | 1992-07-28 | 2007-10-02 | Micron Technology, Inc. | Method for an integrated circuit contact |
| US7282440B2 (en) | 1992-07-28 | 2007-10-16 | Micron Technology, Inc. | Integrated circuit contact |
| US7282447B2 (en) | 1992-07-28 | 2007-10-16 | Micron Technology, Inc. | Method for an integrated circuit contact |
| US7315082B2 (en) | 1992-07-28 | 2008-01-01 | Micron Technology, Inc. | Semiconductor device having integrated circuit contact |
| US7569485B2 (en) | 1992-07-28 | 2009-08-04 | Micron Technology, Inc. | Method for an integrated circuit contact |
| US7871934B2 (en) | 1992-07-28 | 2011-01-18 | Round Rock Research, Llc | Method for an integrated circuit contact |
| US8097514B2 (en) | 1992-07-28 | 2012-01-17 | Round Rock Research, Llc | Method for an integrated circuit contact |
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