JPH02299052A - Dma controller - Google Patents

Abstract

PURPOSE:To carry on operation automatically by setting the tail address and head address of a memory in respective storage means previously and loading the head address in an address counting means when access reaches the tail address. CONSTITUTION:The head address of the RAM is set in a head address register 8 and the tail address of the RAM is set in a tail address register 9. Further, the output of the address counter 1 is compared with their storage contents to monitor a DMA operation address and when the both match each other, a matching detection signal is generated. When the capacity of the DMA is not intermediate capacity of the storage area of the RAM and when the access address reaches the tail address in the middle of the DMA operation, the contents of a register 8 are loaded in the counter 1. The counter 1 counts up from the head address in the middle of the DMA operation. Consequently, when the address reaches the tail address in the middle of the DMA operation, the DMA operation address is set to the head address automatically and the DMA operation ends.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to DMA (Direct Memory Ac
c e s s) This relates to the controller.

[Conventional technology]

Conventionally, there is a DMA controller that allows data to be exchanged directly between a memory and an input/output interface without going through an MPU.

The DMA controller typically provides read and write access to addresses in memory while sending addresses that are incremented or decremented by a constant value toward the output interface.

FIG. 2 is a block diagram of a conventional DMA controller.

In this figure, 1 is an address counter and 2 is a buffer.

The address counter 1 is designed to count up using the clock DACK, and also loads the value of data 9t<s by the line and signal W from the control bus, and transfers the count contents to the data bus by the read signal R from the control bus. This is what is output to.

The count contents of the address counter 1 are also supplied to a buffer 2, and sent to the address bus from this buffer 2 in synchronization with the clock D ACK.

FIG. 3 is a block diagram when such a controller is used in connection with a communication line.

In this figure, 3 is a DMA controller, 4 is a DMA controller, and 4 is a DMA controller.
RAM targeted by A, 5 is the unread line control device, 6
is a pass line, and 7 is a communication line.

The DMA controller 3 starts the DMA operation in response to the request signal DREQ from the communication line control device 5, accesses the RAM 4, and at the same time starts the clock signal DAC.
K is supplied to the communication line control device 5.

Then, the communication line control device 5 receives this clock signal DAC.
Sends data to pass line 6 in synchronization with K and stores it in RAM 4.
The data on the pass line 6 is taken in and sent to the line 7.

By the way, the RAM 4 is often used in a ring buffer manner.

FIG. 4 is a conceptual diagram of the RAM 4.

In the same figure (A), 0000 is the start address of RAM4, and 1234 is the last address of the same RAM4, but the ring buffer is as shown in the same figure (B), as if the storage area is the start address 0000 and the end address 1234.
It can be seen as if they were connected like a ring.

Therefore, in the case of this ring buffer method, when the final address is reached during access, the access is continued by returning to the first address.

[Problem to be solved by the invention]

However, when this ring buffer method is used with the conventional DMA controller described above, it is sufficient that the DMA area falls within the middle of the area as shown by the symbol C in FIG. As shown in the figure, when the final address is reached during the access, the final address of the ring buffer varies depending on the system, so the DMA operation has to be performed in two separate steps, which increases the data transfer time. It had become.

The present invention has been made in view of the above-mentioned problems, and its purpose is to make it necessary to divide the DMA operation into two even if the capacity cannot be secured even when the final address of the memory is reached. The object of the present invention is to provide a DMA controller that completes its DMA operations without having to do so.

[Means to solve the problem]

The DMA controller of the present invention performs D
address counting means for increasing or decreasing the MA operation address by a constant value; first address storage means for storing the first address of the memory to be subjected to the DMA; final address storage means for storing the final address of the memory; The DMA operation address and the final address are compared, and when the two match, the address correction means loads the first address into the address counting means.

[For production]

According to the present invention, by setting the final address and the starting address of the memory in each storage means in advance, when the access reaches the final address, the starting address is loaded into the address counting means, and the DMA operation is automatically performed. It will now continue to that first address.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a DMA controller according to an embodiment of the present invention.

In this figure, 8 is the start address register,
The start address of the RAM 4 (though omitted in this figure, its address input terminal is connected to the address bus, and its data input/output terminal is connected to the data bus) is set in this start address register 8. Ru.

9 is a final address register, and this final address register 9 is used to set the final address of the RAM 4, and monitors the DMA operation address by comparing the output of the address counter 1 and its storage contents, so that both When a match occurs, a match detection signal 12 is generated.

10 is a multiplexer. This multiplexer 10
The signal from the data bus and the output of the first address register 8 are input as the select data, and when the coincidence detection signal 12 is not input from the last address register 9, the signal from the data bus is selected, When the match detection signal 12 is input manually, the output of the head address register 8 is selected.

11 is an OR gate, and the write signal W is manually inputted to the address counter 1 via this OR gate 11. The match detection signal 12 from the final address register 9 is also input to this OR gate 11, so that when the match detection signal 16 is issued, the first address output from the multiplexer 10 is loaded into the address counter. It has become.

Therefore, if the DMA capacity falls within the middle of the storage area of the RAM 4, the contents of the start address register 8 will not be loaded into the address counter 1 because the DMA operation address will never match the final address.

On the other hand, if the capacity of the DMA does not fit in the middle of the storage area of the RAM 4 and the address matches the final address during the DMA operation, the contents of the first address register 8 are loaded into the address counter 1, and the address counter 1 is stored in the middle of the DMA operation. will start counting up from the first address.

As a result, when the address reaches the final address during the DMA operation, the DMA operation address is automatically taken over by the first address, and the DMA operation is completed.

Therefore, by setting a predetermined address in register 8.9 in advance, even if the capacity cannot be secured even after reaching the final address of RAM 4, the DMA operation can be performed without having to divide the DMA operation into two. This will complete the operation.

〔Effect of the invention〕

As explained above, according to the present invention, by setting the final address and the starting address of the memory in each storage means in advance, when the access reaches the final address, the starting address is loaded into the address counting means, and the DMA Since the operation is automatically taken over to the first address, even if the memory capacity cannot be secured even after reaching the final address of the memory, there is no need to divide the DMA operation into two, and the D~ This has the effect that the IA operation can be completed.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a DMA controller according to an embodiment of the present invention, Fig. 2 is a block diagram of a conventional DMA controller, and Fig. 3 shows a system configuration when the DMA controller is connected to a communication line. Block diagram shown, No. 4
The figure is a conceptual diagram showing a memory buffer configuration. 1...address counter, 2...buffer, 4...
・RAM, 8...Start address register, 9...Last address register, 10...Multiplexer, 11...
...orgate.

Claims (1)

[Claims] address counting means for increasing or decreasing a DMA operation address by a fixed value for each DMA operation; a first address storage means for storing a first address of the memory to be subjected to the DMA; and a final address memory for storing a final address of the memory. and address correction means for comparing the DMA operation address and the final address and loading the first address into the address counting means when they match.