JPH02282999A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To simplify the program of a redundant memory cell and to eliminate the area of a pattern by using a redundant address generation circuit both for a write address and for a readout address. CONSTITUTION:When the address for write or the address for readout outputted from a decoder for write 6 and a decoder for readout 7 coincides with a redundant address outputted from the redundant address generation circuit 3, at the time of access, a coincidence signal is outputted from a coincidence detection circuit for write 4 or a coincidence detection circuit for readout 5. Thus, the decoder for readout 7 or the decoder for write 6 get in a deactivated state and a redundant decoder for readout or write 12 or 13 is activated, so that access to the redundant memory cell 15 is performed. Thus, the number of circuits or the scale of circuit is reduced in the redundant address generation circuit and the program of the redundant memory cell is simplified, then the area of the pattern is eliminated.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a first-in-first-out (hereinafter referred to as FIFO) type semiconductor memory device that can perform writing and reading simultaneously, and particularly to a first-in-first-out (hereinafter referred to as FIFO) type semiconductor memory device in which a defective memory cell exists inside. The present invention relates to a method for programming a redundant memory cell address in a redundant circuit for designating a spare redundant memory cell in place of a defective memory cell if the address is designated.

(Prior Art) Conventionally, a large-capacity FIFO type semiconductor memory device includes a memory cell array and a plurality of redundant memory cells for relieving defective memory cells, and accesses memory cells in seven memory cell arrays at high speed. Therefore, independent write address generation circuits and read address generation circuits are provided. The reason why two address generation circuits are provided is that in the case of FIFO operation, the write address normally takes the lead, the read address follows the write address with a certain address difference, and writing and reading are asynchronous and completely independent. This is because the read operation is subject to restrictions. Therefore, when a defective memory cell occurs during memory manufacturing, etc., the address of the redundant memory cell required to replace the defective memory cell with a redundant memory cell matches the read address or write address. A detection circuit and a redundant address generation circuit that generates addresses for redundant memory cells are provided independently for read addresses and write addresses, respectively. The read redundant address generation circuit and the read redundant address generation circuit are often of a type in which the address of a redundant memory cell is programmed by cutting a fuse to generate a predetermined redundant address.

For example, when a defective memory cell is detected during a probing test during manufacturing, programming is performed by cutting the fuse of the defective memory cell on the wafer using a laser or the like. . In this case, since two redundant address generation circuits are provided, one for continuous reading and one for writing, it is necessary to program the same address for reading and writing.

(Problems to be Solved by the Invention) However, the apparatus having the above configuration has the following problems.

Conventional semiconductor memory devices have separate redundant address generation circuits for writing and reading, so even when programming just one address, fuses in two circuits must be cut, and the redundant address generation circuit It takes twice as much time and effort as a general semiconductor memory device that does not have. In addition, the pattern area of the fuse portion needs to be twice as large as that of a standard semiconductor memory device, which hinders higher integration.

The present invention provides a semiconductor memory device that solves the problems of the prior art, such as complicating programming of redundant memory cell addresses and increasing the pattern size of the fuse portion.

(Means for Solving the Problem) In order to solve the problem, the present invention selects the memory cell by decoding a plurality of memory cells and redundant memory cells for storing data, and a write address and a read address, respectively. A FIFO type semiconductor memory device that is equipped with a write decoder, a read decoder, and a write redundant decoder and a read redundant decoder that respectively decode a redundant address and select the redundant memory cell, and is capable of simultaneous writing and continuous reading, as follows. This circuit is equipped with a circuit. That is, a redundant address generation circuit generates a predetermined redundant address when accessing a redundant memory cell, and a redundant decoder for writing detects whether or not the write address and the redundant address match and outputs a write match signal when they match. a writing circuit that activates only the redundant decoder for writing, and a circuit for reading that detects a match or mismatch between the read address and the redundant address and outputs a read match signal when there is a match to activate only the redundant decoder for reading. - a plurality of output circuits are provided in the semiconductor memory device;

(Function) According to the present invention, since the semiconductor memory device is configured as described above, at the time of access, the write address or read address output from the write decoder and the read decoder, and the output from the redundant address generation circuit. When the redundant address is matched with the redundant address, a match signal is output from the minus number construction circuit. As a result, the successive decoder or the write data becomes inactive, and the redundant decoder for reading and writing is activated, and the redundant memory cell is accessed. Therefore, the above problem can be solved.

(Embodiment) FIG. 1 is a diagram showing a schematic configuration example of a large capacity FIFO type semiconductor memory device showing an embodiment of the present invention.

This semiconductor memory device has write addresses WAO to WAO.
Write address generation circuit 1 that generates n, read address generation circuit 2 that generates read addresses RAO to RAn.
, and a redundant address generation circuit 3 that generates redundant addresses PO to Pn, and on their output sides are a write-number construction circuit 4, a read-number construction circuit 5, and a write decoder 6.
, and a reading decoder 7 are connected. A current decoder 6 and a redundant write decoder 8 are connected to the output side of the write-number configuration circuit 4, and a read-out decoder 7 and a read redundancy decoder are connected to the output side of the read-number configuration circuit 5. 9 is connected.

Here, the write address generation circuit 1 and the read address generation circuit 2 are composed of an address counter, a shift register, and the like. After the write address generation circuit 1 resets the address with the write reset signal WR, it is incremented by the write clock signal WCK, and the write address generation circuit 1 is incremented by the write clock signal WCK, and the write address generation circuit 1 is incremented by the write address WAO-WAn. The function to output to the decoder 6 is shown on the right. The read address generation circuit 2 has a function of resetting the address with the read reset signal RRT, and then being incremented by the read clock signal QRCK, and outputting the read addresses RAO, ~RArl to the read-number configuration circuit 5 and the read decoder 7. have. The redundant address generation circuit 3 generates redundant addresses P○ to Pn programmed in advance by cutting off the heat based on a one-pulse initial set signal IST output when the power is turned on. It has a function of outputting to the construction circuit 5.

The write-number configuration circuit 4 has write addresses WAO to W.
A match or mismatch between An and the redundant addresses PO to Pn is detected, and when they match, a write match signal 85 is output to deactivate the write decoder 6 and activate the write redundant decoder 8. This is a circuit that does this. The read-number configuration circuit 5 detects whether or not the read address RAO-RAn matches the redundant addresses RAO to RArl, and when they match, outputs a read match signal S5 and deactivates the read decoder 7. This circuit also activates the read redundant decoder 9.

The write decoder 6 is a circuit for decoding write addresses WAO to WAn, and the write redundancy decoder 8 is a circuit for decoding write addresses WAO to WAn.
A write line buffer 10 for storing data, a write redundant line buffer 12, etc. are connected to their output sides. The read decoder 7 is a circuit that decodes read addresses RAO to RArl, and the read redundant decoder 13 is a circuit that decodes a match signal 85. On their output sides, there is a read line buffer 11 for storing data, and a read line buffer 11 for storing data. A redundant line buffer 13 and the like are connected.

The write line buffer 10 and the read line buffer 111 are connected to the memory cell array 14 via a transfer gate circuit and a bit line (not shown). A plurality of redundant memory cells 1 through a non-transfer gate circuit and a redundant bit line
5. A row decoder 16 for word line selection is connected to the memory cell 14 and the redundant memory cell 5 via a word line (not shown).

2 and 3 are partial circuit diagrams showing the circuit example of FIG. 1. FIG.

As shown in FIG. 2, the redundant address generation circuit 3 includes a P-channel MOS transistor (hereinafter referred to as PMO8) 20 and a fuse 22 connected in series between a power supply potential VCC and a node N, and a fuse 22 between the node N and a ground potential VS2. An N-channel MOS transistor (hereinafter referred to as NMO3) connected between
) 21 and a latch circuit 23 consisting of two inverters connected to node N, and these circuits (
n+1> pieces are provided, and another one is provided to output a signature signal (detection signal) for determining whether or not redundancy is used.
There are a number of An initial set signal IST is input to the gates of the PMO 320 and NMO 321 of each of these circuits. The write-number output circuit 4 and the read-number output circuit 5 connected to the output side of the redundant address generation circuit 3 have the same circuit configuration. One of these days,
The write-number configuration circuit 4 has write addresses WAO to W.
It is equipped with (n+1> FOR gates (exclusive OR gates) 30 that detect coincidence and mismatch between An and redundant addresses PO-Pn, and one inverter 31 that inverts the signature signal S. n+1> EOs
On the output side of the R gate 30 and one inverter 31,
A NAND gate 32 for outputting a write match signal S4 is connected. A write decoder 6 and a write redundancy decoder 8 are connected to the output side of the NAND gate 32.

The write decoder 6 has the same circuit configuration as the read decoder 7, and has the same circuit configuration as the read decoder 7.
It is composed of a plurality of NAND gates 40 that take the NAND of , and a plurality of inverters 41 that invert the output of each of these NANO gates 40 . The write redundant decoder 8 is the same circuit as the successive redundant decoder 9, and is composed of an inverter 42 that inverts the write match signal S4.

Although not shown in FIG. 1, transfer gate circuits 50 and 51 are connected to the output sides of the write decoder 6 and the write redundant decoder 8, respectively. One transfer gate circuit 50 consists of a plurality of pairs of NMO3 that are controlled on and off by the output of each inverter 41, and the source or drain of each pair of NMO3 is commonly connected to a complementary data bus 52.52. ing. The other transfer gate circuit 51 consists of a pair of NMOs 8 that are controlled on and off by the output of the inverter 42, and the source or train of the NMOs 3 is connected to the data bus 52.52. A schematic circuit diagram of the drain or source side of the transformer 77 gate circuit 50 is shown in FIG.

In FIG. 3, the train or source side of the transfer 1 gate circuit 50 is connected to a write write buffer 10 consisting of a plurality of anti-parallel pairs of inverters, and the write line buffer 10 is further connected to the write line buffer 10 by a control signal C31. One ends of a plurality of complementary pairs of bit lines 61, 61 in the main cell array 14 are connected via a transfer gate circuit 60 consisting of a plurality of pairs of NMOs 3 that operate on and off. A plurality of word lines 62a and 62b are arranged perpendicularly to each bit line 61, 61, and a one-transistor dynamic RAM type memory cell 63, for example, is connected to each intersection of the word lines 62a and 62b. Each bit line 6
At the other end of 1.61, there is a transfer gate circuit 64 which is turned on and off by the control signal C32, and a transfer gate circuit 65 via the read line buffer 11.
are connected to the transfer gate circuit 65, and data buses 66 and 66 and a read decoder 7 are roughly connected to the transfer gate circuit 65. The transformer 71 gate circuits 64, 65, line buffer 11, and decoder 7 on the read side are constructed of the same circuit as on the write side.

The operation of the semiconductor memory device configured as described above will be explained.

When a defective memory cell exists in the memory cell array 14, in order to replace the defective memory cell with a redundant memory cell 15, the fuse 22 in the redundant address generation circuit 3 corresponding to the address of the defective memory cell is blown with a laser or the like. Cut it out and program it in advance.

The initial set signal IST input to the redundant address generation circuit 3 is a one-pulse signal output when the power is turned on, and is normally at the "building level. When the initial set signal @IST reaches (#H19), it is disconnected. The NMO321 at 22 fuses is turned on, and the node N connected to it becomes the ground potential VSS (="JILBEL"),
The "Ll level state" is held by the latch circuit 23.

In the 22 fuses that are not disconnected, NMO321 is turned on and the node N becomes "level" due to the "H" level of the initial set signal IST, but the initial set signal IS
The PMO 520 is turned on from "V" of T, and the node N is pulled up to the power supply potential VCC (="A level). In this way, the redundant addresses PO to l)n are output from the redundant address generation circuit 3 in response to the initial set signal IST. Here, the signature signal S in the redundant address generation circuit 3 is a signal that becomes "BI" when the fuse 22 on the signal@S side is cut during redundant use, and becomes H" when it is not cut.

At the time of access, the write address WAO-WAn output from the write address generation circuit 1 in FIG. 1 or the read address RAO output from the read address generation circuit 2 in FIG.
~RAn and the redundant addresses PO to Pn output from the redundant address generation circuit 3 do not match, the write match signals S4 and The read coincidence signal S5 becomes the "H" level. When the coincidence signal 34.S5 becomes H'', the write decoder 6 and the read decoder 7 are activated, and the signal is transmitted through the transfer 1 gate circuit 50.65. Bit line 61.61 and data bus 52, 52, 66.66
becomes connected.

At the same time, the redundant decoder 8 for writing and the redundant decoder 9 for reading become inactive, and the redundant bit lines (not shown) and the data buses 52, 52, 66, 66 are electrically is blocked.

In the case of a write operation, the write addresses WAO to WAn are decoded by the write decoder 6, and based on the decoding result, the data bus 52.
The serial input data on 52 is sequentially latched into the write line buffer 10. When all the serial input data is latched into the write line buffer 10, the transfer gate circuit 60 is turned on by the control signal C3I, and the data in the write line buffer 10 is transferred to the row decoder 16 via the bit lines 61 and 61. are written in parallel to the memory cell 63 selected by .

In the case of a read operation, the data of the memory cell 63 on the word line 628.62b selected by the row decoder 16 is read out, and after being amplified by a sense amplifier (not shown), the transformer turned on by the control signal O32 is read out. 77
The successive data is stored in parallel in the successive output line buffer 11 via the goat circuit 64. The read addresses RAO to RAn are decoded by the read decoder 7,
Based on the decoding results, the data in the read line buffer 11 is sequentially read out serially to the data buses 66 and 66 via the transfer gate circuit 65.

At the time of such access, the write address WAO
- When the read addresses RAO to RAn and the redundant addresses PO to Pn match, and the signature signal S of the redundant address generation circuit 3 is in the 14111 state, the match signal 34 of the -number configuration circuits 4 and 5, When the match signal 34.35 becomes 'bi', the write decoder 6 and the continuous output decoder 7 are all inactivated, and the bit lines 61.61 become the data bus 52.5.
2,66.66 and electrically cut off. At the same time, the redundant decoders 12.13 are activated, and the redundant hit lines (not shown) and data buses 52.52.66.66 are connected to the redundant memory cells 15 through the transfer gate circuits 51... Data is written or read.

This embodiment has the following advantages.

(i) Since the redundant address generation circuit 3 is configured to be used for both write addresses and read addresses, the number and scale of the redundant address generation circuit can be reduced. Therefore, for example, during mass production of semiconductor memory devices, it is necessary to cut the fuse 22 with a laser or the like to remove the redundant address PO-P.
When programming n, the effort required to cut the fuse can be significantly reduced, improving productivity.

(ii) When programming the redundant address generation circuit 3 by, for example, cutting a fuse, the pattern area of the fuse part is determined by the pitch of the fuse 12, etc. by a laser repair device for cutting the fuse, so it is difficult to reduce the pattern area. There are limits.

Therefore, even if the degree of integration of semiconductor memory devices increases due to improvements in miniaturization, the pattern area of the redundant address generation circuit portion does not become much smaller. Therefore, as in this embodiment, when the number and scale of the redundant address generation circuit 3 are reduced, the number of program fuses 22 is also reduced, making it possible to reduce the chip area. Further, by increasing the number of redundant memory cells 15 by using the space created by removing the pattern area of the redundant address generation circuit portion, the number of bits that can be repaired increases, thereby improving yield.

Note that the present invention is not limited to the illustrated embodiment, and the memory cell array 14 and the redundant memory cells 15 are arranged in a static RA.
It may be configured with M memory cells, or each peripheral circuit may be configured with circuits other than those shown.

(Effects of the Invention) As described in detail above, according to the present invention, the redundant address generation circuit is configured to be used for both write addresses and read addresses, so the number and scale of the redundant address generation circuit can be reduced. It can be made smaller, thereby simplifying programming of redundant memory cells and eliminating pattern area.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of a semiconductor memory device showing an embodiment of the present invention, and FIGS. 2 and 3 are partial circuit diagrams of FIG. 1. 1...Write address generation circuit, 2...
・Read address generation circuit, 3...Redundant address generation circuit, 4...Write match detection circuit, 5
. . . Match detection circuit for reading, 6 . . . Decoder for writing, 7 . . . Decoder for reading, 8
... Redundant decoder for writing, 9... Redundant decoder for reading, 10... Line buffer for writing, 11... Line buffer for reading,
12... Redundant line buffer for writing, 13.
...Redundant line buffer for reading, 14...
. . . Memory cell array, 15 . . . Redundant memory cell, 16 . . . Row decoder. Applicant Oki Micro Design Miyazaki Co., Ltd. (and 1 other person) Representative patent attorney Kyo Kakimoto

Claims (1)

[Scope of Claims] A plurality of memory cells and redundant memory cells for storing data, a write decoder and a read decoder that select the memory cell by decoding write addresses and read addresses, respectively, and decoding the redundant addresses, respectively. In a first-in/first-out type semiconductor memory device which is equipped with a write redundant decoder and a read redundant decoder that select the redundant memory cell by selecting the redundant memory cell, the first-in first-out type semiconductor memory device is capable of writing and reading at the same time. a write match detection circuit that detects whether or not the write address and the redundant address match and outputs a write match signal when they match to activate only the write redundant decoder; The present invention is characterized by further comprising a read match detection circuit that detects whether the read address matches or does not match the redundant address, outputs a read match signal when they match, and activates only the read redundant decoder. Semiconductor memory device.