JPH02250406A - Signal generating circuit - Google Patents

Abstract

PURPOSE:To prevent malfunction by connecting half latch circuits in cascade to constitute a shift register, and operating each half latch circuit with at least 3 clocks of equal phase having a pulse width whose duty ratio is <=1/3. CONSTITUTION:A pulse width control circuit 14 is provided to narrow the pulse width of reference clocks B1, B2, B3 thereby forming shift clocks phi1, phi2, phi3 and the shift register is shifted by using the clocks. Thus, a half latch circuits is used as a flip-flop constituting the shift register. Thus, the circuit scale of a charging signal generating circuit is considerably decreased. The shift register is operated by using the clocks phi1, phi2, phi3 whose width is narrowed with the same period and same phase difference with the clocks B1, B2, B3. Thus, latching is applied when the input data of each latch circuit is made stable and no racing takes place even when the half latch circuit is in use.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit technology and a technology that is particularly effective when applied to a sine wave signal generation circuit, such as a digital CODEC (encoder/decoder) for switching equipment. This invention relates to a technique effective for use in a billing signal generation circuit.

[Prior Art] A digital CODEC for an exchange is provided with a sine wave generating circuit that generates a billing signal to be transmitted to a public telephone. Conventional billing signal generation circuits generate sine waves of constant amplitude.

[Problems to be Solved by the Invention] Conventional billing signal generation circuits suddenly generate a sine wave (, Jl!) with a large amplitude and then suddenly interrupt the sine wave, resulting in overshoot or undershoot at the beginning and end of the signal. There is a problem in that noise is likely to occur due to the shoot, and as a result, the telephone device may recognize the noise at the beginning and the end of the billing signal as separate billing signals, causing the billing device to malfunction. Ta.

For the digital CODEC, see pages 59 and 60 of ``Microcomputer Handbook'' published by Ohmsha, December 25, 1985.

The above problem can be solved by creating a so-called ramp-like signal in which the amplitude of the generated sine wave gradually increases and gradually decreases. However, if an attempt is made to generate such a signal using existing technology, there is a risk that one circuit will be complex and considerably large in scale.

SUMMARY OF THE INVENTION An object of the present invention is to provide a signal generating circuit that can generate a ramp-shaped billing signal with a simple and small-scale circuit configuration without causing malfunctions due to noise.

The above and other objects and novel features of the present invention will become clear from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this publication will be summarized as follows.

In other words, a bias voltage that is the center of the generated sine wave and amplitude is applied to both terminals of the resistor ladder, and the switch connected between each node of the resistor ladder and the output node is connected to a shift circuit consisting of a half latch circuit. A ring counter that is sequentially controlled on and off by register output signals and generates three or more clocks with the same period and equally spaced phases, and logic that narrows the pulse width of the clock output from this ring counter. The shift register is operated using three or more types of clocks having relatively small pulse widths.

[Operation] According to the above-mentioned means, the amplitude of the sine wave can be gradually increased or decreased by the resistance ladder, and each latch means of the shift register forms a signal that sequentially controls the switches of the resistance ladder. In order to operate with a relatively small pulse width or lock, each latch can be configured with a half-latch circuit instead of a master-slave full-latch circuit. The circuit scale can be significantly reduced compared to the case where the configuration is configured.

[Embodiment] FIG. 1 shows an embodiment in which the present invention is applied to a billing signal generation circuit built into a CODEC.

In FIG. 1, 1 indicates, for example, a D/A converter and this D/A converter.
A sine wave generating circuit consisting of a read-only memory that stores on/off information of the switch in the A conversion, and 2 resistive elements R1 and R having the same resistance value.

...This is a resistance ladder formed by connecting Rn in series.

An up/down switching circuit 3 is provided between the resistance ladder 2 and the sine wave generation circuit 1, and the sine wave SIN generated by the sine wave generation circuit 1 and the bias voltage Ve, which is the center of the amplitude, are The voltage can be applied to both terminals of the resistance ladder 2 via the up/down switching circuit 3. Also, each connection node N1...Rn of the resistor R of the resistance ladder 2, R2...Rn. Switches MO8FET SWl and SW2''S are connected between N2...Nn and the output node No.
Wn is connected, and a voltage follower 4 is connected to the output node No.

The switches MO8FET SW1 to SWn are, for example, n half latch circuits H as shown in FIG. 2(A).
Control signals P, P2, . . . from the shift register 5 in which L, HL, .
- Controlled on and off in sequence by Pn.

The up/down switching circuit 3 is a pair of switches MO8FET that are controlled on/off by the output Q of the full latch circuit 11 that latches the signal generation start control signal MET.
A pair of switches MO3FET S controlled on/off by SW1□ and 5W12 output Q(7) inverted signal
It consists of W, , SW, .

MOSFET SW1□~SW, 4 (7) including SW,
1 is between the VB input terminal IN and the start end of the resistance ladder 2, and SW, 2 is the connection between the sine wave input terminal IN□ and the resistance ladder 2
5Wti is connected between the sine wave input terminal and the start end of the resistance ladder 2, and SW□ is connected between the Ve input terminal IN2 and the end of the resistance ladder 2. As a result, switches SW□ and 5W14 are turned on while the start signal MET is at a high level, and switches SW and 5WL2 are turned on while the start signal MET is at a low level, and the input relationship of the sine wave SIN to the resistor ladder 2 is reversed. be done.

In this embodiment, a master-slave type full latch circuit 11 as shown in FIG.
A pulse forming circuit 12 that forms a reference pulse S1 of a predetermined pulse width at the rise of ET, and three reference clocks B□, B, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , A ring counter 13 that generates B, and these reference clocks B, B, B,
The shift clock φ2. has a narrowed pulse width. φ2゜φ3
A pulse width control circuit 14 and the like that generate the pulse width are provided.

The reference pulse forming circuit 12 includes a full latch circuit FLT and an exclusive OR gate G1, and forms a reference pulse S1 having a pulse width corresponding to one period of the reference clocks C1 and c2. This reference pulse S□ is supplied to two cascade-connected full latch circuits FLT, , FLT, and their outputs S, , S and pulse S1 are ORed.
By being supplied to the gate G2, a control signal P□ having a pulse width three times the pulse width of the reference pulse S1 is formed, and this signal P1 is supplied to the switch SW1 of the resistance ladder 2 and also to the shift register 5. It is input to the data terminal of the first stage half latch HL□. Also, the signal P
1 is supplied to the AND gate G along with the clock φ, and the output signal of this gate G is connected to the clock φ and the half latch HLn-.

The output signal of the AND gate G4, whose input signal is the output signal, is supplied to the OR gate G.
n as a latch signal.

Next, the operation of the charge generation circuit of the above embodiment will be explained using the timing chart of FIG.

When the signal generation start control signal MET is changed to high level, a reference pulse S1 is formed, which activates the ring counter 13 and outputs the reference clock B1. B,,B
, is generated. Then, a shift clock φ0. φ2. φ is formed, and the shift register 5 is subjected to a shift operation. Then, control signals P1 to Pn, each having one-third of the pulse overlapped with each other, are sequentially formed, and the switches M connected to each node of the resistance ladder 2 are
SW supplied to O8FET SWl, SW, -8Wn
They are turned on in order from SWn to SWn. on the other hand,
When the start control signal MET changes to high level, the output of the full latch circuit 11 changes, thereby causing the MOSF
ET SW,, and SWi! is turned on. Therefore,
The sine wave SIN supplied from the sine wave generating circuit 1 is supplied to the terminal end of the resistor ladder 2 via the turned-on MO8FETS Wl, and the bias voltage VB is supplied to the starting end of the resistor ladder 2, respectively. Therefore, the output voltage to the voltage follower 4 is first divided by the amplitude of the sine wave SIN to 1/n, and as the switches SW1 to SWn are turned on in order, the voltage division ratio gradually increases and the amplitude increases. When the last switch SWn is turned on, a signal having the same amplitude as the input sine wave SIH is output.

Further, when the start control signal MET is changed to a low level, MOSFETs SW, , and SW are turned off,
Instead, 5Wxa and SW are turned on, so that a sine wave is supplied to the starting end of the resistance ladder 2, and a bias voltage VB is supplied to the terminal end.

On the other hand, since the reference pulse S is also formed in the pulse forming circuit 12 when the control signal MET falls, the ring counter 13 is activated in the same way as when the control signal MET rises, and the reference clock B1. B2. B, then shift clock φ1
．． φ2. φ is formed, and the control signals Pi to Pn are output in order from the shift register 5 again, and the switches SW1 to SW1 to
SWn is turned on from SWl to SWn.

As a result, the amplitude of the sine wave is compressed and outputted so that it gradually becomes smaller.

As described above, in the above embodiment, the pulse width control circuit 14 is provided to narrow the pulse width of the reference clocks B□, B, , H□, and then the shift clock φ1. Form φ3゜φ,
Since the shift register 5 is caused to perform a shift operation using this clock, a half latch circuit as shown in FIG. 2(A) can be used as a flip-flop configuring the shift register 5. The circuit scale can be considerably reduced.

That is, a shift register is normally constructed by cascading a master-slave type full latch circuit as shown in Fig. 2 (B) to prevent racing due to clock skew, but a charge signal generating circuit as shown in Fig. 1 The shift register 5 in is configured with a full latch circuit,
Duty 1/-3 with phases shifted by 1/3 period from each other
When the shift register is operated with the clock B1°,B,,B,, as can be seen from Figure 3, the input data of each latch circuit (output of the previous latch) and the change (falling edge) of the latch clock are Since the timings were simultaneous, there was a risk of erroneously latching data. However, in the above embodiment, the clock B1. B2°B, a clock φ1.B with the same period and the same phase difference, but with only a narrower pulse width. φ2
．． Since the shift register 5 is operated at φ, latching can be performed when the input data of each latch circuit is stable, and racing does not occur even when a half latch circuit is used.

Moreover, the charging signal generating circuit of the above embodiment is provided with an up/down switching circuit 3, so that the relationship between the voltages applied to both terminals of the resistor ladder 2 is reversed between the start of sine wave output and the end of output. ing.

Therefore, it is sufficient to simply shift the shift register 5 in the same direction both when starting and ending output. If you try to reverse the turn-on order of the switches SW1 to SWn of the resistance ladder at the start and end of output, you will need to shift the shift register in the opposite direction or use a multiplexer between the shift register and the resistance ladder. Although the circuit scale becomes large, the billing signal generating circuit of the above embodiment does not need to reverse the shift direction, so the circuit scale can be kept small.

Furthermore, in the billing signal generation circuit of the above embodiment, each
Switches SW to SW connected to each node of the resistance ladder 2 with 73 overlapping pulses P, P,...Pn
Since it is designed to control n, switches SW1~
SWn is not turned on one by one, but when the next switch is turned on, a period in which two adjacent switches are turned on simultaneously can be created. When the two switches are turned on simultaneously, it is possible to output a voltage that is between the voltages that would be cursed at the output node when each switch is turned on alone. As a result, a smoother output waveform (sine wave) can be obtained.

As explained above, in the above embodiment, the generated sine wave and bias voltage are applied to both terminals of the resistance ladder, and the switches connected between each node of the resistance ladder and the output node are connected from the half latch circuit. A ring counter generates three or more clocks with the same period and equally spaced phases, and the pulse width of the clock output from this ring counter is narrowed. By providing a logic circuit and operating the shift register using three or more types of clocks with relatively small pulse widths, the amplitude of the sine wave can be gradually increased or decreased using a resistor ladder. and each latch means of the shift register that forms a signal to sequentially control the switches of the resistor ladder.
In order to operate with a small pulse width or a lock, each latch can be configured with a half-latch circuit instead of a master-slave full-latch circuit. The effect is that the circuit scale can be significantly reduced compared to the conventional method.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above example,
The shift register is operated by three shift clocks φ□ and φ2゜φ□ whose phases are shifted by 1/3 period from each other, but four clocks φ whose phases are shifted by 1/4 period are used to operate the shift register.
It is also possible to operate the shift register by forming 1 to φ.

In the above explanation, the invention made by the present inventor was mainly applied to a billing signal generation circuit built into a CODEC, which is the field of application in which the invention was made, but the invention is not limited thereto. , can be generally used in semiconductor integrated circuits having shift registers.

[Effects of the Invention] The effects obtained by typical inventions disclosed in Hyohara are briefly explained below.

That is, in a CODEC with a built-in charging signal generation circuit, it is possible to realize a signal generation circuit that can generate a ramp-shaped charging signal without causing malfunction due to noise with a simple and small-scale circuit configuration.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of the configuration of a charging signal generation circuit in which the present invention is applied. FIG. 2 (A) is a circuit diagram showing an example of the configuration of a half latch circuit. FIG. FIG. 2 is a circuit diagram showing an example of a circuit configuration. FIG. 3 is a time chart showing the operation timing of the billing signal generating circuit of the embodiment. 2...Resistance ladder 3...Up/down switching circuit, 5...Shift register, 14...Pulse width control circuit.

Claims (1)

[Claims] 1. A resistance ladder circuit to which a sine wave generated by a sine wave generation circuit is applied to one terminal, and a connection node of each resistance element in this resistance ladder circuit and an output node. In a signal generation circuit that includes a group of switches connected in parallel and a shift register that generates a signal to turn on and off these switches in sequence, the shift register is configured by cascading half latch circuits, and each A signal generation circuit characterized in that a half latch circuit is shifted by at least three equal phase clocks having a small pulse width with a duty ratio of 1/3 or less. 2. The signal generating circuit according to claim 1, wherein the control signals for controlling the switch group generated by the shift register are formed so that their pulses partially overlap each other. 3. The signal generator according to claim 1 or 2, characterized in that a switching means is provided between the sine wave generating circuit and the resistance ladder circuit to switch the terminal to which the sine wave is supplied. circuit.