JPH02228814A - semiconductor logic circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor logic circuits, and particularly to semiconductor logic circuits using Schottky gate field effect transistors (MESFETs).

[Conventional Technology J] Integrated circuits using compound semiconductors such as gallium arsenide (GaAs) have attracted attention in recent years due to their high-speed, high-frequency operation and low power consumption, and their application to digital circuits is actively progressing. It is being In compound semiconductor circuits such as GaAs, transistors are different from silicon (Si),
It is often composed of MESFETs. As for logic circuits, which are important circuit elements of digital integrated circuits, various circuits using MESFETs are known.

Figure 2 shows DCF L (Direct Couple) which is a typical conventional circuit using MESFET.
2 shows an inverter circuit using an edPET Logic circuit. A depression type (D type) FET 21 for load and an enhancement type (E type) FET 22 for driving are connected in series between power supply terminals 23 and 24, and a load type FET 21 is connected in series between power supply terminals 23 and 24.
The output terminal 25 is connected to the source of 21, and the drive E-type FET
Input terminals 26 are connected to the gates of 22, respectively. Due to its simple structure, this circuit has come to be used in large-scale circuits, but as the circuit scale increases, the driving load of the wiring per gate increases, making it impossible to achieve sufficient high speed. Ta.

Therefore, as shown in Figure 3, an E
A circuit called a 5BFL circuit was considered, which includes a buffer 33 having a push-pull configuration using type FETs 31 and 32. Since this circuit has a high load driving ability, it is possible to prevent speed reduction due to wiring capacitance.

[Problem to be solved by the invention]

By the way, high-speed logic circuits using such MESFETs are ECLIil, which operates at relatively high speed among silicon integrated circuits, which are more popular than GaAs integrated circuits.
There is a need for shared use with roads.

In that case, the same signal level as the ECL circuit (-0, 8 to -
In order to obtain an output of 1.8 V), the power supply voltage is
It is necessary to use about 2.0V.

However, in such a relatively high power supply voltage, as shown in FIG.
When connected, when the output signal of the inverter 41 becomes high level, a through current as shown by a broken line 43 flows from the source follower FET of the inverter 41 to the inverter 42, resulting in a significant increase in current consumption.

An object of the present invention is to solve these problems.

[Means to solve the problem]

In order to solve the above problems, the semiconductor logic circuit of the present invention uses a driving E-type FET whose gate is connected to an input terminal.
, a load element connected between the drain of the driving E-type FET and the first power supply terminal, and a load element whose anode is connected to the driving E-type FET.
a first level shifter whose drain is connected to the first power supply terminal and whose gate is connected to the connection point between the load element and the drain of the driving E-type FET; A first E type FET for buffering is provided, the drain is connected to the source of the first E type FET for buffering, the source is connected to the second power supply terminal, and the gate is connected to the input terminal via the level shift means for signal transmission. The second E-type FET for the buffer, and the first E-type FET for the buffer.
The output terminal is connected to the source of the E-type FET, and the drain is connected to the connection point between the load element and the drain of the driving E-FET, and the source is connected to the driving E-FET through a third level shift means. The amplitude control type FET is connected to the source of the FET and has the gate connected to the output terminal.

[Effect]

When the output signal is at a high level, a current is supplied from the first E-type buffer FET to the gate of the next stage, and when the output signal is at a low level, current is extracted through the second E-type buffer FET. Due to this push-pull operation, the load driving capacity is high. In addition, the amplitude control type F
The ET detects the high level of the output signal, and the high level voltage of the output signal is suppressed to a value determined by the gate width ratio of the level shift diode and the first and second E-type FETs for buffer. Furthermore, a level shift diode is inserted between the source of the drive E-type FET and the power supply terminal, and the source potential of the drive E-type FET is raised from the power supply potential, so the logic amplitude can be increased. .

〔Example〕

FIG. 1 is a circuit diagram showing one embodiment of the present invention. DC by load type FET21 and drive E type FET22
An inverter is constructed using an FL circuit, and E-type buffer FETs 31 and 32 are further added to form an inverter using a 5BFL circuit.

Source of load type FET21 and drive E type FET22
A series circuit including an amplitude control type FET 1 and a level shift diode 2 is connected between the sources of the . The threshold voltage vth of the amplitude control type FETI is the same as that of the load type FET 21.

Diodes 3 and 4 are inserted between the drive E-type FET 22 and the power supply terminal 24, and between the input terminal 26 and the gate of the buffer E-type FET 32, respectively.

That is, the diode 3 is for level shifting, and its cathode is connected to the source of the driving E-type FET 22.
Its anode is connected to the connection point between the source of the buffer E-type FET 32 and the power supply terminal 24 . Further, the cathode of the signal transmission diode 4 is connected to the input terminal 26, and the anode thereof is connected to the gate of the E-type buffer FET 32.

The table below shows the threshold voltage V and gate of each element. An example of width W is shown below.

Next, the operation of this embodiment will be explained.

This embodiment operates with a single power supply of -2V. For example, the power supply terminal 23 is grounded, and the power supply terminal 24 is supplied with -2V.
is given.

First, the basic operation will be explained. When the input signal applied to the input terminal 26 becomes high level, the driving E type F
ET2°2 is turned on, and the source of the load type FET 21 becomes low level. This signal causes the buffer E type F
ET31 is turned off at 8 degrees.At this time, the E type FET for buffer
32 is turned on by the input signal, the output terminal 25
quickly becomes low level. Further, when the input signal becomes low level, the driving E type FET 22 is turned off, and the source of the load type FET 21 becomes high level.

Since this signal turns on the buffer E type FET 31 and the input signal turns off the buffer E type FET 32, the output terminal 25 quickly becomes high level.

In this basic operation, the amplitude control type FETI and the diode 2.3 function to prevent the output signal of the No. 1 level from rising more than necessary. That is, the amplitude control type FET 1 having the same threshold voltage vth as the load type FET 21 has an output signal applied to its gate, and detects that the output signal has reached a sufficiently high level. The gate voltage of the buffer E-type FET 31 is kept low. The maximum value of the voltage applied to the gate of the buffer E-type FET 31 is determined by the level shift voltage at the diode 2.3 and the gate width ratio of the buffer E-type FET 31.32, and by adjusting these, the output signal The high level of can be set to a desired voltage. In this way, the high level of the output signal is prevented from increasing more than necessary, so that the through current flowing from the buffer E-type FET 31 to the gate of the next stage can be suppressed to a low level.

In addition, the level shift diode 3 is a driving E-type FET.
Since the drive E-type FET 22 is inserted between the source of the FET 22 and the power supply terminal 24, the source potential of the driving E-type FET 22 is high, and therefore, the logic amplitude of the signal can be increased. Therefore, it is also possible to configure a NAND gate circuit by vertically stacking driving FETs. Note that the diode 4 can be changed to the driving E by inserting the level shift diode 3.
This is a signal transmission diode that is provided as the source potential of the type FET 22 increases.

In this example, in order to strictly control the high level of the output signal, it is desirable to use a level shift element similar to the gate current-voltage characteristics of an FET.
Although a Schottky diode 2.3 is used, other means may be used.

Furthermore, although a Schottky gate type FET is used for each FET, a junction gate type FET may also be used.

Further, although this embodiment is configured with an inverter which is the basis of a logic circuit, the present invention is not limited to this, and can be applied to OR circuits, NOR circuits, AND circuits, NAND circuits, latches and other circuits. It can also be applied to

〔Effect of the invention〕

As explained above, according to the semiconductor logic circuit of the present invention, the 5BFL circuit, which has a high load driving capability due to the push-pull operation buffer circuit, is provided with the amplitude control means composed of the D-type FET and the level shift means. Therefore, the high level of the output signal can be suppressed to a low level, and therefore, even when used at a high power supply voltage, the through-A current flowing into the gate of the next stage is reduced. Therefore, it is possible to realize a gate circuit with low current consumption while maintaining high load driving capability. Moreover, since the level shift diode is inserted into the source of the driving FET, the logic amplitude can be increased, and therefore the driving FETs can be stacked vertically. Therefore, it is possible to realize a logic gate circuit that not only has high load driving capability and low current consumption, but also has high logic capability.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing an inverter using a conventional DCFL circuit, FIG. 3 is a diagram showing an inverter using a conventional 5BFL circuit, and FIG. 4 is a diagram showing an inverter using a conventional 5BFL circuit. It is a circuit diagram in which two stages of circuits are connected. 1... FET for amplitude control 12.3.4... Diode for level shift, 21... FET for load. 22... E-type FET for driving 123. 24... Power supply terminal, 25... Output terminal, 26... Input terminal, 31.
32... E-type FET for buffer. Patent applicant: Sumitomo Electric Industries, Ltd. Representative patent attorney Yoshiki Hase
Salt 1) Tatsu Yakye Chenko Shin 4 rows Figure 1

Claims (1)

[Claims] 1. E-type FE for driving in which the input terminal is connected to the gate
T, a load element connected between the drain of the drive E-type FET and the first power supply terminal, and a load element whose anode is connected to the source of the drive E-type FET and whose cathode is connected to the second power supply terminal. a first E-type FET for buffering, the drain of which is connected to the first power supply terminal and the gate of which is connected to the connection point between the load element and the drain of the driving E-type FET; A second E-type FET for buffering is connected to the source of the first E-type FET, the source is connected to the second power supply terminal, and the gate is connected to the input terminal via the signal transmission level shift means; and the first E-type FET for buffering.
an output terminal connected to the source of the drive E-type FET, a drain connected to a connection point between the load element and the drain of the drive E-type FET, and a source connected to the source of the drive E-type FET via a second level shift means. A semiconductor logic circuit comprising an amplitude control D-type FET connected to each other and having a gate connected to an output terminal. 2. The semiconductor logic circuit according to claim 1, wherein the driving E-type FET is composed of a plurality of E-type FETs connected in parallel or in series. 3. A D-type FET whose source and gate are short-circuited is used as the load element, and the gate width of the D-type FET for amplitude control is 0.5 times or more the gate width of the D-type FET for the load element. 3. The semiconductor logic circuit according to item 1 or 2.