JPH02228168A - Image reading device - Google Patents

Abstract

PURPOSE:To prevent the deterioration of image by providing level correcting means before and after a synthesizing means which synthesizes outputs of channels into a series signal, eliminating the level difference between channels, and adapting the output to a required level of an A/D converter. CONSTITUTION:The DC level of the dark output part of an odd picture element signal 101a is clamped at about 0V by a clamp amplifier 104a. An even picture element signal 101b is set to such reference level by a clamp amplifier 104b and a voltage control circuit 109, to which data is set by a CPU, that the offset level difference between odd and even picture element signals is eliminated. Both signals are multiplexed to a series picture element signal of one line by a multiplexer 105, and this signal has the white level set to a maximum value of the dynamic range of an A/D converter 108 by a variable amplifier 106 and has the dark level set to a minimum range by a clamp amplifier 107. Thus, the level difference between outputs is eliminated to adapt levels to the range of the A/D converter, thereby preventing the deterioration of image.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a document reading device, and more particularly to a document reading device using a multi-channel image sensor that transfers charges through a plurality of channels.

[Conventional technology]

FIG. 7 shows a conventional document reading device.

In the figure, 901 is a 3-line color CCD image sensor, and a dual channel CCD image sensor 901 is a 3-line color CCD image sensor.
02 to 904, and the charges of odd-numbered pixels and even-numbered pixels are transferred separately, and R, G, and B organic color separation filters are arranged on the sensor element.

71a.

71b is a buffer amplifier? 2a and 72b are output signals V of the image sensor. ! A sample hold circuit (S/H) for removing reset noise included in IA + VO 311. 73a and 73b are output signals V when reading a white board. Variable amplifiers 74a and 74b are output signals VOIAIVos for adjusting the level of SA+VO5II. , and corrects the level difference between GND (
= OV) Clamp amplifier that clamps to the level, 75a
, 75b amplifies the output signal V O8A t vosi;
An A/D converter converts the clamped signal into digital data, and 76 is an output signal VOfi converted to a digital value.
This is a selector circuit that switches A+VO1l for each pixel and converts it into the original one-line read signal.

FIG. 9 shows the configuration of the 3-line color CCD image sensor 901 shown in FIG.

In the figure, 91 is a light receiving section that performs photoelectric conversion depending on the amount of incident light. On the CCD sensor element of this light receiving section 91, R, G, and B color separation filters are arranged on-wafer.

Reference numerals 92 and 93 designate transfer gates, which shift gate pulses φa to transfer the charges accumulated in the light receiving section 91.

The data is transferred to the CCD shift registers 94 and 95 in accordance with the data. The charges accumulated in even-numbered pixels of the light receiving section 91 are transferred to each CO for even-numbered pixels by each transfer gate 93.
Charges transferred to the D shift register 95 and accumulated in odd-numbered pixels of the light receiving section 91 are transferred by each transfer gate 92 to each COD shift register 94 for odd-numbered pixels. The CCD shift registers 94 and 95 perform COD transfer (complete transfer) of the charge sent from the light receiving section 91 side to the output section, and use the driving clock φ.

(φ3.l, φIFII + φ1c,, φIFG +
φ16. φIFB ) and φ2 (φ,,φ1..φ,
6. φ□. , φ, 8°φ, □). Reference numeral 96 denotes an output gate, which sends charges from each COD shift register 94, 95 to output capacitor sections 97a, 97b. Reference numerals 97a and 97b are output capacitance sections that convert transferred charges into voltage. 98a,
98b is a two-stage source follower amplifier that lowers the output impedance and prevents noise from being added to the output signal.

Output capacitance sections 97a and 97b and source follower amplifier section 9
FDA (Floating Di
fffusion amplifier).

08AR, 08BR, 03AG, 08BG.

03AB, 08BBI;! Signal output terminal, φRAR.

φRBR, φRAG, φRBG, φRAB,
φRBB is a reset pulse terminal, φIR, φIG.

φIB, φ2R, φ2G, φ2B are CCD shift register clock terminals, φIFR, φ2FR, φIF
G, φ2FG, φIFB, and φ2FB are CCD shift register final stage clock terminals, φTGR.

φTGG and φTGB are transfer gate clock terminals, and ODR, ODG, and ODB are source follower amplifier drain terminals.

In the color image sensor 901 configured as described above, the light incident on the light receiving section 91 is converted into an electric charge proportional to the amount of light, and this electric charge is transferred to the CCD shift register 95.94 by a shift gate pulse φTG to even pixels, odd pixels The driving clock φ1.
According to φ2, one bit at a time is outputted to the FDA via the output gate 96 at the timing shown in FIG. It is output via amplifiers 98a, 98b and respective output terminals O8A, O8B.

When no light is applied to the light receiving section 91, the potentials applied to the even and odd CCD shift registers 95 and 94 are slightly different, so the dark output levels output from the output terminals O8A and O8B are different.

However, the conventional document reading device outputs the output signal V. sA.

A separate processing system performs signal processing such as amplification, DC clamping, and A/D conversion on the V o ss, and outputs the output signal VOIA.
After removing the level difference between IVosa, we digitally multiplexed each pixel to obtain one line of image signal during reading, so two systems of variable amplifiers and A/D converters were required. However, there was a limit to the cost reduction of the equipment.

Therefore, a configuration as shown in FIG. 8 can be considered.

In the figure, 901 indicates the same part as in FIG. 7. In this embodiment, the signal processing systems for the output signals of the R, G, and B CCD image sensors have the same circuit configuration, so the R COD image sensor will be described.

802a and 802b are buffer amplifiers, each with an R-CO
It receives the odd pixel signal 801a and the even pixel signal 801b of the D image sensor 902 and performs impedance conversion. 803a.

Reference numeral 803b denotes a sample and hold circuit (S/H) that removes reset noise contained in the odd-numbered pixel signal 801a and even-numbered pixel signal 801b of the R-CCD image sensor 902, which are outputted in time series. 804a, 8
04b is a clamp amplifier as a correction means, and each includes an amplifier 804a-1, 804b-2 and a clamp circuit 804.
The clamp amplifier 804a clamps the DC offset level of the odd pixel signal from which reset noise has been removed by the sample and hold circuit 803a to Ov, and the clamp amplifier 804b uses the sample and hold circuit 803b to clamp the DC offset level of the odd pixel signal to Ov. The DC offset level of the even pixel signal from which reset noise has been removed is clamped to the same level (OV) as the clamp amplifier 804a. 805 is a multiplexer as a combining means,
Odd pixel signals and even pixel signals are input from the clamp amplifiers 804a and 804b, and the odd pixel (ODD) signal and even pixel (
EVEN) signal and R as shown in Figure 9.
- Serial pixel signals are obtained in the order of pixel arrangement of the light receiving section of the CCD image sensor 902.

Reference numeral 806 denotes a variable amplifier as variable amplification means, which amplifies the output level of the serial pixel signal outputted in time series by the multiplexer 805 up to the dynamic range of the A/D converter 808. A clamp amplifier 808 clamps the DC offset level of the serial pixel signal amplified to the dynamic range of the A/D converter 808 by the variable amplifier 806 to the lowest reference level of the A/D converter 808, that is, Ov. be.

The A/D converter 808 converts an analog pixel signal, which is a serial pixel signal whose DC offset has been corrected by the clamp amplifier 807, into a digital pixel signal.

Next, the operation will be explained using the R-CCD image sensor 902 as an example.

The structure of the CCD of the sensor 902 is a dual channel type, and the odd and even charges of the sensor pixel 91 are separated into separate CO
Since the transfer is performed by the D shift registers 94.95, the difference in the potentials of the odd and even COD shift registers 94.95 causes a difference in the output DC offset level of the odd and even pixels.

Output signal 801 of R-COD image sensor 902 having a difference in output DC offset level between odd and even pixels
After impedance conversion is performed by buffer amplifiers 802a and 802b, signals a and 801b are input to sample and hold circuits 803a and 803b. This input signal is processed by sample and hold circuits 803a and 803b.
According to the timing shown in FIG. 2 (8) and (9), the reset noise contained in the input signal is sampled and held, and then the respective clamp amplifiers 804a and 804a
04b.

Then, by the clamp amplifiers 804a and 804b, R
- The DC output level of the dark output section from the CCD image sensor 902 is compared with a predetermined reference level Ov, and the DC level of the dark output section is clamped to Ov. Therefore, the odd pixel signal and the even pixel signal are clamped to the same reference level, and the DC offset level difference between the odd pixel and even pixel signals that existed in the output signals of the sample and hold circuits 803a and 803b is removed.

The odd-even side pixel signals clamped to the same reference level (Ov) are sequentially switched and selected by the multiplexer 805 based on the timing shown in FIG. Combined into a serial pixel signal. The arrangement of the serial pixel signals synthesized by the multiplexer 805 is the same as the pixel arrangement order of the light receiving section.

The serial pixel signals synthesized by the multiplexer 805 are amplified by the variable amplifier 806, and when the reference white plate is read and scanned by the R-CCD image sensor 902, the output level reaches the maximum value of the dynamic range of the A/D converter 808. is approximately approximated. The R signal, which is regulated by the variable amplifier 806 to the maximum value of the dynamic range of the A/D converter at the white level, is controlled by the clamp amplifier 807 to have an output level at the dark time of the A/D converter 8.
It is clamped to the lowest level of the 08 dynamic range.

In this way, the R signal whose maximum value and minimum value are regulated with respect to the dynamic range of the A/D converter 808 is
A D converter 808 converts it into a digital image signal.

The R-CCD image sensor has been explained above, but
Since the operations of the G-CCD image sensor 903 and the BCCD image sensor 904 are essentially the same, the explanation will be omitted.

[Problem to be solved by the invention] However, in the conventional document reading device described above, the clamp amplifier 804a
, 804b, even when trying to clamp to the same reference level (Ov), the difference between even and odd pixels after multiplexing is caused by variations in the clamp level due to the clamping accuracy of the clamp amplifiers 804a and 804b, and offset errors between each channel when multiplexing the multiplexer 805. Even if there is a slight difference in the offset level, the variable amplifier 806 and clamp amplifier 807 after multiplexing
The slight difference in offset level is amplified and expanded by A/
This will appear as an offset level difference in the data after A/D by D808.

In addition, since an offset level difference occurs between even and odd pixels, the clamp amplifier 807 causes the A/D converter 80 to
Even if an attempt is made to clamp to the reference lowest level of No. 8, an error will occur and it will not be possible to clamp to the target level.

SUMMARY OF THE INVENTION An object of the present invention is to provide a document reading device that can solve the above-mentioned problems and prevent image deterioration.

[Means for solving problems]

In order to achieve such an object, the present invention provides a multi-channel image sensor having a plurality of charge transfer channels, a separate output section for each charge transfer channel, and a system that uses one of the output signal levels of each charge transfer channel as a reference. a first correction means for correcting the signal level, a second correction means for varying the level of the other signal with respect to the reference level, and a synthesis means for synthesizing both the pixel signals in the same order as the arrangement of the light receiving sections of the image sensor. It is characterized by comprising: variable amplification means for amplifying the pixel signals synthesized by the synthesis means; and third correction means for correcting the output signal of the amplification means to an arbitrary level.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows an embodiment of the invention. In the figure, the color image sensor 901 shows the same part as in FIG.

In this embodiment, since the signal processing systems for the output signals of the R, G, and B CCD image sensors have the same circuit configuration, the R CCD image sensor will be explained.

102a and 102b are buffer amplifiers, each with an R-CC
It receives the odd pixel signal 101a and the even pixel signal 101b of the D image sensor 902 and performs impedance conversion. 103a.

Reference numeral 103b denotes a sample and hold circuit (S/H) that removes reset noise included in the odd-numbered pixel signal 101a and even-numbered pixel signal 101b of the R-CCD image sensor 902, which are output in time series.

104a and 104b are clamp amplifiers as correction means, each of which is composed of an amplifier 104a-1, 104b-1 and a clamp circuit 104a-2, 104b-2,
The clamp amplifier 104a is the sample hold circuit 10
DC of odd pixel signal with reset noise removed in 3a
The offset level is clamped to the reference level V,,,,,=OV, and the clamp amplifier 104b outputs the DC offset level of the even pixel signal from which reset noise has been removed by the sample and hold circuit 103b to the voltage control circuit 1.
This is to clamp to the reference level VreL2 output from 09.

105 is a multiplexer as a combining means, which inputs the odd pixel signal and even pixel signal from the clamp amplifiers 104a and 104b, and sequentially outputs the odd pixel (ODD) signal and the even pixel signal at the timing shown in FIG. 2 (10). EVEN
) signal and R-CCD as shown in Fig. 9.
Serial pixel signals are obtained in the order of pixel arrangement of the light receiving section of the image sensor 902.

Reference numeral 106 denotes a variable amplifier as variable amplification means, which amplifies the output level of the serial pixel signal outputted in time series by the multiplexer 105 up to the dynamic range of the A/D converter 108, and outputs from the voltage control circuit 110. A voltage-controlled amplifier ('olt
age Control Aaplbier:VCA)
It is made up of.

107 is a clamp amplifier, and the variable amplifier 106
The DC offset level of the serial pixel signal amplified to the dynamic range of the /D converter 108 is set to the control voltage V of the voltage control circuit 111. The lowest reference level V noa of the A/D converter 108 according to the NTI.

It is clamped at v (in this embodiment, ■8°□a.□=Ov). A/D converter 108 is clamp amplifier 1
The analog pixel signal, which is a serial pixel signal subjected to DC offset correction in step 07, is converted into a digital pixel signal.

Here, the voltage control circuits 109, 110° 111 will be explained.

According to FIG. 3, the voltage control circuit 109 is composed of an 8-bit multiplication type D/A converter 109a, operational amplifiers 109b and 109c, and resistors R and 2R. The value of the reference human power V t s I is multiplied by four quadrants according to the CPU setting data value (not shown), for example, CPU setting data output voltage 00H-V,... /128 (V)↓
An output voltage of ↓ 80□ 0 [v] ↓ ↓ FFH+V, , /128 (V) is output.

Since voltage control circuits 110 and 111 have the same configuration, voltage control circuit 110 will be representatively described.

Voltage control circuit 110 is voltage control circuit 1
Similarly to 09, an 8-bit multiplication type D/A converter 110a,
Consists of an operational amplifier 110b (Fig. 4)
, reference human power V of the multiplication type D/A converter 110a
r # The value of l is multiplied by two quadrants according to the CPU setting data value, for example, CPU setting data Output voltage 00, O[V] ↓ ↓ 80 n V □+ / 128 C
V) ↓ ↓ FF-V = -r (V). Output as NTI + VCONT2.

Here, the difference between the voltage control circuits 110 and 111 is that the voltage control circuit 110 is a voltage control amplifier (VC
A) 106 control voltages V,. 9A, whereas the voltage control circuit 111 is the clamp amplifier 107.
The setting value of the clamp level to be clamped is controlled, and this clamp level is the lowest reference level V of the A/D converter 108. 77°, which is almost the same. Therefore, the reference power v, l of the multiplier type A/D converter 110a of the voltage control circuits 110, 111 differs depending on the voltage to be controlled.

Next, the operation will be explained using the R-CCD image sensor 902 as an example.

The structure of the CCD of the sensor 901 is a dual channel type, and the odd and even charges of the sensor pixel 91 are separated into separate CCs.
Since the transfer is performed by the D shift registers 94.95, the difference in potential between the odd and even CCD shift registers 94.95 causes a difference in the output DC offset level of the odd and even pixels.

Output signal 101 of R-CCD image sensor 902 having a difference in output DC offset level between odd and even pixels
After impedance conversion is performed by buffer amplifiers 102a and 102b, signals a and 101b are input to sample and hold circuits 103a and 103b. This input signal is processed by sample and hold circuits 103a and 103b.
According to the timing shown in FIG. 2 (8) and (9), the reset noise contained in the input signal is sampled and held, and then the clamp amplifiers 104a and 1
04b.

Then, the clamp amplifier 104a compares the DC output level of the dark output section from the R-CCD image sensor 902 with a predetermined reference level V, . . . = OV, and the DC level of the dark output section is clamped to approximately Ov. Ru.

The other output signal of the R-CCD image sensor 902 is sent to the clamp amplifier 104 by the clamp amplifier 104b.
Similarly to a, the reference level V r a l 2 is clamped to the reference level V r a l 2, but in this case, the reference level V r s l 2 is the ODD of the COD output signal that is finally converted into a digital pixel signal by the A/D converter 108. In this embodiment, the difference between the output data of /EVEN is detected by a CPU (not shown),
In this embodiment, the reference level Vrs+1 of the clamp amplifier 104a on the ODD side is fixed at 0■, so that the CPU (not shown) outputs a voltage according to the detected value so that the difference between ODD/EVEN disappears in the digital pixel signal. By setting data in the control circuit 109 and setting the reference level V +all, the DC offset level difference between the odd pixel signal and the even pixel signal is removed.

The odd pixel signal from which the DC offset level difference between the odd and even pixels has been removed is sent to the multiplexer 105 as shown in FIG.
) Odd number pixel signals and even number pixel signals are sequentially switched and selected and combined into one line of serial pixel signals.

The arrangement of the serial pixel signals synthesized by the multiplexer 105 is the same as the pixel arrangement order of the light receiving section.

The serial pixel signals synthesized by the multiplexer 105 are amplified by the variable amplifier 106, and when the reference white plate is read and scanned by the R-CCD image sensor 502,
The output level is approximately approximated to the maximum value of the dynamic range of the A/D converter 108.

Here, the amplification degree of the variable amplifier 106 is set by a clamp amplifier 107, which will be described later, for the R-CCD image sensor 502.
After adjusting the dark output level of the A/D converter 108 to be the lowest level of the dynamic range of the A/D converter 108, the reference white plate is read and the output data of the A/D converter 108 is processed by a CPU (not shown). Read and output data is A/
The voltage control circuit 110 adjusts the voltage so that the level is almost close to the maximum value FF□ of the dynamic range of the D converter 108.
This is done by setting data from the CPU.

The R signal, which is regulated by the variable amplifier 106 to the maximum value of the dynamic range of the white level A/D converter 108, is controlled by the clamp amplifier 107 so that the output level in the dark is the lowest value of the dynamic range of the A/D converter 108. Clamped to level.

Here, the clamp level of the clamp amplifier 107 is set by the clamp amplifiers 104a and 104b.
After the level difference of VEN is removed, the output level during the dark period is read by a CPU (not shown) and fed back to the voltage control circuit 111 to adjust the control voltage V.
By raising and lowering the level of C0NT□, the lowest level of the dynamic range of the A/D converter 108, Vsoaa. It is adjusted to a level close to 2.

In this way, the R signal whose maximum value and minimum value are regulated with respect to the dynamic range of the A/D converter 108 is
The D converter 108 converts it into a digital image signal.

The R-CCD image sensor has been explained above, but
G-CCD image sensor 903. Since the operation of the BCCD image sensor 904 is essentially the same, the explanation will be omitted.

In this embodiment, an example using a dual-channel image sensor has been described, but essentially the same effects can be obtained even if a multi-channel image sensor with dual channels or more, such as a quad channel image sensor, is used. Can be done.

<Other Example 1> FIG. 5 shows another embodiment of the invention.

Comparing the embodiment shown in FIG. 1 and the embodiment shown in FIG. 5, the correction means are different. That is, in one embodiment, ODD/EV
In order to correct the difference in output level between ENs, the reference level V t e + + of the clamp amplifier 104a is fixed, and the reference level V r *I of the clamp amplifier 104b is fixed.
2 is made variable with respect to the reference level Vr*II, but in this embodiment, the reference level V of the clamp amplifier 104a
r @ I 1 is also made variable, and a voltage control circuit 112 for this purpose is newly provided.

With this configuration, in the embodiment shown in FIG.
The DC output level of the dark output section from the D image sensor is amplified by amplifiers 104a-1 and 104b-1, and clamped to a predetermined level by clamp circuits 104a-2 and 104b-2.
-2 is clamped to a fixed reference level V,,,,, = OV, and in 104b-2, the reference level V r @ l * is set by the control voltage V eON□ of the voltage control circuit 109 so as to match the output level on the ODD side. By raising and lowering the output level difference between ODD and EVEN is removed.

On the other hand, in this embodiment, the clamp circuits 104a-2, 10
4b-217) Reference L/to/l/V, 11. Vmz
b<Each is variable, and a CPU (not shown) reads the final output level of each ODD/EVEN.
The CPU controls the voltage control circuits 112 and 109 so that the control voltage V
C0NT4 + V C0NT+ sets the reference level V rel of each clamp circuit 104a-2, 104b-2.
By varying l+Vr*1m, ODD/EV
The output level difference of EN is removed.

Since this is done, the effects of this embodiment are essentially the same as those of the embodiment shown in the first figure.

<Other Example 2> FIG. 6 shows another embodiment of the embodiment.

Comparing the embodiment of FIG. 6 with the embodiment of FIG. 1, in the embodiment of FIG. 1, the reference level V of the clamp amplifier 104a is
11. is fixed, the reference level Vfalm of the clamp amplifier 104b is made variable with respect to the reference level Vr*++L, and after completely removing the difference between the ODD/EVEN (7) output levels, the multiplexer 105 converts both odd and even pixels into R-
The pixel array is synthesized to be the same as the pixel array of the CCD image sensor 902, and the variable amplifier 106. The maximum level V TOP and the minimum level V of the dynamic range of the A/D converter 108 in the clamp amplifier 107 . The amplification degree and offset level were varied so that the composite pixel signal entered within 77 degrees.

In contrast, in this embodiment, the clamp amplifier 104a,
104b sets the reference level V rsll + Vra12 to the same setting level (in the embodiment, V r @ I l =
A clamping operation is performed as V r *IM=Ov), and the multiplexer 105. Variable amplifier 106. ODD/EvEN synthesis with clamp amplifier 107, A/D converter 1
After the adjustment of the dynamic range level in step 08 is completed, a variable offset amplifier 113 is provided.

The variable offset amplifier 113 includes an amplifier 113a, a third .
V c which is the output signal of the fourth voltage control circuit 115° 116 and the voltage control circuits 115 and 116
It consists of a second multiplexer 115 that switches and combines oHts + V costa according to the ODD/EVEN pixel arrangement, and the voltage control circuit 1
The configurations of circuits 15 and 116 are the same as that of the voltage control circuit 109 shown in FIG. 3 described above.

Now, the output level difference between ODD/EVEN is determined by converting the output data of ODD/EVEN after A/D conversion to CP (not shown).
Read with U, set data in each voltage control circuit 115, 116 so that there is no difference in ODD/EVEN output data, and set each output V costs + V con
ta to the timing shown in Figure 2 (10) (multiplexer 1
05 ODD/EVEN selection signal) to switch, O
Create the combined control voltage vcOIl of DD/EVEN,
ODD/EVEN offset level of amplifier 113a
Perform correction separately.

Since this is done, the effects of this embodiment are essentially the same as those of the embodiment shown in FIG.

〔Effect of the invention〕

As explained above, according to the present invention, with the above configuration, it is possible to eliminate the output level difference that occurs between the output signals of the charge transfer channels, and to improve the dynamic range of the A/D converter, especially the minimum reference level. (V, .770111)
This has the effect of making it possible to suitably match the output signal.

[Brief explanation of the drawing]

1 is a block diagram showing a document reading device according to an embodiment of the present invention, FIG. 2 is a timing chart showing an example of the timing of each part in FIG. 1, and FIG. 3 is a block diagram showing an example of the timing of each part in FIG. The block diagram shown in Fig. 4 is the voltage control circuit 110 and 111 of Fig. 1.
FIG. 5 is a block diagram showing a document reading device according to an embodiment of the present invention; FIG. 6 is a block diagram showing a document reading device according to still another embodiment of the present invention; FIGS. 8 is a block diagram showing a conventional document reading device, and FIG. 9 is a block diagram showing an example of the image sensor shown in FIGS. 7 and 8. 901 is a color image sensor, and 104a. b is a clamp amplifier, 109, 110 and 111 are voltage control circuits, and 108 is an A/D converter.

Claims (1)

[Claims] A multi-channel image sensor having a plurality of charge transfer channels, a separate output section for each charge transfer channel, a first correction means for correcting one of the output signal levels of each charge transfer channel to a reference level, and the other a second correction means that can vary the signal level of the pixel signal with respect to the reference level; a synthesis means that synthesizes both the pixel signals in the same order as the arrangement of the light receiving sections of the image sensor; and amplification of the pixel signal synthesized by the synthesis means. What is claimed is: 1. A document reading device comprising: variable amplification means for correcting an output signal of the variable amplification means; and third correction means for correcting an output signal of the variable amplification means to an arbitrary level.