JPH02226868A - Color decomposition picture correction device - Google Patents

Abstract

PURPOSE:To form a color correction data number as the power of 2 and to efficiently utilize the capacity of a data storage means by dividing equally an input signal at the interval of 'M' from 0 sequentially in total 2L when the input signal is in N-bit and has 2<n> of gradation number and storing the color correction data of the divided points to a color reproduction ROM. CONSTITUTION:A color correction data outputted sequentially from a color reproduction ROM 63R is supplied to a multiplication accumulation device 64R, into which a weight coefficient is supplied sequentially and in which the multiplication accumulation is processed. When an inputted n-color decomposition picture data (n is an integer number of >=2) has N-bit each, the interval of a basic grid is selected to be M quantization level, then the relation of (2N-1)/M+1=2L is satisfied, where 2L is N and N, M, L are integer numbers. Thus, the number of color correction data is expressed as the power of 2 and the capacity of the color reproduction ROM 63R is efficiently utilized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a color separation image correction device suitable for application to color correction devices such as video printers and digital color copiers.

[Background of the Invention] When making a hard copy of a television image using a video printer, digital color copying device, etc., each color system is different, so a color separation image correction device is used to match the reproduced colors. Ru.

For example, a color masking via, which is one of the color separation III image correction devices, is a well-known device for reproducing correct colors by canceling sub-absorption of color materials such as toner in.

For example, from the color masking device 10 shown in FIG. 8, new color correction data (image data after color correction, in this example, yellow Y , magenta M, cyan C image data) are output.

Here, color correction data is obtained by numerically calculating the input image data, but the hue of colors other than the key color,
If nonlinear processing is performed to reduce deviations in saturation, brightness, etc., the hardware becomes extremely complex.

Therefore, the arithmetic processing results of this nonlinear processing are stored in a look-up table (LUT) in advance, and this L/
It is conceivable to refer to the UT to obtain color correction data. However, in order to store all the color correction data, the capacity of the LUT becomes enormous. For example, λ, R, G,
When each image data of H is 8-bit data, the combination of each image data is 211 ・28 ・2
m=22m, and to obtain three color correction data, 22LX3=60. A huge memory capacity of 3 MB is required.

Therefore, in order to reduce the memory capacity, the applicant has
The color space formed by the input image data is divided into a plurality of basic grids, the LUT stores color correction data for the combination of input image data located at the vertices, and the color correction data corresponding to the input image data is stored in the LUT. When the input image data (interpolation point) does not exist, it is proposed to obtain color correction data by weighted averaging of the color correction data of the vertices of the basic grid that includes this input image data (interpolation point).

For example, in a three-dimensional interpolation process, if an interpolation point P exists within a basic lattice consisting of vertices A to H, as shown in FIG. The volume of the rectangular parallelepiped created by the position vertex and the interpolation point P is the vertex A
-Used as a weighting factor for the H color correction data.

That is, the vertices A~ of the basic lattice that include this interpolation point P
The color correction data of H is converted into Yi, Mi, Ci (E=
1 to 8), and the weighting coefficient for the color correction data of the vertices A to H is At (i=1 to 8), then the color correction data Yp, Mp, and Cp of the interpolation point P are calculated by the following equations.

Cp = (1/Sell Ai) ±A1C1 +111 Mp (1/ 2. A i )9A i M 1Yp
=(1/nail Ai), also AiYi meeting... (1) Also, FIG. 110 shows an example of two-dimensional interpolation processing.

A in the same figure is a color system formed by Y, M, etc., and B in the same figure is another color system formed by X, Y, etc. corresponding thereto.

Assuming that the region S composed of vertices A-D corresponds to the region S' formed by A' to D', when an interpolation point P exists in the region S, the corresponding interpolation point P
' can also be assumed to exist in the corresponding region S'.

In this case, same 1! The area ad divided by the interpolation point P is calculated as IA, and the interpolation point P' is calculated by the following equation.

P' = aA' + bB' + cC' + dD'・・
・(2) By the way, in the three-dimensional interpolation process, the color correction data Yp, M of the interpolation point P is
When calculating p and Cp, eight times of multiplication and accumulation processing are required for each, which increases the interpolation processing time.

It is a two-dimensional interpolation process, and the interpolation ra as shown in equation (2)
Even when calculating the interpolation point P' with n calculation processing, four times of multiplication and accumulation processing are required.

Therefore, in order to further shorten the interpolation processing time, the applicant has carried out interpolation processing using a divided space with a minimum number of vertices, such as a triangle in two dimensions and a pentagonal pyramid in three dimensions. I proposed to do it.

Figure 111 is an example of two-dimensional interpolation processing. In the same figure, A is Y
It is a color system formed by , M, etc., and is shown in Figure B.
is another color system formed by X, Y, etc. corresponding to this.

If the region S composed of vertices A-D corresponds to the region S' formed by A' to D', then the region S
When an interpolation point P exists in , it can be assumed that the corresponding interpolation point P' also exists in the corresponding black area S'.

In this case, it is determined which of the vertices of the interpolation point P is included in the triangle, and the area of the area divided by the vertices of the triangle and the interpolation point P is calculated, and then the interpolation point P' is calculated.

For example, as shown in the figure, interpolation point P is vertices B and C.

When included in the triangle formed by D, the areas α, β, and r of the area divided by the vertices B, C, and D and the interpolation point P are calculated.

Then, the interpolation point P' is calculated by the following equation.

P' = aB' + βC' + γD' fist eφ (3) In this way, in the case of two dimensions, the interpolation point P' can be calculated by three multiplication accumulation processes.

FIG. 12 is an example of three-dimensional interpolation processing.

A total of six pentagonal pyramids are formed by one-dot chain lines for the basic lattice composed of vertices A-H. Since the interpolation point P exists within this basic lattice, it is determined in which pentagonal pyramid it is included.

For example, if the coordinates of vertices A to H are as shown in the figure, the interpolation point P
When the coordinates of are P (5, 1, 2), this interpolation point P is the vertices A, B, C, as shown in FIG.
It can be seen that it is included in the pentagonal pyramid T formed by G.

Figure B shows a color system related to this pentagonal pyramid T.

If A' to G' correspond to A to G, respectively,
The interpolation point P' also exists within this triangle tlT'.

Once this pentagonal pyramid T is determined, the interpolation point P and the vertices A, B, C, and G are connected to form a total of four new pentagonal pyramids, as shown in A in the same figure. Each volume V
BCGP, V ACGP, V ABCP,
V ABCP is required. These volumes V 8CG
P, V ACGP, V ABGP.

V ABCP and the vertices A' and B of the color system B (7) in the same figure
', C'G', the interpolation point P' is calculated by the following equation. Note that V ABCG is the volume of the pentagonal pyramid T.

P' = 1/VABCG (VBCGP-A'+VAC
GP-B'+VABGP-C'+VABCP-G'
) If the coordinates of the interpolation point P differ, the pentagonal pyramid T used will also differ. The coordinates of the interpolation point P are P(3°1.6)
When this is the case, this interpolation point P is included in the pentagonal pyramid T formed by the vertices A, C, D, and G as shown in FIG. 14, so this pentagonal pyramid T is used.

In this way, in the case of three dimensions, the interpolation point P' can be calculated by performing multiplication and accumulation processing four times.

FIG. 15 shows an example of a color masking device 10 in which such interpolation processing is performed.

For example, 8-bit input signals R, G, and B supplied to terminals 11R, IIG, and IIB are respectively input to the latch circuit 1.
It is supplied to 2R, 12G, and 12B and is punched (Fig. 16A, D).

In this case, the reference clock CLK supplied to the terminal 14
(B in the figure) is supplied to the four-way counter 16. The 2-bit count output of this 4-way counter 15 (C in the same figure) is
The latch circuits 12R and 12G are separated into an upper bit and a lower bit, and the signal of the upper bit is used as a first latch pulse (E in the figure).

12B.

The latch outputs from the latch circuits 12R, 12G, and 12B are separated into upper 5 bits and lower 3 bits in order to specify the pentagonal pyramid used in the interpolation process. In this case, the upper 5 bits represent the reference lattice point of the vertex of the basic lattice that includes the interpolation point P determined by the input signals R, G, and B (vertex A in Fig. 12), and the lower 3 bits represent the interpolation point P. It represents the position of point P within the basic grid. In this example, the basic lattice is divided into eight equal parts in each direction, and the number of interpolation points at the vertex of the basic lattice is seven.

The lower 3 bits of the signal are the RO which functions as a means.
It is supplied to M17. This ROM 17 contains the 2-bit count output from the 4-way counter 16 (181st! IE,
F) is also supplied. In this ROM 17, it is determined which of the six pentagonal pyramids formed by the vertices of the basic lattice the interpolation point P is included in based on the signal of the lower 3 bits, and from this ROM 17, the information of the pentagonal pyramid is determined. Signals are sequentially output for identifying the vertices forming the .

For example, when the coordinates of the interpolation point P are P (15, 1, 2), the coordinates of the vertices A-H of the basic lattice including this interpolation point P are determined as shown in FIG.

Next, it is determined which of the six pentagonal pyramids formed by vertices A to H of this basic lattice includes the interpolation point P, and the pentagonal pyramid T in FIG. 13A is specified. This pentagonal pyramid T is formed by vertices A, B, C, and G.

A (0,0,0) B (8,0,0) C (8,0,8) G (8,8,8) In this case, with the vertex A as the reference, IJ, the basic lattice r in the X direction
Vertex B can be identified by moving by l'll (signal with bit "1", which corresponds to 8 quantization levels), and with respect to vertex A, basic movement in the X and Z directions, respectively. Vertex C is specified by moving by a grid interval, and roughly speaking, vertex G is specified by moving by a basic grid interval in each of the X, Y, and Z directions with vertex A as a reference.

Therefore, the triangle formed by vertices A, B, C, and G! In order to identify IT, the following signals are sequentially output from the output terminals a, b, and c of the ROM 17 based on the 2-bit count output of the four-way counter 15.

(0,0,0) (1,0,0) (1,0,1) (1,1,1) This digging signal is sent to adders 18R, 18G, 18B
and is added to the upper 5 bits of the signal to form the vertex A,
B, C, and G are calculated, and the pentagonal pyramid T is specified.

In other words, the signal for the first digging is (0, O, O'), so even if this is added to the reference grid point (0, 0, 0>), the position does not move and vertex A is specified. .

The signal for the next digging portion is (1, 0, 0), so adding this to the reference grid point (0, 0, O) yields (1, 0, 0)
((8°0.0) at the quantization level), and vertex B is specified. The signal for the next portion is (1°0, 1), so adding this to the reference grid point (0, 0, O) gives (1, 0, 1) (at the quantization level (8, 0 ,8
)), and the vertex C is specified. Furthermore, since the next jump is the signal wave 1°l, 1), this is set as the reference grid point CO,O.

0), it becomes (1, 1, 1) ((8, 8, 8) at the quantization level), and the vertex G is specified.

Further, for example, when the coordinates of the interpolation point P are P (3, 1° 5), the pentagonal pyramid T that includes the interpolation point P becomes as shown in FIG. Therefore, vertex A.

In order to specify the pentagonal pyramid T formed by C, D, and G, the following distribution signals are sent from the output terminals a, b, and c of the ROM 17 to the 2-bit count of the 4-way counter 15. Output is performed sequentially based on the output.

(0,0,0) (1,0,1) (0,0,1) (1,1,1) And for this shot, the signal is added) EW18R, 18G,
18B and added to the upper 5 bit signals to calculate vertices A, C, D, and G, thereby specifying the triangular pyramid T.

Further, signals for specifying the vertices of the pentagonal pyramid T outputted from the adders 18R, 18G, and 18B (see FIG. 16H) are sent to latch circuits 19R and 19G, respectively.

19B and is latched (in the figure, the reference clock CLK supplied to the terminal 14 is supplied to these latch circuits 19R, 19G, and 19B as a latch pulse.

The latch outputs from these latch circuits 19R, 19G, and 19B are supplied to color correction data forming means 20Y, 120M, and 20C for yellow Y, magenta M, and cyan C, and color correction data Y, M, and C are formed respectively. .

The color correction data forming means 20Y is configured as follows.

That is, the latch outputs from the latch circuits 19R, i9G, and 19B are supplied to the color depth 1jlROM 21Y, and the coordinates of the corresponding vertex of the new triangular pyramid T' obtained when the triangular pyramid T is mapped onto a different color system are calculated. is referenced. That is, the color correction data of yellow Y corresponding to the vertices of the basic lattice is stored in this color reproduction ROM 21Y, and this data is referenced by the latch output from the latch circuits 19R119G and 19B.

The color correction data (Figure 116J) sequentially outputted from this Amoman iJIROM21Y is supplied to the multiplication accumulator 22Y, and this multiplication accumulation @22Y has a weighting coefficient ROM3.
Weighting coefficients are sequentially supplied from 0 through the latch circuit 31 to perform multiplication and accumulation processing. This multiplication accumulation ``W22Y
A reference clock CLK is supplied to the terminal 14.

In this case, the lower three bits of the latch output signals from the false circuits 12R, 12G, and 12B are stored in the weighting coefficient ROM 30.
At the same time, the weighting coefficient ROM 30 is also supplied with a 2-bit count output from the four-way counter 15, and the volume of the new triangular pyramid formed by the apex forming the triangle #aT and the interpolation point P is The required weighting coefficients are sequentially referenced.

For example, in the case of the triangular pyramid T in FIG. 13A, the following weighting coefficients are referred to.

V BCGP, V ACGP, V AflGP
, V ABCP After the weighting coefficient output from the weighting coefficient ROM 30 is latched by the latch circuit 31, it is supplied to the multiplication accumulator 22Y, and the calculation process as shown in the following equation is executed. The reference clock CLK supplied to the terminal 14 is supplied to the latch circuit 31 as a latch pulse.

P'(Y)=1/VABCG(VBCGP-A'+
VACGP-B'+VA8GP-C' +VABCP-
c') Figure 16 shows data during arithmetic processing.

Here, M indicates multiplication processing, A indicates accumulation processing, and R indicates rounding processing.

The multiplication accumulator 22Y outputs the result of each multiplication (N in FIG. 16), and this output is supplied to the latch circuit 23Y and latched. Then, the final calculation result is outputted from this latch circuit 23Y as interpolated data Y (P
).

Second, in order to perform the above-described arithmetic processing at a predetermined timing, a control circuit 40 composed of a logic circuit is provided. The 2-bit count output (E and F in the figure) from the quaternary counter 15 is supplied to a NAND circuit 41, and the output of this NAND circuit 41 (G in the figure) is supplied to a latch circuit 43 and latched.

The output from the latch circuit 43 (L in the figure) is supplied to the multiplication accumulator 22Y as an accumulation pulse.

Further, the latch output from this latch circuit 43 is supplied to a latch circuit 44, and the latch output from this latch circuit 44 is supplied to the latch circuit 2 as a second latch pulse (O in the figure).
Supplied to 3Y. The latch circuit 43°44 has terminal 14
The reference clock CLK supplied to is supplied as a latch pulse.

Further, the phase of the output of the NAND circuit 41 is inverted by an inverter 42, and the output of this inverter 42 (M in the figure) is supplied as a rounding pulse to the multiplication accumulation IJ 122Y.

By the way, as a handsome man fJIROM21Y, for example, 2
A bit capacity ROM is used in 56, and the input signals R, G
, only 32 points between the minimum level and the maximum level of B are extracted, thereby 32X32X32=32
Color correction data of 768 points is stored.

In this case, the input signals R, G, and B are 8 bits,
It has a 256PM tone, and the distribution of 32 points is, for example, as shown below, starting from 0 and dividing it into "8" increments, 0, 8. 1B, ・φ..., 240.248, which is divided into equal parts for a total of 32 points, and the 33rd point above 249 and up to 256 are not used, or 24
treated as 8.

The color correction data of each of these distribution points, that is, the vertices of the basic lattice whose basic lattice spacing is 6 quantization levels, is accurately calculated, and this calculated correction data is stored in the color reproduction ROM 2.
Stored in 1Y.

Also, when the basic lattice spacing is 8 quantization levels, 4@
The total swelling coefficient is 8X8X8/6=512/6, which is normalized to 256. Then, as the weighting coefficient ROM 30, an 8-bit general-purpose IC is used.
The sum of the four weighting coefficients is always 266 so that
For example, if the interpolation point P is at the same position as the vertex A in FIG. 12, the weighting coefficients V BCGP, V ACG
P, V ABGP, V A3CPu Next (7)
The values in parentheses are theoretical values.

V BCGP, V ACGP, V ABGP,
V A8CP26δ OO1 (512/6 0 0 0) In this way, the sum of the four weighting coefficients is always 256, so even if it is not mentioned above,
Multiplication accumulation I! ! The division process of 1/V ABCG in 22Y is performed by shifting the output by 8 bits. In this case, the rounding process is, for example, 8 from the bottom.
Determine whether the bit is “rl” or “0”,
When it is "1", "l" is added to the 9th bit.

Although the explanation is omitted, the color correction data forming means 20M
, 20C are configured similarly to the color correction data forming means 20Y described above, and output interpolated data M and C.

[The invention attempts to solve i! I! I] By the way, the first
In the example in Fig. 5, the input signal R of 8 bits and 266 gradations is
32 between the minimum and maximum levels of G and B
Only a point is extracted, and the color correction data of that point is a color image pAR.
It is stored in OM21Y, and the distribution of 32 points is as follows.
Starting from O, divide by r8'', 0, 8. 16. - and Φ・, 240.248 total 3
It is divided equally into two pieces, and the 33rd point is 24.
Numbers from 9 to 255 are not used or are treated as 248.

In this case, since 32 is expressed as a power of 2, the number of color correction data is also a power of 2, and the color image Ijl R0M21Y
(memory generally has a capacity of power of 2 bytes), but the input signals R, G, B
Of these, the portions 249 to 255 have the disadvantage that they are not interpolated or are not correctly interpolated even if they are interpolated.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a color separation image correction apparatus that allows efficient use of memory capacity and correctly performs interpolation processing on input signals.

[i! Means for Solving the Problem] This invention divides a color space formed by n color separation image data (n is an integer of 2 or more) that can be input for color correction into a plurality of basic grids, and data storage means having color correction data for the n-color separation image data located therein; and weights for generating weighting coefficients for each of the color correction data selected from the data storage means based on the input n-color separation image data. coefficient generating means; and color separations modified by multiplication and accumulation processing of color correction data selected from the data storage means based on the input n color separation image data and weighting coefficients generated by the weighting coefficient generating means. When the input n color separation image data is each N bits, the basic lattice spacing is M quantization 1 noher, and 2L=N, (2 squares - 1 )/M+1=2L (where N, M, and L are !1 numbers).

[Function] In the above configuration, when the input signal has N hits and 2N gradations, it is divided into rM'' units starting from O, and the total of 2 is 0, M, 2M, ・yu・, 2M−1.
For example, if the input signal is 8 bits and has a 28=256 PJ tone, it is divided into 17 pieces starting from 0, 0.1?, 34. --9255 will be equally distributed for a total of 16 pieces.And,
Color correction data for this distribution point is stored in the data storage means.

Therefore, the number of color correction data becomes a power of 2, and the capacity of the data storage means can be used efficiently. Furthermore, all the gradations of the input signal are equally distributed, and there are no unused portions of the input signal or portions that are treated as other values and processed.

[Example] Hereinafter, an example of the present invention will be described with reference to FIG. 11.

In this example, the input signals are yellow Y, magenta M, cyan C,
This is an example of a color masking device in which the output signals are Red R, Green G, and Blue B.

In the figure, terminals 51Y, 51M, and 51C.

8-bit input signals Y, M are supplied to the 51K.

C and K are latch circuits δ2Y and 52M, respectively.

It is supplied to 52C and 152K and latched.

In this case, the reference clock CLK supplied to the terminal 63
is supplied to the six-way counter 54. This quinary counter 6
The signal of the upper 1 bit of 4 is supplied to latch circuits 52Y to 52K as a latch pulse.

The output of each of these latch circuits 52Y to 52 is 1
ROM5 for digging into storage data and lower-level data
Supplied to 5Y to 55K. These R0M55 Y~5
From 5K, when the outputs to the latch circuits 52Y to 52 are divided by 17, the quotient is output as 4 bits, and the remainder is output as 6 bits.

That is, in this example, one input word Y, M, C
.

Each K is 8 bits and has 211=256 gradations, and is divided into "17" units starting from O, and the distribution point (
The vertices of the basic lattice) are 0, 1? , 34.・Bones・, 2155, for a total of 16 pieces. As a result, the interval in each direction of the basic lattice (hypercube) becomes 17 quantization levels, and the number of interpolation points between vertices in each direction becomes 16.

In this case, the 4-bit output, which is the quotient, is the input signal Y,
A basic grid (
The 5-bit output representing the remainder represents the position of the interpolation point P within the basic lattice.

The 6-bit single words YL, ML, CL, and KL outputted by these R0M55Y~55 are sent to the data output device 5.
6. A 3-bit count output from a 6-way counter 64 is also supplied to this data output device 5G.

Incidentally, the color density y4ROM, which will be described later, stores only color correction data for the vertices of the basic grid and performs interpolation processing, but in this example there are four inputs, resulting in four-dimensional interpolation processing. In this case, in order to shorten the interpolation processing time, the interpolation processing is performed using the construction pyramid having the minimum number of vertices.

Here, a total of 24 m of erected pyramids are formed for the basic lattice (hypercube). This basic lattice has the coordinates (X, Y) of 16 vertices as shown in FIG.

Z, A), the coordinates (X, Y, Z, A) of the vertices of the 24 erected pyramids are the third
The result will be as shown in the figure.

Then, the coordinates of the interpolation point P (x, y, Z+ a
), the five weighting coefficients for each erecting pyramid are as shown in FIG. This weighting factor is the volume of the five laying pyramids formed by connecting the interpolation point P and the apex of each laying pyramid when the hypervolume of each laying pyramid is normalized to 1.

It can be determined in which of the 24 construction pyramids the interpolation point P is included by checking where the weighting coefficients are all positive.

The data output device 56 outputs signals YL, Ml, .
Based on CL and KL, it is determined in which of the 24 construction pyramids formed by the vertices of the basic lattice the interpolation point P is included. The data output device 56 sequentially outputs signals for digging to specify the vertices forming the construction pyramid.

41st! I indicates a specific configuration example of the data output device 56.

In the same figure, ROM55Y, 55M, and 55C.

65 (signals YL, ML, CL, and L are selectively supplied to comparators 571 to 576).

The comparator 571 determines whether YL-ML≧O is satisfied, the comparator 672 determines whether YL-CL≧O1i: is satisfied, the comparator 573 determines whether YL-KL≧0 is satisfied, and the comparator 674 determines whether ML-CL≧0. The comparator 676 determines whether ML−KL≧O is satisfied, and the comparator 576 determines whether CL−KL 0
It is determined whether the above conditions are satisfied, and when the conditions are satisfied, a high level "1" signal is output, and when the conditions are not satisfied, a low level "0" signal is output.

The outputs of these comparators 1571 to 576 are supplied to the ROM 58 for determining the diagonal pyramid in which the interpolation point P is included. As mentioned above, to determine which of the 24 construction pyramids the interpolation point P is included in, it is sufficient to check where the weighting coefficients are all positive, and using this, determination data is stored in the ROM 58 in advance. . W4 For example, when the interpolation point P is included in the laying pyramid of positive 4 in FIG.
In this case, it is determined that the interpolation point P is included in the construction pyramid of Na4.

The determination result output from the ROM 58 is supplied to a ROM 159 for outputting a signal. The 3-bit count output from the 5-way counter 54 is also supplied to this ROM 59. Then, the ROM 59 sequentially outputs signals for identifying the five vertices forming the construction pyramid determined by the ROM 58 in accordance with the count output.

For example, when the interpolation point p is included in the laying pyramid of floor 4 in FIG. 3, the output terminal of the ROM 59 outputs a signal (y) as shown in FIG.

nL C,k) are sequentially output based on the count output.

The distributed signals (y, m, c, lc) are supplied to adders 60Y, 60M, 80C, 80K,
It is sequentially added to the 4-bit signals YH, MH, CH, and KH output from the ROMs 55Y, 56M, and 55C055K, thereby specifying the five vertices of the laying pyramid that include the interpolation point P.

In addition, the signals outputted by adders 1160Y, 60M, 60C, and 80 for specifying the 5gi apex of the erecting pyramid are U-Sochi circuit 61Y, respectively. 61M, 61C061■(
are sequentially supplied and latched. These latch circuits 61
The reference clock CLK supplied to the terminal 53 is supplied to Y, IBM, 61C, and 61K as a latch pulse.

The latch outputs from these latch circuits 81Y, 81M, 61C, and 61K are supplied to color correction data forming means 82R, 82G, and 62B for R, G, and B, and color correction data R, G, and B are formed respectively. Ru.

The color correction data forming means 62R is configured as follows.

Sunawachi, latch l1ga61Y, 61M, 610°6
The latch output from 1K is dark fjl ROM 83 R
is supplied to This dark Tj! R0M63 R stores the color correction data of R corresponding to the vertices of the basic grid, and this
Referenced by the latch output from 1K.

The color correction data sequentially outputted from the color reproduction ROM 83R is supplied to the multiplication accumulator 6'4R, and the I coefficient is sequentially supplied to the multiplication accumulator 84R to perform the multiplication accumulator I.

That is, in this multiplier/accumulator 84R, when the color correction data sequentially supplied are R1 to R5 and the weighting coefficients are V1 to 5, the following calculation is performed.

RI Vl +R2V2 +R3V3 +R4V4 +R5V5 A control signal necessary for multiplication processing, accumulation processing, etc. is supplied from the controller 7° to this multiplier accumulator 64H. The controller 7o is supplied with a 3-bit count (words) from a five-way counter 64 and a reference clock CLK from a terminal 53.

The output from the accumulator 64R is converted to 17 by the divider 65R.
17 and then supplied to the latch circuit 66R. The final calculation result is output as interpolated data R from this latch circuit 66R.

The divider 65R divides it into 1/17 by using 5 as described below.
This is because the sum of the weighting coefficients Vl to 5 is 17. Note that a latch pulse is supplied to the latch circuit 66H from the controller 70 every time a multiplication and accumulation process is performed.

Furthermore, the weighting coefficients are supplied to the multiplication accumulation 1164R as follows.

That is, 6-bit 1N numbers YL and ML output from the ROMs 55Y, 55M, 55C, and 55.

C1, . . . KL are supplied to the selector 71 and upstream 72. These selectors 71 and 72 are supplied with 2-bit select signals S1 and S2, respectively, corresponding to the string ball pyramid in which the interpolation point P is included, from the data output device δ6.

In other words, as shown in FIG. 4, the determination result output from the ROM 5B is supplied to the ROM 73 for outputting select number 18, and from this ROM 73, a 2-bit select signal corresponding to the string ball pyramid containing the interpolation point P is output. Signals S1 and S2
are sequentially output in response to the count output.

For example, when the interpolation point P is included in the string ball pyramid of Na4 in FIG.
1 and 72, the 51st! The signal shown in I is controlled to be selected.

Here, x, y, z, and a in FIG. 3 correspond to YL, ML, CL, and Kl, respectively, and "1" in the same figure corresponds to "17". In other words, in this example, the sum of the six weighting coefficients is 1
7. Howl.

In addition, the output A L of the selector 71 and the selector 2
The output BL is supplied to a weighting coefficient calculator 74. The weighting factor calculator 74 is also supplied with a 3-bit count output from the quinary counter 54.

The creep coefficient calculator 74 outputs the following calculation results as weighting coefficients in response to the count output.

That is, when the count output is "000", 17-
A, L, rool" - AL- when rQ11J
BL, r 100J throat 1 Niha AL force is output.

For example, when the interpolation point P is included in the string ball pyramid of Na4 in FIG. 3, the weighting factor calculator 74 outputs a weighting factor in response to the count output as shown in FIG.

The weighting coefficient output from the weighting coefficient calculator 74 is latched by the latch circuit 76, and then supplied to the multiplication accumulator 64R, where the multiplication and accumulation processing is performed as described above. The reference clock CLK from the terminal 53 is supplied to the latch circuit 75 as a latch pulse.

Although the explanation is omitted, the color correction data forming means 62G
, 62B are similarly configured and output interpolated data G and B.

In this way, in this example, the input number 1g is 8 bits and 2
M = 256111 keys, divided into 17 notes in order from 0'b), 0, 1?, 34. --, 255, totaling 16
The color correction data of this distribution point is stored in the color depth Kit ROM. Therefore,
The number of color correction data is a power of 2, and the color depth fj! R.O.
The capacity of M can be used efficiently.

Also, all gradations of the input signal are distributed equally.

Since unused portions of the input signal or portions that are treated as unused values are not generated, it is possible to always obtain correct interpolated data.

Furthermore, since the data output device 56 is configured using comparators 571 to 67.6 as shown in FIG.
OM can be saved. In other words, the entire RO
For the 11th case consisting of M, (2L X2L X2L
X2L

In the above-mentioned embodiment, three color correction data forming means 62R to 62B are provided so that the interpolation processing of RlG and B is processed in parallel.
The color correction data forming means is 111il, and the color reproduction ROM
R, G, and B color correction data are stored in the ROM, and the color correction data output from this color reproduction ROM is converted into R, G, and B color correction data.
Alternatively, the interpolation processing for R, G, and B may be sequentially performed by switching to B sequentially.

Furthermore, in the above embodiment, the input signals Y, M.

Although C and K are 8 bits and the basic lattice spacing is 17 quantization levels, generally when the input signal is N bits, by setting the basic lattice spacing to M quantization levels that satisfy the following formula. , it is possible to obtain the same effects as those of the above-mentioned embodiments. Here, 2L=N, and N, M,
L is an integer.

(2-1)/M+1=2L Figure 7 shows the relationship between N, M, and L at this time.

Further, although the above-mentioned embodiment is a case of 4 inputs, the present invention can be similarly applied to a case of 3 inputs or the like.

[Effect of the invention 1] As explained above, according to the present invention, the input signal is N
When the bit has two gradations, it is divided into 1"MJ units starting from O and equally distributed so that the total number is 2L, and the color correction data of this distribution point is stored in the data storage means. Therefore, according to the present invention, the number of color correction data becomes a power of 2, and the capacity of the data storage means can be used efficiently.Furthermore, all the gradations of the input signal are divided into equal parts. Since there are no unused portions of the input signal or portions that are treated as wasteful and processed, interpolation processing can always be performed correctly.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing an embodiment of the present invention, FIGS. 2 to 7 are diagrams for explaining the same, and FIGS. 8 to 16 are diagrams for explaining the invention in detail. . 52Y~521 (,61Y~61, 66R,7
5. O-latch circuit 54 dispute ◆ 6-way counter 55Y-55 - Data storage is in ROM 56.
・Data output device BOY ~60! (62R~628 3R 4R 5R 71,72 - Adder f!!, correction data forming means - Color reproduction ROM - Multiplication accumulator - Divider - Controller selector - Weighting coefficient calculator Explanatory diagram of data output device No. 5 Figure 6 Explanatory diagram of weighting coefficient calculator

Claims (1)

[Claims] (1) n color separation image data that can be input for color correction (
n is an integer of 2 or more) into a plurality of basic lattices, and data storage means has color correction data for the n color separation image data located at the vertices of the basic grid, and the input n color separations weighting coefficient generating means for generating weighting coefficients for each of the color correction data selected from the data storage means based on the image data; and processing means for outputting color-separated image data corrected by multiplication and accumulation processing of weighting coefficients generated by the weighting coefficient generation means, wherein the input n-color separation image data is A color separation image correction device characterized in that the following equation is satisfied when each bit is N bits, the basic grid spacing is M quantization levels, and 2L=N. (2^M-1)/M+1=2^L (N, M, and L are integers)