JPH022118A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the film quality of a wiring from deteriorating and enable contact resistance between the wiring and a substrate diffusion layer to be reduced by setting a low-resistance anneal treating temperature of a high melting-point metal silicide layer to a temperature which is lower than an activation anneal treating temperature of a polysilicon film. CONSTITUTION:A separation insulation film 2, a substrate diffusion layer 4, and a interlayer insulation film 5 are obtained on a substrate 1 by the conventional method to allow a polysilicon film 7 to be formed. Then, an insulation film 21 is formed on a polysilicon film 7 by the thermal oxidation method and then a P<+> ion impregnation and an activation anneal treatment for example at 950 deg.C are performed to allow polysilicon film 7 to be doped. Then, after eliminating an insulation film 21 by the RIE method, a TiSi2 is accumulated on the polysilicon film 7 by the sputter method to allow a high melting-point metal silicide layer 8 to be formed and the both ate selectively subject to etching by the RIE method to allow a wiring 10 to be formed. Then, after accumulating SiO2 so that the wiring 10 may be covered by the CVD method and then forming an insulation film 9, an anneal treatment at for example 900 deg.C is performed to achieve a low-resistance high melting-point metal silicide layer 8 to complete a semiconductor device.

Description

[Detailed Description of the Invention] [1] Relating to a method for manufacturing a semiconductor device, it is possible to almost eliminate deterioration of the film quality of wiring, and
The purpose of the present invention is to provide a method for manufacturing a semiconductor device that can reduce the contact resistance between wiring and a substrate expansion layer. forming a contact hole on the layer; forming a polysilicon film so as to make contact with the substrate diffusion layer through the contact hole; and selectively introducing impurities into the polysilicon film; a step of performing an annealing treatment for activating the polysilicon film; a step of forming a high melting point metal layer or a high melting point metal silicide layer on the polysilicon film; and a step of forming the polysilicon film and the high melting point metal layer. Alternatively, the method is configured to include a step of selectively etching the high melting point metal silicide layer to form a wiring, and a step of performing an annealing treatment to lower the resistance of the wiring.

[Industrial application field]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device that can reduce contact resistance between wiring and a substrate diffusion layer.

In recent years, as LSIs have become more highly integrated, it has become necessary to reduce the contact resistance between wiring and diffusion layers formed by impurity implantation. As a wiring structure for achieving low resistance, there is a polycide structure wiring, which consists of a high melting point metal layer made of, for example, Ti or a high melting point metal silicide layer made of, for example, TiSi2, and a polysilicon film. Consists of layered wiring. By performing high-concentration ion implantation (for example, implanting impurities such as P or As) and activation annealing treatment into the wiring of this polycide structure, the impurity concentration of the activated polycide is increased and the contact resistance with the diffusion layer is increased. A method has been proposed to lower the

However, when this high concentration ion implantation and activation annealing treatment are performed, there is a problem in that the film quality of the high melting point metal layer or the high melting point metal silicide layer is likely to deteriorate. The reason for the deterioration of the film quality is considered to be that the crystals of the high melting point metal layer or the high melting point metal silicide layer are damaged by ion implantation and become amorphous or defects are generated. In addition, when annealing is performed, Si tends to precipitate, and this Si may increase the resistance.
There is also a problem that the polysilicon film and the high melting point metal layer (or the high melting point metal silicide layer) may peel off.

This becomes more noticeable as the size becomes smaller. The reason why Si is precipitated is considered to be that excessive Si added to relieve stress and improve oxidation resistance is precipitated by heat.

Therefore, it is required to obtain high-quality, low-resistance wiring and a junction with low contact resistance between the wiring and the diffusion layer.

[Conventional technology]

Conventionally, the manufacturing method for reducing the contact resistance between wiring and a substrate diffusion layer in a polycide structure consisting of a two-layer structure of a high-melting point metal layer or a high-melting point metal silicide layer and a polysilicon film is to form it on a polysilicon film. A method of implanting ions onto a high melting point metal layer or a high melting point metal silicide layer has been adopted.

Hereinafter, this will be explained in detail using the drawings.

FIGS. 3(a) to 3(f) are diagrams for explaining an example of a conventional method for manufacturing a semiconductor device.

In these figures, l is a substrate made of, for example, St and whose thermoelectric type is p type, 2 is an element isolation insulating film made of, for example, 5iQ2, 3 is an insulating film made of, for example, Sin, 4 is a substrate diffusion layer, and 5 is a substrate. For example, an interlayer insulating film made of SiO□, 6 a contact hole, 7 a polysilicon film, 8 a T
i S i ', a high melting point metal silicide layer (
For example, it may be a high melting point metal such as Ti), 9
is an insulating film made of, for example, 5iOz (PSG may also be used),
Reference numeral 10 denotes a wiring, which is composed of a polysilicon film 7 and a high melting point metal silicide layer 8.

Next, the manufacturing process will be explained.

First, as shown in FIG. 3(a), an insulating film 3 having a thickness of, for example, 200 mm is formed on the substrate l by, for example, a thermal oxidation method, and then a film thickness of, for example, 60 mm is formed on the substrate l by field oxidation.
00 is selectively formed.

Next, as shown in FIG. 3(b), after a substrate diffusion layer 4 is selectively formed in the base film by ion implantation with an impurity of, for example, As'') and an amount of, for example, 4E15 cm-'', For example, an annealing treatment for activation is performed at 900 to 1000°C.

Next, as shown in FIG. 3(c), after selectively etching the insulating film 3 by, for example, RIE, etching is performed by, for example, CVD.
By depositing 5 in2 on the entire surface by the method, the film thickness is, for example, 200 mm.
An interlayer insulating film 5 of 0 is formed.

Next, the contact hole 6 is formed on the substrate diffusion layer 4 by selectively etching the interlayer insulating film 5 by, for example, RIE method. At this time, the substrate diffusion layer 4 is exposed.

Next, as shown in FIG. 3(d), poly-Si is deposited on the entire surface by, for example, the CVD method, and contact is made with the substrate diffusion layer 4 through the contact hole 6. After forming a polysilicon film 7 having a thickness of, for example, 1,000 thick, TiSi2 is deposited on the polysilicon film 7 by, for example, sputtering to form a high melting point metal silicide layer 8 having a thickness of, for example, 2,000.

Next, as shown in FIG. 3(e), ion implantation is performed at a dose of, for example, IE16 cm@-2, in which the impurity is, for example, P.

After selectively etching the high melting point metal silicide layer 8 and polysilicon film 7 by, for example, the RIE method to form the wiring 10, a film of Sin is deposited to cover the wiring 10 by, for example, the CVD method. For example, 1000 insulating films 9 are formed. Next, for example, 95% is applied, including activation of impurities and lowering of the resistance of the high melting point metal silicide layer 8.
By performing annealing treatment at 0° C., a semiconductor device having a structure as shown in FIG. 3(f) is completed.

[Problem to be solved by the invention]

However, in such a conventional method for manufacturing a semiconductor device, the wiring 10 is formed by performing high concentration ion implantation and activation annealing treatment on the wiring 10 having a polycide structure.
This method lowers the contact resistance between the metal silicide layer 4 and the substrate diffusion layer 4, but there is a problem in that the film quality of the wiring 10, especially the high melting point metal silicide layer 8 (for example, the same applies to high melting point metals such as Ti) is likely to deteriorate. . The reason for the deterioration of the film quality is considered to be that the crystals of the high melting point metal silicide layer 8 are damaged by the ion implantation and become amorphous or defects are generated.

In addition, when annealing treatment is performed, Si tends to precipitate, and this S
The resistance may increase due to i, or the polysilicon film 7
There was a problem that the high melting point metal silicide layer 8 and the high melting point metal silicide layer 8 could peel off. The reason why Si is precipitated is considered to be that excessive Si added to relieve stress and improve oxidation resistance is precipitated by heat.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device that can almost eliminate deterioration due to wiring modification and also reduce the contact resistance between the wiring and the substrate diffusion layer. .

[Means to solve the problem]

In order to achieve the above object, the method for manufacturing a semiconductor device according to the present invention includes the steps of selectively forming a substrate diffusion layer in a substrate, forming a contact hole on the substrate diffusion layer, and forming a substrate diffusion layer through the contact hole. a step of forming a polysilicon film so as to make contact with the substrate diffusion layer; a step of selectively introducing impurities into the polysilicon film, and then performing an annealing treatment for activating the polysilicon film; A step of forming a high melting point metal layer or a high melting point metal silicide layer on the polysilicon film, and selectively etching the polysilicon film and the high melting point metal layer or the high melting point metal silicide layer to form wiring. The method includes a step of forming the wiring, and a step of performing an annealing treatment to lower the resistance of the wiring.

[For production]

In the present invention, a substrate diffusion layer is selectively formed in a substrate, a contact pole is formed on the substrate diffusion layer, and then a polysilicon film is formed to make contact with the substrate diffusion layer through a contact hole. Ru. Next, impurities are selectively introduced into the polysilicon film, and after an annealing process is performed to activate the polysilicon film, a high melting point metal layer or a high melting point metal silicide layer is formed on the polysilicon film. . Then, after the polysilicon film and the high melting point metal layer or the high melting point metal silicide layer are selectively etched to form wiring, an annealing process is performed to lower the resistance of the wiring.

Therefore, since the annealing process can be performed at a lower temperature than the activation annealing temperature of the polysilicon film to reduce the resistance of the wiring, impurities in the polysilicon film can be re-injected into the high melting point metal layer or the high melting point metal silicide layer. This makes it difficult to distribute the contact resistance between the wiring and the substrate diffusion layer. In addition, since a high melting point metal layer or a high melting point metal silicide layer can be formed after the activation annealing treatment of the polysilicon film, deterioration of the film quality of the high melting point metal layer or high melting point metal silicide layer due to high temperatures can be prevented. be able to suppress it.

(Example〕 Hereinafter, the present invention will be explained based on the drawings.

FIGS. 1(a) to 1(g) are diagrams for explaining one embodiment of the method for manufacturing a semiconductor device according to the present invention. The illustrated semiconductor device is applied to, for example, an N-channel transistor.

In these figures, the same reference numerals as in FIGS. 3(a) to 3(f) indicate the same or corresponding parts, and 21 is an insulating film made of, for example, SiO□.

Next, the manufacturing process will be explained. In addition, Figure 1 (
Steps a) to (c) are similar to those described in FIGS. 3(a) to (c) of the conventional example.

First, as shown in FIG. 1(a), an insulating film 3 having a thickness of, for example, 200 mm is formed on a substrate 1 by, for example, a thermal oxidation method, and then a film thickness of, for example, 200 mm is formed on a substrate by field oxidation. 6000 element isolation insulating films 2 are selectively formed.

Next, as shown in FIG. 1(b), for example, if the impurity is As
After selectively forming the substrate diffusion layer 4 in the substrate 1 by ion implantation with a dose of, for example, 4E15 cm2,
For example, annealing treatment for activation is performed at 900 to 1000°C. This corresponds to the step of selectively forming a substrate diffusion layer within the substrate of the present invention.

Next, as shown in FIG. 1(c), after selectively etching the insulating film 3 by, for example, RIE, etching is performed by, for example, CVD.
By depositing 5 in2 on the entire surface by the method, the film thickness is, for example, 200 mm.
An interlayer insulating film 5 of 0 is formed.

Next, the interlayer insulating film 5 is selectively etched by, for example, RIE to form a contact hole 6 on the substrate diffusion N4. At this time, the substrate diffusion layer 4 is exposed. This corresponds to the step of forming a contact hole on the substrate diffusion layer according to the present invention.

Next, as shown in FIG. 1(d), poly-Si is deposited by, for example, the CVD method, and a film thickness of, for example, 10 mm is formed so as to make contact with the substrate diffusion layer 4 through the contact hole 6.
o polysilicon films 7 are formed. This is the present invention.
This corresponds to the process of forming a polysilicon film so as to make contact with the substrate diffusion layer through a contact hole. Next, an insulating film 21 having a thickness of, for example, 100 nm is formed on the polysilicon film 7 by, for example, a thermal oxidation method (CVD method may also be used). The insulating film 21 not only has the function of optimizing the next step of ion implantation, but also has the function of preventing impurities from diffusing into the atmosphere during the activation annealing process. be.

Next, as shown in FIG. 1(e), impurities such as Po
Polysilicon film 7 is selectively doped by performing ion implantation at a dose of, for example, 8E15 cm -2 and activation annealing at, for example, 950°C. After selectively introducing impurities into the polysilicon film of the present invention,
This corresponds to the process of performing annealing treatment to activate the polysilicon film.

Next, as shown in FIG. 1 (), after selectively removing the insulating film 21 by, for example, RIE, TiSi2 is deposited on the polysilicon film 7 by, for example, sputtering to a film thickness of 2000 nm. A high melting point metal silicide layer 8 is formed. This corresponds to the step of forming a high melting point metal layer or a high melting point metal silicide layer on a polysilicon film according to the present invention. Next, the high melting point metal silicide layer 8 is formed by, for example, RIE method. Then, the polysilicon film 7 is selectively etched to form the wiring 10. This is the process of selectively etching the polysilicon film and the high melting point metal layer or the high melting point metal silicide layer to form the wiring according to the present invention. After forming the insulating film 9 with a thickness of, for example, 1000 by depositing 5 in 2 to cover the wiring 10 by, for example, the CVD method, in order to lower the resistance of the high melting point metal silicide layer 8. For example, by performing annealing treatment at 900°C, a semiconductor device having a structure as shown in FIG. 1(g) is completed. The resistance of the high melting point metal silicide layer 8 (which has already been sufficiently activated) may be appropriately set to be lowered in resistance.

It is preferable that the temperature is low and the time is short. This corresponds to the step of performing annealing treatment to lower the resistance of the wiring according to the present invention.

That is, in the above embodiment, the temperature (e.g., 900°C) of the resistance lowering annealing treatment for the wiring 10 (particularly the high melting point metal silicide layer 8) is lower than the temperature (e.g., 950°C) for the activation annealing treatment of the polysilicon film 7. It can be performed at a low temperature, and unlike conventional methods, it is not necessary to perform the activation annealing process for the polysilicon film 7 and the annealing process to lower the resistance of the wiring IO at the same time. In addition, the activation annealing treatment of the polysilicon film 7 can be sufficiently performed at a high temperature. therefore,
It is possible to almost eliminate deterioration in the V and quality of the wiring IO, and to reduce the contact resistance between the wiring IO and the substrate diffusion N4 (conventionally 150 Ωμm2 was reduced to 70Ωμm).
can be reduced to 2). The reason why the contact resistance can be reduced is that the resistance of the wiring 10 can be reduced by annealing at a low temperature (the shorter the time, the better), so that the impurities in the polysilicon film 7 are absorbed by the high melting point metal that constitutes the wiring IO. This is thought to be due to the fact that it becomes difficult to redistribute into the silinide layer 8. Specifically, as shown in FIG. 2, when the resistance of the polysilicon film 7 is high, the current passing through the interface A between the polysilicon film 7 and the interlayer insulating film 5 is concentrated at the contact hole 6. ), it is easier to flow uniformly not only in the contact hole 6 portion but also in the vertical direction to the interface between the high melting point metal silicide layer 8 and the polysilicon film 7a (so that the high melting point metal silicide layer 8 and the polysilicon film 7a contact resistance decreases.

Therefore, the resistance lowering annealing treatment of the high melting point metal silicide layer 8 can lower the contact resistance at a temperature lower than the activation annealing treatment temperature of the polysilicon film 7. Furthermore, deterioration of the film quality of the high melting point metal silicide layer 8 can be suppressed because the high melting point metal silicide layer 8 can be formed after the activation annealing treatment of the polysilicon film 7. This is because the influence of

In the above embodiment, a case where an N-channel transistor is applied as a semiconductor device has been described, but the present invention is not limited to this, and may be applied to a structure that employs both an N-channel and a P-channel, such as a CMOS transistor. It can also be applied to Specifically, for example, a resist pattern for ion implantation of P'' is formed on the thing shown in FIG. do. Next, an activation annealing process for the N channel is performed, for example, a resist pattern for B' ion implantation is formed, B' ions are implanted, and then the B' ion implanted resist pattern is removed. Next, as shown in FIG. 1(f), after removing the absolute uA film 21 and forming a high melting point metal silicide layer 8, the high melting point metal silicide layer 8 and the polysilicon film 7 are removed.
is selectively removed to form a wiring lO. And the first
As shown in Figure (g), after forming the insulating film 9, a CMOS transistor can be formed by performing an annealing process to lower the resistance of the high melting point metal silicide layer 8 and an annealing process to activate B'. can.

In this case, the first activation annealing is for the N channel, and the last activation annealing is for both activating the P channel and lowering the resistance of the high melting point metal silicide layer 8. be.

Both can be performed at the same time because the resistance of the polysilicon film 7 for the P channel is less dependent on the activation annealing temperature.

In each of the above embodiments, a polycide structure in which a high melting point metal silicide layer 8 is formed on a polysilicon film 7 has been described, but the present invention is not limited to this. It may be a polycide structure in which a high melting point metal layer is formed.

〔effect〕

According to the present invention, it is possible to almost eliminate deterioration of the film quality of the wiring, and it is also possible to reduce the contact resistance between the wiring and the substrate diffusion layer.

5...Interlayer insulating film, 6...Contact hole, 7...Polysilicon film, 8... High melting point metal silicide 9...Insulating film, 10...Wiring, 21...Insulating film.

De layer,

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating an embodiment of the semiconductor device manufacturing method according to the present invention, FIG. 2 is a diagram illustrating the effects of the embodiment, and FIG. 3 is an example of the conventional semiconductor device manufacturing method. FIG. 1...Substrate, 2...Element isolation insulating film, 3...Insulating film, 4...Substrate diffusion layer,

Claims (1)

[Claims] A step of selectively forming a substrate diffusion layer in a substrate, a step of forming a contact hole on the substrate diffusion layer, and a step of making contact with the substrate diffusion layer through the contact hole. forming a polysilicon film on the polysilicon film, selectively introducing impurities into the polysilicon film and then performing an annealing treatment for activating the polysilicon film, and depositing a high melting point metal on the polysilicon film. a step of forming a layer or a high melting point metal silicide layer; a step of selectively etching the polysilicon film and the high melting point metal layer or the high melting point metal silicide layer to form a wiring; 1. A method of manufacturing a semiconductor device, comprising the step of performing an annealing treatment to make it resistive.