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JPH02201945A - Surface mounting type semiconductor device - Google Patents

Surface mounting type semiconductor device

Info

Publication number
JPH02201945A
JPH02201945A JP1020045A JP2004589A JPH02201945A JP H02201945 A JPH02201945 A JP H02201945A JP 1020045 A JP1020045 A JP 1020045A JP 2004589 A JP2004589 A JP 2004589A JP H02201945 A JPH02201945 A JP H02201945A
Authority
JP
Japan
Prior art keywords
leads
land
lead
semiconductor chip
base material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1020045A
Other languages
Japanese (ja)
Inventor
Atsuhiko Izumi
和泉 篤彦
Seiichi Nishino
西野 誠一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1020045A priority Critical patent/JPH02201945A/en
Publication of JPH02201945A publication Critical patent/JPH02201945A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0296Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298Multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components
    • H10W74/00

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To make the gap between leads connected to the land on the same plane larger, avoid defective shorts by solder bridges, and enhance the reliability by connecting and fixing a first and a second lead to lands each disposed on different insulating boards. CONSTITUTION:A downward bend lead 7 is bent in parallel to the mounting surface of a base 2b on a land 5b, and a mounting section is formed. It is connected and fixed to the land 5b by a conductive adhesive 6 like solder. The front end of an upward bend lead 8 is connected and fixed to a land 5c by the adhesive 6 toward the land 5c in the vicinity of the top surface of a base 2c. With this construction, since a semiconductor chip 9 is mounted, leads 7, 8 of the semiconductor chip are connected to corresponding lands 5b, 5c, respectively, on two planes whose heights are different from each other. Thus, since the space between leads in the same plane is doubled, disadvantages such as solder bridge can be avoided, and the reliability is highly improved.

Description

【発明の詳細な説明】 [産業上の利用分野コ 本発明は絶縁基板上に半導体チップを表面実装した表面
実装型半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a surface-mounted semiconductor device in which a semiconductor chip is surface-mounted on an insulating substrate.

[従来の技術] 第3図は従来の表面実装型半導体装置を示す断面図であ
る。
[Prior Art] FIG. 3 is a sectional view showing a conventional surface-mounted semiconductor device.

配線基板1aは絶縁基材2a、配線部3a、ランド部5
a及びソルダレジスト4a等により構成されている。こ
の配線基板1aは、次に示す方法により製造されている
The wiring board 1a includes an insulating base material 2a, a wiring portion 3a, and a land portion 5.
a, solder resist 4a, and the like. This wiring board 1a is manufactured by the following method.

先ず、ガラスエポキシ等の絶縁性の基材2a上にC11
箔等の金属箔を圧着し、この金属箔にエツチング等の処
理を行って所定の形状の配線部3a及びランド部5aを
形成する。次いで、配線部3a上にソルダレジスト4a
を塗布、し、ランド部5a上に半田めっきを施す。これ
により、配線基板1aが完成する。
First, C11 is applied onto an insulating base material 2a such as glass epoxy.
A metal foil such as foil is crimped, and the metal foil is subjected to a treatment such as etching to form a wiring portion 3a and a land portion 5a of a predetermined shape. Next, a solder resist 4a is applied on the wiring part 3a.
Then, solder plating is performed on the land portion 5a. Thereby, the wiring board 1a is completed.

半導体チップ9aは、その封止部の側部からリード15
aが導出されている。このリード15aは前記封止部の
近傍で配線基板1aの実装面に向けて屈曲すると共に、
実装面の近傍で実装面と平行になるように屈曲する屈曲
部16aを有しており、また、実装面と平行に成形され
た部分が基板2aへの取付は部となっている。そして、
この取付は部が配線基板1aのランド部5aに半田等の
接着剤6aにより接着されて電気的及び機械的に接続さ
れることにより、半導体チップ9aが配線基板1a上に
実装されるようになっている。
The semiconductor chip 9a is connected to a lead 15 from the side of its sealing portion.
a has been derived. This lead 15a is bent toward the mounting surface of the wiring board 1a near the sealing portion, and
It has a bent portion 16a that is bent parallel to the mounting surface near the mounting surface, and the portion formed parallel to the mounting surface is the part that is attached to the substrate 2a. and,
In this mounting, the semiconductor chip 9a is mounted on the wiring board 1a by adhering the part to the land part 5a of the wiring board 1a with an adhesive 6a such as solder and connecting it electrically and mechanically. ing.

[発明が解決しようとする課題] しかしながら、上述した従来の表面実装型半導体装置に
おいては、半導体チップ9aのリード15aは全て同一
の長さであり、また、取付は部が同一平面上に並ぶよう
に成形されているため、リード15aの配列ピッチが狭
い半導体チップ9aを表面実装する場合、隣接するり−
ド15aの各屈曲部16aの間に半田が侵入して半田ブ
リッジを形成し、リード15a間を短絡させてしまうと
いう問題点がある。
[Problems to be Solved by the Invention] However, in the conventional surface-mounted semiconductor device described above, the leads 15a of the semiconductor chip 9a are all of the same length, and the leads 15a of the semiconductor chip 9a are mounted so that the parts are arranged on the same plane. Therefore, when surface mounting a semiconductor chip 9a with a narrow arrangement pitch of leads 15a, the adjacent
There is a problem in that solder enters between the bent portions 16a of the leads 15a, forming solder bridges, resulting in a short circuit between the leads 15a.

本発明はかかる問題点に鑑みてなされたものであって、
半田ブリッジ等による短絡不良を回避できる表面実装型
半導体装置を提供することを目的とする。
The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a surface-mounted semiconductor device that can avoid short-circuit defects caused by solder bridges or the like.

[課題を解決するための手段] 本発明に係る表面実装型半導体装置は、その第1面に複
数のランド部を設けた第1の絶縁基材と、前記第1面と
高さ位置が異なる第2面に複数のランド部を設けた第2
の絶縁基材と、封止部の側方で下方に屈曲した第1のリ
ードと上方に屈曲した第2のリードとが交互に配列され
た半導体チップとを有し、前記半導体チップの第1のリ
ード及び第2のリードのいずれか一方が前記第1の絶縁
基材のランド部と接続されて固定されており、他方のリ
ードが前記第2の絶縁基材のランド部と接続されて固定
されていることを特徴とする。
[Means for Solving the Problems] A surface-mounted semiconductor device according to the present invention includes a first insulating base material having a plurality of land portions on its first surface, and a height position different from the first surface. The second surface has a plurality of lands on the second surface.
an insulating base material, and a semiconductor chip in which first leads bent downward and second leads bent upward are arranged alternately on the side of the sealing part, and the first lead of the semiconductor chip Either one of the leads and the second lead is connected to and fixed to the land portion of the first insulating base material, and the other lead is connected to and fixed to the land portion of the second insulating base material. It is characterized by being

[作用] 本発明においては、その封止部の側方で下方に屈曲した
第1のリードと上方に屈曲した第2のリードとが交互に
配列された半導体チップを使用し、このリードを夫々第
1の絶縁基材のランド部又は第2の絶縁基材のランド部
に接続して実装する。
[Function] In the present invention, a semiconductor chip is used in which first leads bent downward and second leads bent upward are arranged alternately on the side of the sealing part, and these leads are It is mounted by connecting to the land portion of the first insulating base material or the land portion of the second insulating base material.

この第1及び第2の絶縁基板のランド部が設けられた面
は相互に高さが異なるので、同一平面上で接続すべきリ
ードの相互間の間隔は従来の2倍になるため、半田ブリ
ッジ等の形成を抑制できる。
Since the surfaces of the first and second insulating substrates on which the land portions are provided have different heights, the distance between the leads to be connected on the same plane is twice that of the conventional one, so the solder bridge etc. formation can be suppressed.

[実施例] 次に、本発明の実施例について添付の図面を参照して説
明する。
[Example] Next, an example of the present invention will be described with reference to the accompanying drawings.

第1図は本発明の第1の実施例を示す断面図である。FIG. 1 is a sectional view showing a first embodiment of the present invention.

ガラスエポキシ又はトリアジン樹脂等の絶縁性の基材2
b上には、所定の配線パターンで配線部3b及びランド
部5bが形成されている。そして、この基材2b上には
、搭載すべき半導体チップ9に整合する大きさの開口部
10が開口された基材2cが積層されて固定されている
。この基材2Cも、基材2bと同様に、ガラスエポキシ
又はトリアジン樹脂等の絶縁性物質により形成されてい
る。
Insulating base material 2 such as glass epoxy or triazine resin
Wiring portions 3b and land portions 5b are formed in a predetermined wiring pattern on b. A base material 2c having an opening 10 of a size matching the semiconductor chip 9 to be mounted is laminated and fixed on the base material 2b. This base material 2C is also formed of an insulating material such as glass epoxy or triazine resin, like the base material 2b.

基材2c上には配線部3Cが所定のパターンで形成され
ており、この配線部3C上にはソルダレジスト4bが被
覆されている。また、基材2Cの開口部10の近傍には
ランド部5Cが配設されている。
A wiring portion 3C is formed in a predetermined pattern on the base material 2c, and the wiring portion 3C is coated with a solder resist 4b. Furthermore, a land portion 5C is provided near the opening 10 of the base material 2C.

本実施例に使用される配線基板1bは上述の如く構成さ
れている。
The wiring board 1b used in this embodiment is constructed as described above.

一方、本実施例において使用される半導体チップ9は、
リード曲げ金型により封止部の近傍で下方に曲げ加工さ
れた下方曲げリード7と、上方に曲げ加工された上方曲
げリード8とが封止部の側部に交互に配列されている。
On the other hand, the semiconductor chip 9 used in this example is
Lower bent leads 7 bent downward in the vicinity of the sealing part by a lead bending die and upper bent leads 8 bent upward are arranged alternately on the side of the sealed part.

下方曲げリード7は、ランド部5b上で基材2bの実装
面と平行に曲げ加工されて取付は部が形成されており、
この取付は部とランド部5bとが半田等の導電性接着剤
6により接続されて固定されている。
The downward bending lead 7 is bent on the land portion 5b parallel to the mounting surface of the base material 2b to form a mounting portion.
In this attachment, the part and the land part 5b are connected and fixed with a conductive adhesive 6 such as solder.

また、上方曲げリード8は、基材2cの上面の近傍でラ
ンド部5Cに向けて曲げ加工されており、先端部分がラ
ンド部5Cと接着剤6により接続されて固定されている
Further, the upper bent lead 8 is bent toward the land portion 5C near the upper surface of the base material 2c, and the tip portion is connected and fixed to the land portion 5C with an adhesive 6.

本実施例においては、上述の構造により半導体チップ9
を実装するため、半導体チップのリード7.8は基板1
bの基材2bの面と基材2Cの面との相互に高さが異な
る2千面において、夫々対応するランド部5b、5cと
接続される。これにより、同一平面におけるリード間の
間隔は従来に比して2倍となるため、半導体チップの実
装時における半田ブリッジ等の不都合を回避できるから
、リード間隔が狭い半導体チップについても、極めて信
頼性が高い表面実装型半導体装置を得ることができる。
In this embodiment, the semiconductor chip 9 has the structure described above.
In order to mount the leads 7 and 8 of the semiconductor chip on the board 1
2,000 planes of the base material 2b and the base material 2C having different heights are connected to corresponding land portions 5b and 5c, respectively. As a result, the spacing between leads on the same plane is doubled compared to the conventional method, which avoids problems such as solder bridging when mounting semiconductor chips, resulting in extremely high reliability even for semiconductor chips with narrow lead spacing. It is possible to obtain a surface-mounted semiconductor device with high resistance.

なお、開口部10は、半導体チップ9の搭載精度を考慮
して、開口部10の壁面が下方曲げり−ド7の取付は部
の先端から0.5龍以上離れるように開口することが好
ましい。
Note that, in consideration of the mounting accuracy of the semiconductor chip 9, the opening 10 is preferably opened so that the wall surface of the opening 10 is bent downward and is separated from the tip of the door 7 by at least 0.5 mm. .

第2図は本発明の第2の実施例を示す断面図である。FIG. 2 is a sectional view showing a second embodiment of the invention.

絶縁性の基材2e上には所定のパターンで配線部3d、
ランド部5d及びランド部5eが形成されている。そし
て、配線部3d上にはソルダレジスト4cが被覆されて
いる。配線基板1cは、このようにして構成されている
Wiring portions 3d are formed in a predetermined pattern on the insulating base material 2e,
A land portion 5d and a land portion 5e are formed. The wiring portion 3d is coated with a solder resist 4c. The wiring board 1c is configured in this manner.

盛上げ端子11は絶縁性の基材2dの上面に上層端子部
13を形成し、下面に下層端子部14を形成して、上層
端子部13と下層端子部1゛4とをスルーホール12に
より電気的に接続したものである。そして、この盛上げ
端子11の下層端子部14がランド部5dに半田等の接
着剤6により接続固定されている。
The raised terminal 11 has an upper layer terminal portion 13 formed on the upper surface of the insulating base material 2d, a lower layer terminal portion 14 formed on the lower surface, and electrical connection between the upper layer terminal portion 13 and the lower layer terminal portion 1-4 through the through hole 12. It is connected to The lower terminal portion 14 of this raised terminal 11 is connected and fixed to the land portion 5d with an adhesive 6 such as solder.

半導体チップ9は、第1の実施例と同様に、封止部の近
傍で下方又は上方に交互に曲げ加工された夫々下方曲げ
リード7及び上方曲げリード8を有し、更に各リードの
先端部は実装面に平行に曲げ加工されて取付は部となっ
ている。そして、下方曲げリード7の取付は部はランド
部5eと接着剤6により接続されて固定されており、上
方曲げリード8の取付は部は盛上げ端子11の上面に形
成された上層端子部13に接続されて固定されている。
Similarly to the first embodiment, the semiconductor chip 9 has downwardly bent leads 7 and upwardly bent leads 8 which are bent downward or upward alternately in the vicinity of the sealing portion, and furthermore, the tips of each lead are bent downwardly or upwardly. The mounting surface is bent parallel to the mounting surface. The lower bent lead 7 is attached to the land portion 5e and fixed by adhesive 6, and the upper bent lead 8 is attached to the upper layer terminal portion 13 formed on the upper surface of the raised terminal 11. Connected and fixed.

本実施例においては、上述の構造により半導体チップ9
が実装されているため、第1の実施例と同様に、半田ブ
リッジ等のリード間の短絡を回避できる。また、本実施
例においては、半導体チップの実装領域の基材上にも配
線を設けることができるため、極めて高密度の配線を行
うことができる。
In this embodiment, the semiconductor chip 9 has the structure described above.
Since this is implemented, short circuits between leads such as solder bridges can be avoided as in the first embodiment. Further, in this embodiment, since wiring can be provided also on the base material in the mounting area of the semiconductor chip, extremely high-density wiring can be performed.

[発明の効果コ 以上説明したように本発明によれば、封止部の側方で下
方に屈曲した第1のリードと上方に屈曲した第2のリー
ドとが交互に配列された半導体チップを使用して、この
第1のリードと第2のリードとを夫々異なる絶縁基材上
に設けられたランド部に接続して固定するから、同一平
面上のランド部と接続されるリード間の間隔は極めて大
きくなる。これにより、隣接するリードが半田ブリッジ
等により相互に接続される短絡不良の発生を回避して、
信頼性が高い表面実装型半導体装置を得ることができる
[Effects of the Invention] As explained above, according to the present invention, a semiconductor chip in which the first leads bent downward and the second leads bent upward are arranged alternately on the side of the sealing part. Since the first lead and the second lead are connected and fixed to land portions provided on different insulating base materials using the same method, the distance between the land portions and the connected leads on the same plane is reduced. becomes extremely large. This avoids the occurrence of short circuit defects where adjacent leads are connected to each other by solder bridges, etc.
A highly reliable surface-mounted semiconductor device can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の第1の実施例を示す断面図、第2図は
本発明の第2の実施例を示す断面図、第3図は従来の表
面実装による半導体装置の実装構造を示す断面図である
。 1a、lb、lC;配線基板、2a、2b、2c、2d
、2e ;基材、3a、3b、3c、3d;配線部、4
a、4b、4c ;ソルダレジスト、5a、5b、5c
、5d、5e ;ランド部、6゜6a;接着剤、7;下
方曲げリード、8;上方曲げリード、9.9a;半導体
チップ、10.開口部、11;盛上げ端子、12;スル
ーホール、13;上層端子部、14;下層端子部、15
a;リード、16a;屈曲部
Fig. 1 is a sectional view showing a first embodiment of the present invention, Fig. 2 is a sectional view showing a second embodiment of the invention, and Fig. 3 is a mounting structure of a semiconductor device by conventional surface mounting. FIG. 1a, lb, lc; wiring board, 2a, 2b, 2c, 2d
, 2e; Base material, 3a, 3b, 3c, 3d; Wiring portion, 4
a, 4b, 4c; solder resist, 5a, 5b, 5c
, 5d, 5e; Land portion, 6° 6a; Adhesive, 7; Downward bent lead, 8; Upward bent lead, 9.9a; Semiconductor chip, 10. Opening portion, 11; Raised terminal, 12; Through hole, 13; Upper layer terminal portion, 14; Lower layer terminal portion, 15
a; Lead, 16a; Bent part

Claims (1)

【特許請求の範囲】[Claims] (1)その第1面に複数のランド部を設けた第1の絶縁
基材と、前記第1面と高さ位置が異なる第2面に複数の
ランド部を設けた第2の絶縁基材と、封止部の側方で下
方に屈曲した第1のリードと上方に屈曲した第2のリー
ドとが交互に配列された半導体チップとを有し、前記半
導体チップの第1のリード及び第2のリードのいずれか
一方が前記第1の絶縁基材のランド部と接続されて固定
されており、他方のリードが前記第2の絶縁基材のラン
ド部と接続されて固定されていることを特徴とする表面
実装型半導体装置。
(1) A first insulating base material having a plurality of lands on its first surface, and a second insulating base material having a plurality of lands on its second surface at a different height from the first surface. and a semiconductor chip in which first leads bent downward and second leads bent upward are arranged alternately on the side of the sealing part, and the first lead and the second lead of the semiconductor chip are arranged alternately. One of the two leads is connected to and fixed to the land portion of the first insulating base material, and the other lead is connected to and fixed to the land portion of the second insulating base material. A surface-mounted semiconductor device characterized by:
JP1020045A 1989-01-30 1989-01-30 Surface mounting type semiconductor device Pending JPH02201945A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1020045A JPH02201945A (en) 1989-01-30 1989-01-30 Surface mounting type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1020045A JPH02201945A (en) 1989-01-30 1989-01-30 Surface mounting type semiconductor device

Publications (1)

Publication Number Publication Date
JPH02201945A true JPH02201945A (en) 1990-08-10

Family

ID=12016089

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1020045A Pending JPH02201945A (en) 1989-01-30 1989-01-30 Surface mounting type semiconductor device

Country Status (1)

Country Link
JP (1) JPH02201945A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04184967A (en) * 1990-11-19 1992-07-01 Mitsubishi Electric Corp Semiconductor device
JPH0529747A (en) * 1991-07-19 1993-02-05 Akai Electric Co Ltd Printed wiring board
US5450289A (en) * 1993-03-05 1995-09-12 Samsung Electronics Co., Ltd. Semiconductor package and a printed circuit board applicable to its mounting
EP0766505A3 (en) * 1995-09-29 1998-12-23 Allen-Bradley Company, Inc. Rigid-flex circuit board having a window for an insulated mounting area

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04184967A (en) * 1990-11-19 1992-07-01 Mitsubishi Electric Corp Semiconductor device
JPH0529747A (en) * 1991-07-19 1993-02-05 Akai Electric Co Ltd Printed wiring board
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