JPH02184816A - Active matrix type liquid crystal display device - Google Patents

Abstract

PURPOSE:To eliminate the flicker of a display by connecting the drains of respective transistors (TRs) connected to address wires of odd lines or even lines to 1st or 2nd signal wire driving circuits and scanning the same address lines at every 1/2 frame period. CONSTITUTION:Plural lines of the address wires Y1 to Yn are divided to two groups; odd address wires Y1, Y3,... YK-1, YK-1,... Yn-1 (where, k, n are even numbers) and even address wires Y2, Y4,... Yk, YK+2,... Yn. The drains of the respective TRs connected to the respective address wires are connected to the 1st or 2nd signal wire driving circuits 22a, 22b and the same address wires are scanned at every 1/2 frame period. Further, the display signals once written in the same liquid crystal cell 5 and the display signals inverted in polarity are delayed by 1/2 frame period and are written. The phases of the waveforms of the display voltage impressed to the same liquid crystal cell 5 are shifted by 180 deg. at every 1/2 frame period in this way, by which the frequency components of the flicker are doubled and the flicker of the display is made hardly sensible.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to an active matrix type liquid crystal display device using a thin film transistor array, and in particular to an active matrix type liquid crystal display device with improved driving means. Related to display devices.

(Prior Art) In recent years, active matrix liquid crystal display devices have been actively developed in which a thin film transistor (hereinafter abbreviated as TFT) is incorporated into a matrix array as a switching element to drive a liquid crystal panel.

An example is shown in FIG. This conventional active matrix liquid crystal display device has multiple rows (n) of address lines (Yl), ... (Yn) and multiple columns (m) of signal lines (
A liquid crystal cell ( 5)
A pixel display electrode (2) is arranged. Then, the gate electrodes of the TFTs (1) located on the same row are common address lines (Yl).

...(Yn), TFT (1) located on the same column
The drain electrodes of each signal line (Xl) are common,...
- (Xm>). Roughly speaking, the multiple rows of address lines (Yl), . . . (Yn) are connected to the address line drive circuit (6), and the multiple columns of signal lines (Xl).

... (Xm) is connected to the signal line drive circuit (7).

The address line drive circuit (6) has its input terminal (8)
, (9), a scanning signal is generated from a vertical scanning start pulse and a vertical shift clock pulse, and the address lines (Yl), . . . (Yn) are sequentially scanned. The signal line drive circuit (7) also has an input terminal (10),
A sample pulse is created from the horizontal start pulse and horizontal shift clock pulse supplied to the terminal (11), and a display signal whose polarity is inverted every frame supplied to the other input terminal (12) is sampled and held. line(
Xl), ... (Xm).

FIG. 6 is a drive voltage waveform diagram of the active matrix type liquid crystal display device shown in FIG. 5 above. vX shown in the same figure (a) is the display signal voltage supplied to the signal lines (Xl), ... (Xm>), and vY is the address line (Yl),
. . . (Yn) is the scanning signal voltage supplied to the terminal. The polarity of the display signal voltage vX is inverted every frame period T using the polarity inversion reference voltage VB as a reference. Further, Vs shown in the same figure (b) is a display signal voltage written to and held in the capacitance of the liquid crystal cell, and VC is a common electrode potential.

By the way, the scanning signal voltage ■Y and the display signal voltage V
When X is supplied to the address lines (Yl), . . . (Yn) and the signal lines (Xl), . The voltage ■S having the waveform shown in the figure is written and held, but a level shift ΔV occurs between the final write voltage and the holding voltage. Therefore, even if the input display signal voltage Vx has the same imaging width on the positive and negative sides with respect to the polarity inversion reference voltage VB, the voltage ■s applied to the liquid crystal cell (5) The value becomes different between the positive electrode side and the negative electrode side with respect to the common electrode potential VC. As a result, the fundamental frequency of the voltage S applied to the liquid crystal panel (5) is halved, causing flicker to occur in the display and significantly deteriorating the image quality.

(Problems to be Solved by the Invention) As described above, in the conventional active matrix liquid crystal display device, the effective value of the display signal voltage VS applied to the liquid crystal panel is on the positive side and the negative side with respect to the opposing common electrode potential c. Since the fundamental frequency of the display signal voltage Vs applied to the liquid crystal panel is halved, there is a problem in that flickering occurs in the display and the image quality is significantly degraded.

This invention was made in order to solve the above-mentioned problems, and improves the display by eliminating the flickering that occurs when the fundamental frequency of the display signal voltage vS applied to the liquid crystal panel is halved. The purpose is to

[Structure of the Invention] (Means for Solving the Problems) A switch made of a transistor is provided corresponding to each of the pixel display electrodes of a liquid crystal cell arranged in a plurality of rows and a plurality of columns. The gates of the transistors located on the same column are commonly connected to the same address line and connected to the address drive circuit, and the drains (or sources) of the transistors located on the same column are commonly connected to the same signal line and connected to the signal line drive circuit. In an active matrix type liquid crystal display device, the drain (or source) of each transistor connected to an odd-numbered row address line is
In addition to connecting to a signal line drive circuit, the drain (or source) of each transistor connected to an even-numbered row address line is connected to a second signal line drive circuit, and the same address line is scanned every 1/2 frame period. As a result, the same display signal with reversed polarity is supplied to the same liquid crystal cell with a delay of 172 frame periods.

(Function) As described above, multiple rows of address lines are divided into odd-numbered rows and even-numbered rows, and the drain (or source) of each transistor connected to the odd-numbered row address line is connected to the first signal line drive circuit.
In addition, by connecting the drain (or source) of each transistor connected to an even-numbered row address line to a second signal line drive circuit and scanning the same address line every 1/2 frame period, the same liquid crystal cell can be If a display signal written twice and a display signal whose polarity is inverted are written with a delay of 172 frame periods, the phase of the waveform of the display voltage applied to the same liquid crystal cell will change by 180° every 172 frame periods.
The frequency component of the flicker can be doubled compared to the conventional driving means, and the flickering of the display can be made less perceivable.

(Example) Hereinafter, the present invention will be described based on an example with reference to the drawings.

FIG. 1 shows the structure of an active matrix type liquid crystal display device which is an embodiment of the present invention. As shown in FIG. 2, the liquid crystal panel (20) of this liquid crystal display device has multiple rows of address lines (Yl), ... (Yn) and multiple columns of signal lines (Xl), ... (Xm). ) and (X′1),・
...(X'm) are arranged orthogonally, and T is placed at each intersection.
An FT (1) and a pixel display electrode (2) of a liquid crystal cell (5) are arranged. The TFT located on the same row (
1) gate electrodes are connected to a common address line (Yl
), ・"(Yn) and the drain electrodes of TFTs (1) located on the same column are connected to common signal lines (Xl), ・"(Xm), (X'1), . . .・(X'm
> is connected to. In the liquid crystal display device of this example, the plurality of address lines (Yl), . . . (Yn)
to odd address lines (Yl>, (Y3), ... (YK-
1>, (YK +1>.

... (Yn-1> (where n is an even number) and even address lines (Y2), (Y4), ... (YK),
(YK +2>, ... (Yn)), and correspondingly, the signal line drive circuit is divided into two groups, odd address lines (Yl>, (Y3), ... (YK -1>
.

The signal line (Xl
).

. . . (Xm) to the signal line drive circuit I (21a), even address lines (Y2 >, (Y4), . . . (Y)).

(YK+2>, ... (Yn)
'1), ・''(X'm) as signal line drive circuit II
(21b). In addition, the address line (Yl
), ... (Yn) is also divided into two groups, and the (Yl)
.

(Y2), ... (YK-1> is the address line drive circuit
(22a), (YK), (YK +1>,
”・(Yn) as address line drive circuit I (22b)
is connected to. In FIG. 2, (2) is a liquid crystal, and (3) is a counter common electrode.

The above address line drive circuits (2) and fl (22a).

(22b) C, respective input terminals (23a), (
24a), (23b) and (24b), a scanning signal is generated from the vertical scanning start pulse and vertical shift clock pulse supplied to the address lines (Yl>,
(Y2>.

...(YK-1> and even address line (YK).

(YK+1), . . . (Yn) are sequentially scanned at the same timing. In addition, the signal line drive circuit engineer and ■ (21a)
, (21b) are the input terminals (25a), (21b), respectively.
26a).

A sample pulse is generated from the horizontal scanning start pulse and horizontal shift clock pulse supplied to the terminals (25b) and (26b), and the sample pulse is supplied to the other input terminal (27a).

(27b) and hold the display signal and display signal supplied to each signal line drive circuit.
The signal line (X) connected to I (21a) and (21b)
l).

...(Xm) and (X'1), ...(X'
Drive m>.

The input terminal (27a) of the display signal generator supplied to the signal line drive circuit (2) is connected to the video signal input terminal (30) via a changeover switch (29). Further, the display signal input terminal (27b) of the display signal (■) supplied to the signal line drive circuit II (21b) is connected to the A/D converter (31),
Memory that can store data for 1/2 frame period (3
2) is connected to a video signal input terminal (30) via a D/A converter (33), an inverting amplifier (34), and a changeover switch (29).

Thus, the video signal input to the video signal input terminal (30) is converted into a digital signal by the A/D converter (31) and stored in the memory (32), and the signal from the timing pulse generation circuit (35) is In other words, the address line (Yl>) is delayed by 1/2 frame period.

... (Yn), data is read out from the memory (32), converted into an analog signal by the D/A converter (33), and further inverted in polarity by the inverting amplifier (34). As a result, a signal that is 1/2 frame period earlier than the signal input to the input terminal (30) is obtained at the output of the inverting amplifier (34). The changeover switch (29) is switched every horizontal scanning period based on the video signal input to the video signal input terminal (30), the output of the inverting amplifier (34), and the signal from the timing pulse generation circuit (35). , create display signal ■ and display signal ■.

Figure 3 shows the relationship between the video signal, the display signal ■ and the display signal ■, and the relationship between the scanning signals of the address lines (Yl), ... (Yn) obtained from each address line drive circuit ■, ■. . In FIG. 3, one day represents one horizontal scanning period, and T represents one frame scanning period of the liquid crystal cell.

By the way, if each signal is created as described above, the result shown in Figure 4 (
As shown in Fig. b), the display signal voltage VS applied to the liquid crystal cell writes the same signal that differs only in positive and negative polarity in one frame period T, and is shown in comparison with Fig. 3(a). Compared to the conventional voltage application method, the flicker frequency component is higher. Therefore, for example, if the video signal is
If a signal is used and scanning is performed in a non-interlaced manner, the flicker frequency component will be 60H2, which can be made imperceptible to the human eye.

In the above embodiment, the signal line was connected to the drain electrode of the TFT, but the connection between the TFT and the signal line is different from that of the TFT.
A signal line may be connected to the source electrode.

Further, although the inverting amplifier (34) is connected after the D/A converter (33), it may be inserted between the input terminal (30) and the switch (29) instead. Furthermore, in the above embodiment, the memory (3
Although 2) is used, other delay means, such as a shift register having the number of bits for one screen, etc. may also be used.

[Effect of the invention] Switches made of transistors are provided at the intersections of address lines in multiple rows and signal lines in multiple columns of a liquid crystal panel, and the gates of transistors located on the same row are commonly connected by the same address line. The multiple rows of address lines are divided into odd and even rows, and the drain or source of each transistor connected to the odd row address line is connected to the first signal line drive circuit, and each transistor connected to the even row address line is connected to the first signal line drive circuit. Connecting the drain or source of to the second signal line drive circuit,
By scanning the same address line every 1/2 frame period, the same display signal written once to the same liquid crystal cell and the same display signal with the polarity reversed are written with a delay of 172 frame periods. The phase of the waveform of the display voltage that is not applied to the liquid crystal cell is shifted by 1800 every 172 frame periods, and the flicker frequency component can be doubled compared to conventional driving means, resulting in a display device in which you do not notice any flickering in the display. can do.

[Brief Description of the Drawings] Figures 1 to 4 are detailed explanatory diagrams of the present invention.
The figure shows the configuration of an active matrix type liquid crystal display device, which is an example of the same, Figure 2 shows the configuration of the liquid crystal panel, and Figure 3 shows the relationship between each signal applied to the liquid crystal panel. Voltage waveform diagram, Figure 4 (a) and (b)
are comparative diagrams of the voltage waveforms of display signals applied to the conventional liquid crystal panel and one embodiment of the present invention, respectively, where (a) shows the voltage waveform written and held in the conventional liquid crystal panel, and (b)
is a voltage waveform in the above embodiment, FIG. 5 is a diagram showing the main part configuration of a conventional active matrix liquid crystal display device, and FIGS. 6(a) and (b) are display signals supplied to the signal lines, respectively. and the voltage waveform of a display signal written and held in the liquid crystal panel. 1... Thin film transistor (TFT) 2... Pixel display electrode 3... Liquid crystal layer 5... Liquid crystal cell 20... Liquid crystal panel 21a, 21b... Signal line drive circuit 22a, 22b... Address Line drive circuit 29...changeover switch 30...video signal input terminal

Claims (1)

[Claims] A switch made of a transistor is provided corresponding to each pixel display electrode of a liquid crystal cell arranged in a plurality of rows and a plurality of columns, and the gates of the transistors located on the same row are connected to the same address line. The drains (or sources) of the transistors located on the same column are commonly connected to an address line drive circuit that supplies scanning signals, and the drains (or sources) of the transistors located on the same column are commonly connected to the same signal line and are connected to a signal line drive circuit that supplies display signals. In the active matrix liquid crystal display device connected to each other, the drain (or source) of each transistor connected to an odd-numbered address line among the plurality of address lines is connected to a first signal line drive circuit; The drains of each of the above transistors connected to the even row address lines (
or source) to the second signal line drive circuit, and
By scanning the same address line every 2 frames, the same display signal with reversed polarity is sent to the same liquid crystal cell.
An active matrix type liquid crystal display device characterized in that the display is delayed by two frame periods.