JPH02170638A - Ic circuit network connected by bus line - Google Patents

Abstract

PURPOSE:To simultaneously send data through a data line by providing a circuit means to block the supply of a confirming signal to the data line between an arbitrary IC out of the plural ICs and a data line. CONSTITUTION:A unidirectional interface circuit 22, which makes only the data on a data line 2 pass through to a monitor device 20 side, is provided between the data line 2 and the monitor device 20. Thus a confirming signal ACK from the monitor device 20 is not sent to the data line 2 side, and the data on the data line can be monitored by the monitor device 20 without causing a bus line error. Further, the data can be simultaneously sent, for example, from a CPU 6 through bus lines 1 and 2 to a memory 14 and the monitor device 20, and communication at 1:2 is attained without generating the bus line error.

Description

Detailed Description of the Invention [Industrial Field of Application] The present invention refers to a plurality of ICs <semiconductor integrated circuits> on a data line and a clock line, suitable for use in, for example, a television receiver. In the present invention, electronic circuits in general including semiconductor integrated circuits are collectively referred to. ) are connected in parallel, and one of these multiple ICs sends data to the other IC via its data line, and the other IC returns a confirmation signal to that one IC via its data line. The present invention relates to an IC circuit network connected by such a bus line.

[Summary of the invention]

The present invention is suitable for use in, for example, a television receiver, in which a plurality of ICs are connected in parallel to a data line and a clock line, and one IC of the plurality of ICs connects to another IC.
An IC connected by a bus line that sends data to the first IC via its data line and sends a confirmation signal from the other IC back to the first IC via its data line.
In the C network, any one of the plurality of ICs
By providing a circuit means between the IC and the data line to prevent the confirmation signal from being supplied to the data line, one IC of the plurality of ICs can communicate with the other plurality of ICs. This allows data to be sent simultaneously via the data lines without causing bus line errors.

[Conventional technology]

In order to simplify internal wiring in television receivers, etc., multiple ICs are connected in parallel to a two-wire bus line consisting of a clock line and a data line, and one of the multiple ICs 1 between and one other IC
IC circuit networks that are capable of transmitting and receiving data on a one-to-one basis have come into use.

FIG. 6 shows such a conventional IC circuit network disclosed in, for example, Japanese Unexamined Patent Publication No. 57-106262,
In this Figure 6, (1) is the serial clock SCL
(2) is the clock line that transmits the serial data S
These are data lines that transmit DA, and these clock lines (1) and data lines (2) each have resistors (3).
and (4) are pulled up to a higher voltage source (for example, 12 V or 5 V > (5).
6) shows a certain microcomputer (hereinafter referred to as CPU) made up of one or more ICs as a whole, and in this CPU (6), the clock line (1) is S
The data line (2) is connected to one input terminal of the control circuit (9) via the CL terminal (7A) and the high input impedance buffer circuit (8A), and the data line (2) is connected to the SDA terminal (108) and the high input impedance buffer circuit (8A). Buffer circuit (IIA
> to the other input terminal of the control circuit (9). Then, its SCL terminal (7A) and S
The DA terminal (IOA) is grounded through N-channel MO5 type FETs (12^) and (13A), and receives control signals JA and K from the control circuit (9).
A is the MO3 type FET (12A) and (
13A) and its MO3 type FE
The opening and closing of T (12A) and (13A) can be freely controlled by the control circuit (9).

Therefore, this CPU (6) is a buffer circuit (8 people)
and (IIA), the data on the clock line (1) and the data line (2), respectively, can be input manually, and the control signals JA and KA are used to control the MO3 type FET (
12A) and (13A) intermittently conduct the serial clock SCL on the clock line (1) and the serial data S on the data line (2), respectively.
DA can be generated.

In addition, (14) indicates a memory that is integrated into an IC as a whole, and this memory (14) has an SCL terminal (7B) and an SDA terminal.
Clock line (1) respectively via terminal (10B)
and data line (2), and CP
When compared with U(6), only the control circuit (9) is replaced with RAM (15). Therefore, in this memo'J (14), CP
The portion corresponding to CPU U (6) is shown with A in the reference numeral attached to the corresponding portion of CPU U (6) replaced with 已. This memory (14) can input data on the clock line (1) and data line (2) similarly to the CPU (6), and uses control signals JB and KB to input data on the clock line (1), respectively. serial clock SC
Serial data SDA on L and data lines (2) can be generated.

In addition, (16) is a keyboard IC, and (17) is a display IC, and these ICs (16), (17)
When compared with the CPU (6), the control circuit (9) has a structure in which the control circuit (9) is replaced with a respective circuit.

In addition, if it is not necessary to send the serial clock SCL on the clock line (1) by the IC, the Clock
MO3 type FET (12A) of P U (6)
The parts corresponding to , etc. can be omitted.

In FIG. 6, the operation when the CPU (6) reads data from the memory (14) will be explained with reference to FIG. As shown in (18), the clock line (1
) on the serial clock SCL (FIG. 7A) and the serial data 5DA on the data line (2) (FIG. 7D) are both held at high level "1". And CPU
(6) causes the serial f-93D to rise by raising the control signal KA (this inverted signal KA is shown in Figure 7).
A becomes a low level "0" and the CPU (6) becomes a "mask" in the IC circuitry.

Thereafter, the CPU (6) receives a control signal JA (this inverted signal JA is the serial clock SCL of FIG. 7A).

) to sequentially send out a certain serial clock SCL onto the clock line (1) using nine pulses as shown in FIG. Then, the CPU (6) controls the control signal KA to output 8 bits, ie, 1 byte, of data D1 to D8 in synchronization with the first 8 of the 9 pulses, as shown in Figure 7. It is sent on the data line (2). This 1-byte data D1 to D8 is stored in the memory (14
) includes the device address.

The memory (14) includes a buffer circuit (8B) and a buffer circuit (11).
1 synchronized to its serial clock SCL via B>
Byte data D1 to D8 are taken into the device address discrimination circuit in RAM (15), and the device address indicated by the data D1 to D8 is assigned to the memo IJ (14)! , 4 address, the control signal KB (this inverted signal KB is shown in FIG. 7C) is raised in synchronization with the 9th pulse of the serial clock SCL, and the confirmation signal ) Generate an ACK book. In this case, the inverted signal K of the control signal KA of the CPU (6)
Since A is a high level "1", its sure S Ninja word A
The CK book becomes the serial data SDA signal as it is,
As shown by the broken line block (19>), the serial data SD is synchronized with the 9th pulse of the serial clock SCL.
An acknowledgment signal ACK as Δ is sent on the data line (2).

Therefore, when the CPU (6) receives the low level "0" confirmation signal ACK on its data line (2) synchronized with the 9th pulse of the serial clock SCL, the memo IJ (14) operates normally. The rXi can recognize what is being done, and can begin the next data read operation.

[Problem to be solved by the invention]

In an IC circuit network connected by a conventional bus line,
For example, for debugging during research and development, operation confirmation during factory shipping adjustment, and identification of defective parts during maintenance, bus lines (1) and (2), as shown by the broken lines in Figure 6, may be used. Each SCL terminal (7ε)
A monitor device (20) which is converted into an IC and has a monitor picture tube or the like externally attached is connected to the bus line (1) via a 5DAi element (IOE).

There are cases where it is desired to monitor the state of (2).

However, if the monitor device (20) is connected in this way and the device address of this monitor device (20) is shared with the device address of the memo 'J (14), for example, the memo will be sent from the CPU (6). 'J (14)
When you try to read or write data in the memo 'J (1
4) as well as its monitor device (20), the mP signal ACK is sent on the data line (2), causing a bus line error, and these bus lines (1)
There was an inconvenience that the status (2) could not be monitored.

Such a disadvantage is that the conventional IC circuit network as shown in the example in FIG.
This is due to the fact that it is based on one-to-one communication in which data is sent and received only between one IC and one other IC.

In view of these points, the present invention makes it possible to simultaneously send data from one IC to multiple other ICs without causing a bus line error in an IC circuit network connected by such a bus line. The purpose is to do so.

[Means to solve the problem]

For example, as shown in FIG.
and the clock line (1), and a plurality of ICs (6), (
14).

(16) and (20) are connected in parallel, and the data line (
2) Send data (for example, D1 to D8) via m I! from other ICs. In an IC circuit network connected by bus lines (1) and (2) in which the signal ACK is sent back to that one IC via its data line (2), any certain I of the plurality of ICs A circuit means (22) is provided between the data line (2) and the data line (2) for preventing the confirmation signal ACK from being supplied to the data line (2).

C Effect] According to the present invention, data D1 to D8 on the data line (2) are taken into the certain IC (20) via the circuit means (22). And that data D
If 1 to D8 are data for another IC that has the same device address as that IC (20), the other IC sends an acknowledgment signal ACK on its data line (2). However, the confirmation signal ACK output from the certain IC (20>) is blocked by the unidirectional circuit means (22) at least at the timing of sending out the confirmation signal.

Therefore, the data line (
Data D1 to D8 are sent via 2).

〔Example〕

A first embodiment of an IC network connected by a bus line according to the present invention will now be described with reference to FIG. In this example, the present invention is applied to a system that monitors the status of a bus line in an IC circuit network, and the parts in FIG. 1 that correspond to those in FIG. Therefore, detailed explanation thereof will be omitted.

FIG. 1 shows the IC circuit network of this example. In FIG. 1, a certain bus line from a clock line (1) and a data line (2) includes a CPU (6), which is implemented as an IC, respectively.
Memory (14) and keyboard IC (16) are connected in parallel, clock line (1) and data line (2)
A serial clock SCL and a serial data SDA are respectively transmitted to the terminals.

In addition, (20) indicates an IC monitor device,
A monitor receiver and data recorder (not shown) are connected to this monitor device (20). This monitor device (20) has a high input impedance buffer circuit (8ε), (11ε
), MO3 type FET (12B), (13B) and processing circuit (21), bus line (1),
(2) If the high side voltage is about 5V, the MO
5 type FET (12ε).

(13B) N P N transistors may be used instead of (13B). The processing circuit (21) is connected to the bus line (
You can capture the signals of 1) and (2) and output them to the attached monitor receiver, etc., and also use the MO3 type FET (12)
, (131E), and has a function of controlling control signals JE and KE for the bus lines (1) and (2) to send pseudo signals to the bus lines (1) and (2). The monitor device (2o)
Connect the SCL terminal (7E) connected to the input terminal of one of the buffer circuits (8E) to the clock line (1),
The SDA terminal (10ε) connected to the input terminal of the other buffer circuit (11E) is connected to the interface circuit (
1/F circuit) (22) to the data line (2).

The interface circuit (22) is formed by connecting a high input impedance buffer circuit <23> and a resistor (24) in series, and connects the input terminal of the buffer circuit (23) to the data line (2), Connect one end of the resistor (24) to the SDA terminal (10E) of the monitor device (20).
Connect to. The resistor (24) is the MO3 type FET
(13E) When the buffer circuit (
23) This is to prevent overcurrent from flowing.

To explain the operation of the example in Figure 1, for example, the monitor device (
Assume that the device address of 20) is set to be the same as the device address of memory (14). In this case, CPU (
6) tries to read the data of the memory (14), and the clock line (1) and the data line (2) each receive a certain serial clock SCL and the device address of the memory (14) by nine pulses. When the byte of serial data D1 to D8 is sent, an acknowledgment signal ACK is sent from the memory (14) onto the data line (2) in synchronization with the ninth serial clock SCL.

Similarly, the monitor device (20) also has a buffer circuit (
23) and (11B), and in an attempt to send out the confirmation signal ACK in synchronization with the ninth serial clock SCL, the control signal KE of the processing circuit (21) is Set to high level "1". However, the control signal K
E is set to high level "1" and its MO3 type F E
Even if T (13B) becomes conductive, the output current of the buffer circuit (23) only increases and has no effect on the data line (2). In this example, a unidirectional interface circuit is provided between the data line (2) and the monitor device (20) that allows only the data on the data line (2) to pass to the monitor device (20) side. (22), the monitor device (
The confirmation signal ACK from 20) is the data line [2]
There is the benefit of being able to monitor data on that data line (2) with that monitor device (20) without being transmitted to the side and causing bus line errors.

Furthermore, according to the example in FIG. 1, bus lines (1), (2
), for example, from CPU (6) to memo 'J (1
4) and the monitor device (20) at the same time, which has the advantage of enabling one-to-two communication without generating bus line errors.

Next, a second embodiment of the present invention will be described with reference to FIG. 2, in which parts corresponding to those in FIG. 1 are denoted by the same reference numerals.

This example in Figure 2 replaces the unidirectional interface circuit (22) in the example in Figure 1 with an interface circuit (25) that can be switched between bidirectional and unidirectional, and This is a conditional input/output terminal.

In this interface circuit (25), a resistor (26) and a resistor (26) are connected in parallel with a buffer circuit (23) and a resistor (24) connected in series between the data line (2) and the SD/IJ element (IOE). (27), and connect the connection point between these resistors (26) and resistors (27) to NPN
) to the emitter of the transistor and connect this transistor (
29) is connected to the higher voltage source (5). The movable contact (28a) of the mode selector switch (28) allows the base of this transistor (29) to be opened and closed manually.
) and press 2 of this mode selector switch (28).
One of the two fixed contacts is connected to a voltage source (5) and the other is grounded.

In the example in Fig. 2, when the operator switches the movable contact (28a) of the mode selector switch (28) to the ground side (during normal operation), the transistor (29) is in the open state, so the data line ( The data in 2) is sent to the monitor device (20) via the buffer circuit (23), resistor (24) and buffer circuit (IIB).
is taken into the processing circuit (21). Then, when the processing circuit (21) sets the control signal KE to high level "1", the potential of the data line (2) goes to low level "0" via the resistors (26) and (27). As a result, its monitoring device (20) can send data on its data line (2), including an acknowledgment signal ACK, like a normal IC.

Furthermore, when the operator switches the movable contact (28a) of the mode changeover switch (28) to the higher voltage source (5) (when monitoring the bus line), the transistor (29) becomes conductive. Those resistors (26)
The potential at the connection point between and (27) is always set to high level "1". Therefore, the processing circuit (21) sets the control signal KE to high level "1" and the MO3 type F E
Even if T(13B) is made conductive, the potential of its data line (2) is maintained at a high level "1".

In this way, in the example in Figure 2, the mode changeover switch (2
By switching the movable contact (28a) of 8) to the high voltage source (5) side, the interface circuit (25
) is a unidirectional circuit that passes only the data on the data line (2) to the monitor device (20), so the confirmation signal A from the monitor device (20)
Since CK is not sent to the data line (2) side, data on the data line (2) can be monitored without causing bus line errors. Furthermore, the second
In the illustrated example, by switching the movable contact (28a) of the mode changeover switch (28) to the ground side,
The confirmation signal ACK and serial data D1 to D8 from the monitor device (2o) are directly transferred to the data line (2o).
), which has the advantage of expanding the range of applications.

In the example in Figure 2, the mode selector switch (28) provided in the interface circuit (25) controls the on/off of the disc (29), but this mode selector switch (28) is omitted. Then, a mode select terminal MOD is provided in the processing circuit (21), and the mode select terminal MOD and the base of the transistor (29) are connected with a lead wire (30). The transistor (29) may be turned on/off.

Next, a third embodiment of the present invention will be described with reference to FIG. 3, in which parts corresponding to those in FIG. 2 are denoted by the same reference numerals.

This example in Figure 3 is the ink face circuit (25) of the example in Figure 2.
This uses a simplified interface circuit (34).

As shown in FIG. 3, the interface circuit (34) includes a buffer circuit (23) and a resistor (24) connected in series, and resistors (26) and (27) connected in parallel to these.
and an NPN l-transistor (29) connected between the connection point of these resistors (26) and (27) and the high-potential side voltage source (5). Further, (31) indicates the monitor device of this example, and this monitor device (31)
is the processing circuit (2) in the monitor device (20) in FIG.
1) is replaced with a processing circuit (32). This processing circuit (32) has a confirmation signal output terminal AK, and a certain serial clock SCL is inputted from the clock line (1) via the buffer circuit (8B) in the form of nine pulses as shown in FIG. When the voltage is 1, a control signal that becomes high level "1" is output from the m-pressure signal output terminal AK in synchronization with the 9th pulse of the serial clock SCL as shown in FIG. 4C. The signal is the AK terminal (3
3) to the base of the transistor (29) of the interface circuit (34).

The pulse width T2 at which the control signal becomes a high level "1" means that the control signal KE (an inverted signal of KE, shown in FIG. 4B) is a low level "0" in order to output the confirmation signal ACK. The pulse width T1 is set to be wider than the pulse width T1 when the confirmation signal A CK is generated.

According to the example in FIG. 3, in synchronization with the 9th pulse of the serial clock SCL, the control signal that becomes high level "1" from the confirmation signal output terminal AK for a pulse width T 2 is the transistor (29). Since this transistor (29) is conductive, the resistor (26) in the interface circuit (34) is supplied to the base of the interface circuit (34) only during the pulse width T2.
The connection point between and (27) is forcibly set to high level "l". Therefore, as shown in FIG. 4, the pulse width T2
The processing circuit (32
) becomes high level "l" (inverted signal KE is shown in Figure 4), and even if an attempt is made to output the confirmation signal ACK, the confirmation signal ACKm will be as shown by the broken line in Figure 4. It is not directly output as an acknowledgment signal ACK on the data line (2).

In this way, also in the tC circuit network shown in the example in FIG. 3, the confirmation signal AC is sent from the monitor device (31) to the data line (2).
K is not output, and the states of the bus lines (1) and (2) can be monitored without causing a bus line error. In addition, in the example shown in FIG. 3, the sending of data from the monitor device (31) to the data line (2) is prevented only at the timing of outputting the confirmation signal ACK, and in other states, the monitor device (31) Since data can be freely sent to the data line (2) from the monitor device (
31) onto its data line (2).

A fourth embodiment of the present invention will be described with reference to FIG. In the example shown in FIG. 5, the present invention is applied to a so-called multi-mask circuit having a plurality of microcomputers.

In FIG. 5, a memory (38), a microcomputer A (CPU-A) (35),
CPU-B (36) and CPU-C (37) are connected in parallel, and between the SDA terminal (36A) for serial data input/output of CPU-B (36) and the data line (2). connects the interface circuit (39), and connects the interface circuit (4) between the SDA terminal (37A) of the CPU-C (37) and the data line (2).
0). These microcomputers (35)
, (36) and (37) are R for program storage.
It includes a buffer circuit for input/output with the OM and external equipment (not shown).

Also, those interface circuits (39), (40)
have the same configuration as the interface (34) in the example in FIG. 3, and the CPU-B (36) and CPU-C
A control signal for switching these interface circuits (39) or (40) from bidirectional to unidirectional is supplied from (37) via a lead wire (not shown).

According to the example in FIG. 5, for example, the data in the memory (38) is
PU-A (35), CPU-B (36) and CPU-C
(37), send data from that memory (38) to that data line (2) by - degrees,
The data on that data line (2) is transferred to those CPU-A
(35), CPU-B (36) and CPU-C (
37) should be taken in at the same time. in this case,
Since the acknowledgment signal ACK is sent from the CPU-A (35) onto the data line (2), the Memo'J (38) can confirm that the data has been received, and the CPU-A
The confirmation signals ACK from -B (36) and CPU-C (37) are sent to the interface circuits (39) and (40), respectively.
This prevents bus line errors from occurring.

As described above, according to the example shown in FIG. 5, it is possible to perform substantially one-to-three communication, and there is an advantage that the data transfer efficiency is tripled.

Although the above-mentioned embodiment shows an example in which the present invention is applied to a circuit network using a two-wire bus line consisting of a clock line and a data line, the present invention is not limited to this. The present invention can be applied to any circuit network in which a plurality of circuits capable of data communication are connected to each other and a confirmation signal is sent back when data is received. Further, by applying the present invention to a television receiver, for example, it becomes possible to make adjustments by connecting the television receiver in a subordinate manner during assembly adjustment at a factory.

As described above, the present invention is not limited to the above-described embodiments, and it goes without saying that various configurations can be adopted without departing from the gist of the present invention.

〔Effect of the invention〕

An IC network connected by a bus line according to the invention is provided with circuit means between any one of the plurality of ICs and a data line to prevent an acknowledgment signal from being applied to that data line. Since the confirmation signal is not output from that certain IC on that data line,
Sending data simultaneously from one IC among the plurality of ICs to the plurality of ICs including the certain IC via the data line without generating a bus line error f
There are profits that can be made.

This also means that according to the present invention, communication between one IC and multiple ICs can be easily achieved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of an IC circuit network connected by a bus line according to the present invention, FIG. 2 is a block diagram showing main parts of a second embodiment of the present invention, and FIG. FIG. 4 is a timing chart for explaining the operation of the example in FIG. 3; FIG. 5 is a configuration diagram showing the fourth embodiment of the invention; FIG. 6 and 7 are diagrams for explaining conventional IC circuit networks. (1) is the clock line, (2) is the data line, (6
) is a micro combi coater (CPU), (14) is a memory, (16) is a keyboard IC, (20) is a monitor device, (22) is an interface circuit, (23)
is a buffer circuit, and (24) is a resistor. Deputy person Sadomatsu Ito Hide Mori 1 Figure 3 Figure 2 Figure 5 Figure 1

Claims (1)

[Claims] A plurality of ICs are connected in parallel to a data line and a clock line, data is sent from one of the plurality of ICs to the other IC via the data line, and the other IC is connected to the data line and the clock line.
In an IC circuit network connected by a bus line configured to send a confirmation signal from the plurality of ICs back to the one IC via the data line, the An IC network connected by a bus line, characterized in that it is provided with circuit means for preventing an acknowledgment signal from being applied to said data line.