JPH02166849A - data extraction circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention concentrates terminal elements such as sensors and actuators used in various industrial machines (press machines, NC machine tools, robots, etc.) and automatic guided vehicles. The present invention relates to a data extraction circuit that is employed in a controlling control device, various data processing devices, etc., and extracts desired data change history.

[Conventional technology]

The above control devices include, for example, a large number of node controllers that directly extract output from data input terminals (sensors) or output signals to data output terminals (actuators), and a main controller that centrally manages these node controllers. There is a serial control device that divides the terminals and connects these node controllers and main controllers in series to realize centralized management of each terminal.

For details of such a series control device, for example, the name of the invention in Japanese Patent Application No. 120337/1988 "Series Control Device" and the name of the invention in Japanese Patent Application No. 120338/1982 "
``Series Control Device'', and furthermore, the title of the invention in Patent Application No. 1983-209868 is ``Series Control Device'', Patent Application No. 1983-237263.
As is clear from the title of the invention, ``Series Control Device,'' etc., in particular, this configuration uses two signal lines, the first and second, to connect each of the above-mentioned node controllers (hereinafter simply referred to as nodes) and the main controller. FIG. 6 shows a schematic diagram of a double loop connected in series.

That is, in the series control device shown in FIG. 6, if the control device is applied to a press machine, the main controller 100 is provided in the controller section of the press, and the sensor groups 1-1 to 1-n are connected to the press machine. Actuator groups 2-1 to 2-2 correspond to sensors that detect the status of each part.
- n corresponds to various actuators that drive each part of the press.

Sensor group 1-1 and actuator group 2-1 are connected to node 10-1, sensor group 1-2 and actuator group 2-2 are connected to node 10-2, and sensor group 1
-3 and actuator group 2-3 are connected to node 10-3, and similarly sensor group 1-n and actuator group 2-n are connected to node 10-n. In addition, the nodes 10-1 to 10-n and the main controller 10
0 is connected in series through two loops, Loop E and Loop ■. These loops ■ and ■ are not given priority as primary or secondary.

In such a configuration, the main controller 100 controls the sensor group 1-1 connected to each node 10-1 to 10-n.
~1-n detection signals (sensor data) are collected, and drive data is sequentially sent to actuator groups 2-1 to 2-n connected to each node 10-1 to 10-n. For this purpose, for example, a signal having a frame structure as shown in FIG. 7 is used.

That is, frame signals (frame SOI and SOI
[), and these frame signals are transmitted through each loop to "node 101→node 10-2→...-node 1".
0-n→main controller 100'', the sensor group data DI to be managed by each node is incorporated into the frame signal, and the data assigned in advance to the frame signal through the main controller 100 is Distribution of the actuator drive data DO to each corresponding node is realized. As a result, when the above-mentioned frame signals emitted from the main controller 100 as frames SOI and SO■ are returned to the main controller 100 as frames SnI and 5nII, the above-mentioned actuator drive data collectively loaded in the frame signals are D
All sensor data DI of all the sensors to be managed are allocated to each corresponding node, and the sensor data DI of all the sensors to be managed are incorporated into the same frame signal through each corresponding node. During this time, each node constantly captures the sensor outputs of the sensor groups to be managed, and each time the frame signal arrives, the captured sensor outputs are used as data in a predetermined format in the predetermined format of the frame signal. For the actuator group, each time the same frame signal arrives, the drive data related to the actuator group included in the predetermined position is extracted at a predetermined timing, and this is converted into a predetermined actuator drive signal. Then, the drive of each corresponding actuator is actually controlled.

Note that in each frame signal shown in FIG.
, is an input data start code that is added in advance from the main controller 100 to the same frame as a bit string with a predetermined logical structure in order to indicate the start position of input data (sensor data) DI, and rsTo is ,
In order to indicate the start position of the output data (actuator drive data) DO, the main controller 10 uses a bit string having a predetermined logical structure 3 different from the above rSTI.
0 is a start code for output data that is added to the same frame in advance, and "SP" is the above-mentioned rSTl, Or rsT
rDL is a stop code that is added in advance to the same frame from the main controller 100 as a bit string with a predetermined logical structure that is further different from rDL. rSTI, No. 1! is data length data that is added to the same frame each time in the main controller 100 and each node in order to instruct the next stage node or the main controller 100 about the data length from the end part to the rear end part of the rsPJ, rCRC is also one of the data for error checking, and is an error value that is added to the same frame each time in the main controller 100 and each node in order to perform a well-known CRC check (cyclic redundancy check) on each of the above data strings. This is a check code (CRC code), and each node and the main controller 100 exchange the previous data DI and DO with each frame signal based on the detection of rsTI, 5TOJ and rsp. , and also checks whether a data transmission error has occurred by referring to the above rDLJ and rCRC.
This is an error code that is added when a data transmission error is detected during such an error check.
Normally, various error contents can be expressed depending on the code contents, but here, for example, the error contents detected according to the error check using the above-mentioned rDLJ and rcRcJ are expressed. The example shown in FIG. 7 shows that some data transmission error has occurred in the loop (2) between the node 10-1 and the node 10-2.

In such a series control device, the relevant data extraction circuit is disposed in the actuator drive data (data Do) extraction section in each node or in the sensor data (data DI) extraction section in the main controller 100, for example, loop I and The change history of each desired data is extracted based on the comparison of data (included in the frame signal) regarding each same terminal that is periodically and repeatedly transmitted via the respective terminals.

In addition, in FIG. 6, the configuration of the series control device is as follows.
For convenience of illustration, <a> All nodes connected in series to the main controller jointly manage both the sensor group and the actuator group.

Although only the configuration is shown, <b> a first type node that manages both the sensor group and the actuator group, a second type node that manages only the sensor group, and a second type node that manages only the actuator group. At least two types of nodes of the third type of nodes, and the third type of nodes, are connected in series to the main controller in a mixed manner.

<C> All nodes connected in series to the main controller manage only sensor groups.

<d> All nodes connected in series to the main controller manage only actuator groups.

<e> In the case where all the nodes connected in series to the main controller manage only the actuator group, the n-th node 10-n at the final stage and the main controller 100 are separated, and the series is connected in a so-called daisy chain. It becomes a connection.

<f> This is a case where all the nodes connected in series to the main controller manage only the sensor group, and the main controller 100 and the first node 10-1 are separated, forming a so-called daisy chain series connection. However, in this case, the leading node 10-1 also has the function of periodically generating the frame signal.

The configuration etc. may be adopted as appropriate depending on the actual situation of the machine to which it is applied.

Furthermore, in the above, in a more general manner, sensors or actuators are divided into several groups and managed by each node as a group, but each of these sensors or actuators is managed individually by one node. There are things that are done.

Furthermore, the structure of the frame signal shown in FIG. 7 is only one example, and in reality, frame signals with various structures based on various protocols are employed.

The key point of these frame signals is to change the state (contents) of these data at a predetermined high frequency so that the data extraction circuit can clearly extract the change history of desired data such as the sensor data and actuator drive data. It is sufficient if the information can be transmitted repeatedly.

[Problems to be Solved by the Invention] As in the above example, connecting each node and the main controller in series in a double loop using two signal lines prevents system failure in the event of loop breakage. In particular, as mentioned above, it is effective as a backup measure for the first and second loops, without setting a priority order of primary and secondary for each loop, and transmitting data to each of these loops equally. If the change history is extracted based on matching data from the same data source, the reliability of the extracted data will be further increased.

However, on the other hand, in such a dual system, due to subtle timing discrepancies, the data content in both systems may differ even though no data error has occurred, or data may be stored in only one system. When an error occurs, or even when one system returns to a normal state from a disconnection state, it is difficult to judge which system's data should be extracted as the true data. The unavoidable inconvenience is that even though data can be extracted with high reliability during normal times, when some kind of abnormality occurs, the reliability of that data rapidly declines.

This situation is not limited to the above-mentioned serial control device, but also applies to data processing devices using Ike's double loop, as in Omiya.

This invention has been made in view of these circumstances, and as mentioned above, the first and second data are generated from the same data source.
The circuit that extracts the change history based on the matching of the data that is periodically and repeatedly transmitted through the two signal lines, respectively, is specifically targeted, and if there is any abnormality in the above two systems or either system. An object of the present invention is to provide a data extraction circuit that can extract the true change history of the data with high reliability even in such cases.

[Means to solve the problem]

In this invention, for data transmitted via the first signal line, the latest data is latched in the first signal line.
a new data latch means, and a first old data latch means in which, after new data is latched in the first new data latch means, the data latched in the first new data latch means is separately latched as old data. data latch means;
Regarding the data transmitted via the signal line, a second new data latch means latches the latest data each time, and after new data is latched in this second new data latch means, the latest data is latched each time. a second old data latch means in which the data latched by the second new data latch means is separately latched as old data; and the data latched by the first new data latch means and the first old data latch means. a first comparison means for comparing the data latched in the second data latch means, and a second comparison means for comparing the data latched in the second new data latch means and the data latched in the second old data latch means. a comparing means, a third comparing means for comparing the data latched by the first new data latch means and the data latched by the second new data latch means, each time the third comparing means 2, when the comparison results of at least one of the first and second comparison means match corresponding to a predetermined number of data, the matching data is set as true. and determining means for determining the data and extracting and outputting the data.

[Effect]

With the above configuration, and especially with the arrangement of the determination means, (a) unless the data latched simultaneously in two systems match at least the contents (the comparison results by the third comparison means match), It is never captured as real data.

(b) Even if the contents in these two systems match, unless the same contents are maintained a predetermined number of times in each system, this will not be taken in as true data.

(c) The conditions in (a) and (b) above to be taken as true data do not need to be satisfied in both systems, but as long as they are satisfied in either one of them. As soon as this condition is satisfied, the data of this corresponding system will be immediately taken in (extracted and output).

Arrangements for data extraction will be made. In other words, this fact is actually incorporated (extracted) even in many cases that are generally considered unstable.
The reliability of the data will be maintained (by setting the conditions (a) and (b) above), and for example, the
This makes it possible to achieve data extraction on a case-by-case basis with far greater stability than if the conditions of
(according to the condition setting in (c) above)).

In addition to this, after the condition (c) above is satisfied, the determination means includes a means for forcibly initializing the condition (b) above not only for the corresponding system but also for the other system. By combining this with the system, even if one system returns to a normal state from a disconnected state, the reliability of the extracted data can be maintained well, and furthermore, , when it is clear that the cause of the failure of condition (a) above is in the other party's system (for example, when a data transmission error, etc. is detected in the other party's system),
If the determination means is also provided with a means for forcibly canceling the condition (a), even faster data extraction using these two systems can be realized.

Note that data extraction in this manner is performed on the premise that (data transmission period) Needless to say.

〔Example〕

1 to 5 show an embodiment of a data extraction circuit according to the present invention.

This embodiment is installed in the main controller 100 of the series control device as shown in FIG. 6 above, and extracts sensor data collected through each node. The data extraction circuit according to the present invention is applied to a circuit that outputs each data change history to a target control unit such as a press controller. In other words, in Figure 1, the loop ■
and loop ■ respectively indicate the two loops shown in FIG.
0 signal input lines).

As shown in FIG. 1, this embodiment circuit includes a loop I processing circuit 10 for processing a frame signal transmitted to the loop (2) based on a predetermined rule;
A loop ■processing circuit 2 for processing the frame signal transmitted to the above loop ■ based on a predetermined rule.
0, and an extraction processing circuit 30 for extracting the change history based on the data extracted from each frame signal by the loop I processing circuit 10 and the loop II processing circuit 20. It is composed of

Of these, the loop I processing circuit 10 and the loop II processing circuit 20 each process a modulation signal (for example, a CMI signal) of a frame signal as shown in FIG. A frame signal consisting of so-called NRZ and data having a period synchronized with each unit bit period are input. The data input demodulation circuits 11 and 21 demodulate to the clock DCK, and sensor data (which is loaded and inputted into each frame signal) is input based on the pre-switch settings or the pre-acceptance registration operation of sensor number information from each node. In the following, for convenience, the data number holding circuits 12 and 22, which store and hold the number 1 per sensor, and the frame signal demodulated by the demodulation circuit 11 or 21, respectively, obtain the input data start code rsTIJ. STI detection circuit 13 to detect
and 23, by the detection signal A1 or A2 from these STI detection circuits 13 or 23 (switch Sll
or by turning on S21), reads the stored data B1 or B2 of the data number holding circuit 12 or 22 as a preset value, and thereafter counts down in order from this read value based on the demodulated data clock DCK. Down counters 14 and 24 that operate, SP detection circuits 15 and 25 that detect the stop code rsPJ from one frame word demodulated by the demodulation circuit 11 or 21, and detection signals from these SP detection circuits 15 or 25. First delay circuits 16a and 26a that delay output by the number of bits from the rsPJ end of the frame signal to the error check code rcRc and the end, and delayed outputs F1 or F by these first delay circuits 16a or 26a, respectively.
2 and the number of bits of the error code rERRJ, that is, the error code rBRR of each frame signal.
, the second delay circuits 16b and 26b delay the output by the number of bits up to the end (frame end) taking into account the frame signal (this delayed output becomes the frame end signal FE1 or FB2). ), and for example, in this case, after the arrival of a certain frame signal, (transmission time for one frame signal) + (time for frame interval) + (one frame signal) transmission time)
+ (time required for half the frame interval) when the next frame signal does not arrive,
A disconnection detection circuit 17 that determines that each corresponding loop is disconnected and outputs a disconnection detection signal BRI or BH3.
and 27, from the generation of the detection signal A1 or A2 by the STI detection circuit 13 or 23 to the generation of the delayed output F1 or F2 by the first delay circuit 16a or 26a (switch S12 or S22
is in the on state), each corresponding frame signal (precisely its rDIJ , rsTOJ , rsp, . . . ).

Error check circuits 18 and 28 take in the error code (rDLJ and rCRC) and check whether a transmission error has occurred. Error code detection circuits 19 and 29 that detect the presence or absence of a history, and the disconnection detection port #117
Alternatively, the OR signal of the disconnection detection signal BRI or BH3 outputted from the circuit 27, the error detection output from the error check circuit 18 or 28, and the error code detection output from the error code detection circuit 19 or 29 is used as the abnormality detection signal EBI. Alternatively, it is configured with OR circuits 0RIO and 0R20 that output as EB2, and is a circuit portion that functions as a circuit for forming a timing signal or a processing condition signal for the extraction processing circuit F430, which will be described below.

Further, the extraction processing circuit 30 includes the loop I processing circuit 10.
The period from the time when the detection signal A1 is generated by the STI detection circuit 13 of the same loop until the time when the borrow signal C1 is generated by the down counter 14 of the same loop I processing circuit 10 (switch 31
4 is in the on state), all data (sensor data DI) included in the demodulated frame signal regarding loop I is taken in through the data input demodulation circuit 11, and is latched (- time memory) based on the data clock DCK. )
When the detection signal A2 is generated by the STI detection circuit 23 of the loop processing circuit 20, the down counter 1 of the loop processing circuit 20 is activated.
4 until the borrow signal C2 is generated (switch S
24 is in the on state), all the data (sensor data DI) included in the frame signal regarding the demodulated loop 2 is taken in through the data input demodulation circuit 21, and is similarly latched (at - time) based on the data clock DCK. A first data latch 32a for loop (2) to store), a first data latch 31 for loop I or loop (2)
In this embodiment, the data latched in a or 32a is transmitted to the determination circuit 36, which will be described later, especially during a period when the transfer permission signal n1 or n2, which will be described later, is active (on).
Provided that write permission is granted through
Second data latches 31b and 32b for Louve and loop 2 to be relatched, the loop I processing circuit 1
0 and loop ■ Frame end signals FEI and FE2 formed through the processing circuit 20 (second delay circuit 1
6b and 26b outputs), borrow signals C1 and C2
(outputs of down counters 14 and 24), disconnection detection signals BR1 and BH3 (outputs of 1!Ii line detection circuits 17 and 27), respectively, the first data latch 31a
Or from 32a to second data latch 31b or 3
Transfer permission signals n1 and n for permitting data transfer to 2b (turning on switches S31 and S32)
2 (however, in this embodiment, the actual data transfer is completed only after a write permission signal is output from the determination circuit 36, which will be described later, during this permission period); Data latch 31
Generates a tally signal W (assuming a tally signal with a higher frequency than the data clock DCK) for determining the processing timing (processing speed) of the extraction processing circuit 3014C, including the data writing timing to data clocks DCK and 32b. When the switch S35 is turned on by the transfer permission signal n1 or B2 via the OR circuit 0R32, the write tally generating circuit 34 starts counting operation based on the clock signal W, and starts the counting operation based on the clock signal W.
Data latch 31a and 32a, second data latch 3
1b and 32b, respectively of the determination circuit 36 described above, and their output count values to be used as address signals AD and OR times fI? Data number information value B1 or B2 (data number holding circuit 12 or 22
(stored information), that is, the output of the exclusive OR circuit (digital comparator) EOR34 becomes logic "0".
The address counter 35, which is reset at the next rising timing of the clock signal W, completes the counting process and resets the data latched in the first data latch 31a for the Loop I. A first exclusive OR circuit EOR31 compares the data latched in the second data latch 31b with respect to data related to the same address signal, that is, data related to the same sensor (each 1-bit data); The data latched in the data latch 32a is compared with the data latched in the second data latch 32b for loop (2), which are related to the same address signal, that is, data related to the same sensor (each 1-bit data). Or time 1?1
EOR32, first data latch 31a for the above Rogue I
A third exclusive operation is performed to compare the data latched in the first data latch 32a and the data launched in the first data latch 32a for the loop (2), which are related to the same address signal, that is, data (each 1-bit data) separated by the same sensor. target OR circuit 11EOR33, each comparison output of these first to third exclusive OR circuits EOR31 to EOR33, and the above-mentioned loop 1 processing circuit #110 or loop ■processing circuit 20
Based on the abnormality detection signal EBI or EB2 from the sensor, it is determined whether the data for each sensor latched in the second data latches 31b and 32b is true or false, and only the data determined to be true is transmitted to its corresponding data. During the period when the address is specified, switch S33 or S3
4, the second data latch 31b or 32b
and an OR circuit OR31 that outputs the OR output of the output data to the data processing/control circuit (for example, press controller) 40 as extracted data by the data extraction circuit of the embodiment.
These are the circuit parts constituting the main part of the data extraction circuit of the embodiment, each of which includes the following.

In the data processing/control circuit 40, the address signal AD
(and tarok signal W), the above OR circuit OR
For example, as data for this control, the main The above-mentioned actuator drive data Do (see FIG. 7) is included in the frame signal emitted from the controller 100 and distributed to each node.
is used.

2 and 3 show the transfer timing generation circuit 33 and determination circuit 3 in the extraction processing circuit 30.
This figure shows each of the 6 ingredients # configuration examples, and the 4th
The figure is a timing chart showing an outline of the operation of the circuit according to the embodiment, taking Loop I as an example. The configuration and operation related to data determination processing will be explained in further detail.

First, details of the transfer timing generation circuit 33 shown in FIG. 2 will be explained.

This circuit 33 is connected to the loop I processing circuit 10 as described above.
and frame end signals FEZ and FE2, which are the outputs of the second delay circuits 16b and 26b, borrow signals C1 and C2, which are so-called counting end outputs of the down counters 14 and 24, from the loop processing circuit 20, respectively;
Then, the disconnection detection signals BRI and BH3, which are the outputs of the disconnection detection circuits 17 and 27, are received, and the signals are switched from the first data latch 31a or 32a to the second data latch 31, respectively.
This is a circuit that forms and outputs transfer permission signals n1 and B2 to permit data transfer (re-latching) to b or 32b.The mechanism by which these transfer permission signals n1 and B2 are formed is as follows. It has become.

That is, suppose that the borrow signal C1 is output from the down counter 14 of the loop I processing circuit 10 in the relationships shown in FIG. 4 [a], (b), (c), and (f) (at this point , writing of the data (column) DI included in the frame signal that has arrived via the looper to the first data latch 31a has been completed (see ff) and fi) in Figure 4), the flip-flop FF 301 is set, and this set AND circuit AD301 by output
becomes active. The frame end signal FBI from the second delay circuit 16b (signal indicating passage of the end position taking into account the error code rERR of the frame signal that has arrived via the looper: see FIGS. 4(a) and (0)) is as follows: In this state, the signal is input to the OR circuit 0R301. Therefore, with the input of the frame end signal FEZ, the logical product condition of the AND circuit AD301 is satisfied, and the logical product output (logic level "1") is latched in the flip-flop FF302. This AND output continues to be latched through the loop of the Q output of , the OR circuit 0R301, and the AND circuit AD301. Furthermore, this flip-flop F
The clock SCK applied to the clock terminal of F302 is assumed to be a system clock having a frequency of several MH2.

On the other hand, regarding loop H, which is not shown in the timing chart of FIG.
303 is set, and this set signal and the second delay circuit 2
The AND circuit AD302 outputs an AND signal (logic level "1") with the frame end signal FE2 applied from 6 through the OR circuit 0R302 to the flip-flop F
It is latched to F304 and continues to be latched.

Then, in both flip-flops FF302 and FF304 related to loops I and (2), the logic level "1" signal is latched, and by continuing to be latched, AND circuits AD303 and AD3
As long as the above-mentioned latched state continues, these AND circuits AD303 and A
D304 outputs the AND signal (logic level "1") as the transfer permission signals n1 and B2 via OR circuits 0R303 and 0R304, respectively (see FIG. 4(j)). Transfer permission signals n1 and B2 are sent to switches S31 and S, respectively.
32 is turned on, the first data latch 31a or 3
Allow data transfer from 2a to the second data launch 31b or 32b (make data transfer possible)
As mentioned above, it works in this way.

Furthermore, as described above, these transfer permission signals n1 and B2 also turn on the switch S35, thereby starting up the address counter 35 (Figs. 1 and 4 (j
) and (k)).

The activated address counter 35 starts counting based on the tarock signal W generated from the write clock generation circuit 34, as described above, and receives the address signal AD.
The output of the exclusive OR circuit EOR34 (logic level "0") when the output count value matches the data number information value B1 or B2 (in the example of FIG. 4, the number of data is set to 4 for convenience). (see FIG. 4 fk)), the output signal E of the exclusive OR circuit EOR 34, which essentially acts as an active signal (enable signal) for the address counter 35.
also acts as one of the active signals for the transfer timing generation circuit 33 in question.

That is, as shown in FIGS. 1 and 2, this circuit 33 receives the output signal E of the exclusive OR circuit EOR34.
is received by each reset terminal R (which serves as a logic inversion input) of flip-flops FF301 and FF303, and based on the switching of the signal E from the logic "1" level to the logic "0" level, The above-described loop for sustaining the latch of the flip-flops FF302 and FF304 is cut off.Therefore, the above-mentioned transfer permission signals n1 and n2 outputted from the transfer timing generation circuit 33 are transmitted to the address counter 3.
Approximately in synchronization with the end of the counting operation in step 5, the inactive level (logic “
0” level) (Fig. 4 Fk
) and fj)).

By the way, the above operation of the transfer timing generation circuit 33 is based on the assumption that loops ■ and ■ are both normal and the frame signal is reliably transmitted to both loops, but if, for example, there is a break in loop ■, If this occurs and the frame signal no longer arrives on the loop (2) side, the circuit 33 operates in the following manner.

That is, in this case, since loop IIPI is normal, in response to the arrival of the frame signal via loop I,
Although the flip-flop FF302 latches the logic "1" level signal as described above, the logic "1" level signal is not latched in the flip-flop FF304 corresponding to the loop (2) side (borrow signal C2 and frame end signal FB2 does not occur).

In this case, the disconnection detection circuit 27 on the loop (2) side, based on the above-mentioned function, receives the first frame signal shown in FIG. 4(a), for example, at the timing shown by the broken line in FIG. Assuming that a disconnection occurs in the loop (2) after the frame signal one before the previous one arrives, approximately half of the time corresponding to the interval between this first frame signal and the next frame signal in terms of the loop (2). A disconnection detection signal BR2 is output at a timing corresponding to the time.

As a result, in the transfer timing generation circuit 33, from the time when the disconnection detection signal BR2 is output, the AND circuit A
The logical AND condition of D305 is satisfied, and the AND circuit AD305 outputs the transfer permission signal n1 as the transfer permission signal n1.
The AND signal (logic level "1'") is the OR circuit 0R
303 (see the broken line diagrams in FIGS. 4(g) and (j)), the operation for resetting the transfer permission signal n1 is the same as in the previous example.

In this way, the transfer timing generation circuit 33 shown in FIG.
According to the above, even if one loop is disconnected, a transfer permission signal for the other normal loop is output.

Also, when it comes to normal loops, in any case,
The transfer permission signal will be output before the next frame signal arrives.

Next, details of the determination circuit 36 shown in FIG. 3 will be explained.

As described above, this judgment circuit 36 receives the comparison outputs of the first to third exhaustive OR circuits EOR31 to EOR33, as well as the abnormality detection signal EBI or EB2 from the loop processing circuit 10 or the loop processing circuit 20. Based on this, the sensor-specific data latched in each of the second data latches 31b and 32b is determined to be true or false, and only the data determined to be true is sent to the switch 333 during the period in which its corresponding address is specified. Alternatively, the circuit outputs the data from the second data latch 31b or 32b through S34.The mechanism by which these data decisions are made is as follows.

Now, data latching to each of the first data latches 31a and 32a regarding a certain incoming frame signal in both loops ① and ② has been completed.
(i)) and based on the transfer permission signals n1 and n2 output from the transfer timing generation circuit 33, the switches 531 and 332 are turned on, and the address counter 35 performs the count (address designation) of the address signal AD. (See Figure 4 Fk)
, First, in response to the designation of address "1 (count value 1)" by this address signal AD, the first exclusive OR circuit EOR
31 is the data (first sensor data Di) stored at address "1" of the first data latch 31a and the data (first sensor data) previously stored at address "1" of the second data latch 31b. The second exclusive OR circuit EOR32 compares the data (data DI) of the first sensor with the data DI of the first sensor and outputs the comparison result. and the data (first sensor data DI) stored up to that point in the address "1" of the second data latch 32b. Compare the data stored at address "1" of the data launcher 31a (first sensor data DI) and the data stored at address "1" of the first data launch 32a (first sensor data DI>) The comparison results are outputted to the determination circuit 36, respectively.

Here, in the determination circuit 36, the comparison output of the third exclusive OR circuit EOR33 is determined by the AND circuit AD6.
(A) the abnormality detection signal EBI and EB2 are not output, and if the comparison output (comparison output of the third exclusive OR circuit i?-3E OR33) is at logic "0" level (comparison result = same content), AND circuit AD6
03 to AD606 are all activated.

(B) If neither of the abnormality detection signals EBI and EB2 is output, and the comparison output is at logic "1" level (comparison result = different content), AND circuit AD6
03 to AD606 are all inactive.

(C) Even if the comparison output is at the logic "1" level (ratio 12 result - different contents), if the abnormality detection signal EB2 is output from the loop ■ side, the AND circuits AD603 and AD605 on the loop E side will be With this active, the AND circuit AD604 and AD on the loop ■ side
606 is inactive.

CD) Even if the comparison output is a logic “1” level (comparison result = different content), the abnormality detection signal E is output from the loop 1 side.
If BI is output, the AND circuit AD on the loop ■ side
604 and AD606 are activated, and the AND circuits AD603 and AD605 on the loop ■ side
This is set to be inactive.

(E) When both the abnormality detection signals EBI and EB2 are output, all AND circuits AD603 to AD606 are rendered inactive, regardless of the comparison output.

Five types of logic are set, and further combination conditions of these five types of logic and the comparison result by the first exclusive OR circuit EOR31 or the comparison result by the second exclusive OR circuit EOR32 are set. Accordingly, the data determination movement t described below is controlled.

For example, on the loop-e side, AND circuit AD6
03 and AD605 are placed in an inactive state (B
), (D), and (E), under the conditions (A) and (C) above, in which the AND circuits AD603 and AD605 are active, the first
According to the comparison output of the exclusive OR circuit EOR31, (I-1) If this comparison output is at the logic "0" level (comparison result = same content), the AND circuit AD603 becomes inactive (logical product logic). The AND circuit (NOR circuit) AD605 satisfies the AND condition (AND output = logic "1" level).

(I-2) If this comparison output is at logic “1” level (comparison result = different content), the AND circuit AD603 meets the AND condition, and the AND circuit (NOR output = logic “1” level). (Circuit) AD605 becomes inactive (logical product logic "0" level).

Control is executed in such a manner. Here, the fact that the AND circuit 1iAD603 is controlled to be inactive means that the AND circuit AD615 in the determination circuit 36 is kept inactive, and the “1” generated from the “1” data generation circuit 65 is Launching of data to the count number latch 67 is prohibited, and the AND circuit AD31 (FIG. 1) functioning as a write mask gate of the second data latch 31b is also kept inactive, and the second data latch 31b is
The fact that data writing (latching) is prohibited and, conversely, the AND condition of the AND circuit AD603 is satisfied means that the AND circuit AD615 is controlled to be active, and "1" is output from the data generation circuit 65. The generated “1” data is sent to count number latch 6 via OR circuit 0R603.
7 is written to the specified address by the address signal AD (provided that the AND circuit AD613 is in the active state), and the AND circuit AD31 (FIG. 1) is also controlled to be in the active state (this is the write enable signal mentioned above). ) means that data writing to the second data latch 31b based on the clock signal W is executed.

The second data latch 31b latches the data transferred from the first data latch 31a at the rising timing of the output of the AND circuit AD31. In addition, the above AND circuit (NOR circuit) A
The fact that the AND condition of D605 is satisfied means that AND circuits AD607 and AD611 in the determination circuit 36 are satisfied.
are both controlled to be active, and the count number data at the specified address (address "1") read from the count number latch 67 is incremented by "1" through the "+1" adder 63, and the new data is added. It is rewritten as count number data to the same specified address of the same count number latch 67 (however, when the AND circuits AD609 and AD613 are in the active state), and conversely, the same AND circuit (NOR circuit) AD6
05 is controlled to be inactive, which means that the AND circuits AD607 and AD611 are kept inactive, and the specified address (address "1") with a count of 1,000 and 67 is controlled.
Each means that updating of count data is prohibited. This control of the determination circuit 36 is carried out in exactly the same manner as above for the loop 1■ side to which the comparison output of the second exhaustive OR circuit EOR32 is input, although separately from the loop l1llll. Implemented.

In addition, in this judgment circuit 36, exclusive OR circuits (digital comparators) EOR603 and EOR604 receive the count number data (AND circuit AD607 or AD608) updated via the +IJ adder 63 or 64 on the loop ■ or ■ side, respectively. output) and a certain arbitrary count number N preset in the count number setting device 60
When these data are equal, that is, when the update count number on each corresponding side reaches the set count number N, the comparison output (logic "O" level signal) With this, the switch 33
3 or 534 (FIG. 1), and in the case of the exclusive OR circuit EOR603 on the loop I side, both the AND circuit AD 609 and the AND circuit AD614 on the other loop ■ side are made inactive, In the case of the exclusive OR circuit EOR604 on the loop ■ side, the AND circuit AD61
0 and the other AND circuit AD613 on the Rougue side are both inactive. When the switch 333 or S34 is turned on, the data at the address currently specified by the address signal AD is transferred from the corresponding side of the second data latch 31b or 32b.
As described above, the signal is output to the data processing/control circuit 40 via the OR circuit 0R31 (FIG. 1). In addition, the AND circuit AD609 or AD
613 being controlled inactive means that the count number "0" (initial value) is written to the address specified by the address signal AD of the count number latch lo 7 on the loop ■ side. , the above AND circuit A
Controlling D610 or AD614 inactive means that the count number "0" is written to the address specified by the address signal AD of the count number latch 68 on the loop (2) side.

As is clear from the above, the operational logic of the determination circuit 36 shown in FIG. 3, for example with respect to loop (2), is summarized as follows, listed in descending order of the 0 condition.

(1) When an abnormality is detected in the own loop ■ (when the abnormality detection signal EBI is output), and the data latched in the first data latch 31a of the own loop ■ and the data latched in the first data latch 31a of the other loop ■ 1 data latch 32a
If the contents differ from the data latched in (however,
(except when its own loop I is normal and the abnormality detection signal EB2 is output from the other loop ■), the first
Neither the data latched in the data latch 31a is latched into the second data latch 31b nor the count latched in the count latch 67 is updated.

(2) If the count latched in the count holder 67 is "0" and data is latched to the first data latch 31a, the count is divided by 'IJ('÷
(including IJ).

(3) When the count number latched in the count number latch 67 is other than "OJ", if data different from the data latched in the second data latch 31b is latched in the first data latch 31a, The same count number is set to "1", and the data launched in the second data latch 31b is updated with the data latched in the first data latch 31a (the second data latch 3
1b).

(4) When data with the same content as the data latched in the second data latch 31b is latched in the first data latch 31a, the count number latched in the count number switch 67 is updated by "+1". .

(5) When the count number becomes the count number N preset in the count number setter 60 by updating the count number in the above (2), the data latched in the second data latch 31b is changed to the true value. Regarded as data, this is output to the data processing/control circuit 40, and both count number latches 67 and 68 set the latched count number to "0".

The determination operation based on such logic is repeatedly executed every time a frame signal arrives, with time-division processing for each target sensor, that is, with sequential scanning of specified addresses based on updates of the address signal AD.

Therefore, as in the example shown in FIG. 4, for example, when the first frame signal (see FIG. 4(a)) arrives, the target sensor data (data D1
- D4), if the state corresponds to the condition (2) or (3) above, the determination circuit 36 sets the count number latch 67 in response to the sequential update of the specified address of the address signal AD. Each latched count number is set to "1" (Fig. 4 (k) and (1) g
(see).

In particular, when the condition (3) above is met, the latched contents of the second data latch 31b are updated by the data latched in the first data latch 31a (FIG. 4 fk).
and (Q)9).

Next, the second # frame signal ■ in the diagram of FIG.
When the error code r is found in the frame (word), the error code r is searched (see FIG.
If it is detected that ERR is on the verge of being exceeded, an abnormality detection signal EBI (see FIG. 4(h)) is outputted through the loop processing circuit 10, so that the determination circuit 36
In this case, based on the logic in (1) above, the data content latched in the second data latch 31b at that point is maintained (see FIG. 4 [Q)I), and the count number latch is maintained at that point. The count number latched in 67 is maintained (see FIG. 4 (1) #).Although exact illustration is omitted in FIG. 1, the abnormality detection signal EBl or BH2 is
) is output with a certain time width that can cover at least the period during which the address signal AD is output, as shown in FIG. 4(h). This is, for example, an error detection output by the error check circuit 18 (or 28) (see FIG. 4(d) for the error check mode).
Alternatively, the above-mentioned error code detection output from the error code detection circuit 19 (or 29) may be extended for a predetermined time using a timer circuit or the like, or these detection outputs that have been kept output may be This is realized by resetting the "ST■" detection output AI (or A2> of the frame signal), etc.

Next, the third frame signal ■ shown in FIG. 4 arrives, and the data of each sensor included in this (data D1
-D4) all satisfy the condition (4) above, the determination circuit 36 calculates each count latched in the count latch 67 at that point based on the logic (4). The number "1" is updated by "+1j" in response to the address designation by the address signal AD. That is, each count becomes "2" (see FIG. 4 [k] to (1)).

Furthermore, the fourth frame signal ■ shown in FIG. 4 has arrived, and the data of each sensor (data D1 to D4) included therein all satisfy the condition (4) above. However, if the count number N preset in the count number setter 60 is "3", then the count number is updated based on the arrival of this frame signal (fourth
(See Figure (1)), the condition (5) above is now satisfied. Therefore, in this case, the determination circuit 36 uses the logic (5) to determine the data (data D1) that has been latched in the second data latch 31b.
~D4) are regarded as true data, and are sequentially outputted via the OR circuit 0R33 (see FIG. 4 (Ω) and (n)), and both the count number latches 67 and 68 Set the count number of the addresses (all in the case of the example in Figure 4) to "0" (Figure 4 (0
)reference).

Regarding the frame signals that arrive thereafter, data determination and extraction operations through the determination circuit 36 are repeatedly executed in a manner similar to the above.

Here, for convenience of explanation, the operation performed by the determination circuit 36 regarding loop I has been mainly illustrated, but it is to be understood that the above-mentioned operation of the determination circuit 36 is similarly executed regarding loop ■. Of course.

In order to further facilitate understanding of the operation of the data extraction circuit of this embodiment, FIG. For reference, examples of the transition of the data determination and extraction operations described above, which are performed each time a frame signal arrives, are listed below.

In FIG. 5, data rA'', each of which is 1-bit data, represents data at a logic level of 1 bit, and data rB represents data at a logic level of 0, for example. As shown in the remarks column of the figure,
In each latch data column, the symbol "xj" indicates that some data error has occurred (abnormality detection signal EBI or BH2 was output), and the symbol "XX" indicates that the corresponding loop has been disconnected. (Disconnection detection signal BH
1 or BH3) is output.

In this FIG. 5 as well, the operation transition is illustrated assuming that the count number N preset in the count number setting device 60 is "3", and the annotation symbol "
As shown in the part "*1", when the count number becomes "3" for either Loope or ■ (which happen to be both in the turn), the corresponding data "A" is The data is extracted as true data (output to the data processing/control circuit 40).

In addition, if different data is latched at the same time in loop I and loop ■, as in the part with the annotation symbol ": ni 2" in FIG. It is processed according to the logic in (1). That is, no processing is performed regarding data determination or extraction.

This occurs when an error occurs on the loop side ("
The same applies to the part marked *3).

In addition, the annotation symbol "*4" or r' in Fig. 5(a)
:'< 5 As in the part J, when the count number of either loop I or ■ becomes "3" and the corresponding data is extracted, the count number of the other loop is still "3". ”, both of these counts are reset to “0”. If this is the case where the count number is maintained without being reset on the side that has not reached the count number "3" (in the configuration example of FIG. 3, the AND circuit AD613 and °A
OR circuit 0R603 or 0 without D614
The output of R604 is directly connected to the count number latch 67 or 6.
8), as shown in FIG. 5(b), a break occurs in one of the loops, especially (break time) L (set count number N). And if this is restored, undesirable results will occur.

That is, as shown in the part marked with the annotation symbol "*7" in FIG. 5(b), for example, in loop I, a disconnection occurs when the count number is "2", and at this time, the other loop ■
In , the count number becomes "3", the corresponding data rB is extracted, and even though the count number is reset to "0", the count number of the broken loop I is "2". Assuming that it is maintained without being reset, the disconnection will be restored after that as shown in the part marked with the annotation symbol "*8" in Figure 5(b), and the data that has arrived at this time happens to be the data immediately before the disconnection. Latch data (data “
If the data (data "B") has the same content as "B"), the count number is updated to "3", even though the reliability of this incoming data (data "B") is still low. , this will be extracted as true data (*9).

In this respect, at least with this embodiment circuit having the operation logic shown as (5) above, the above-mentioned inconvenience does not occur, and all other transition results in FIG. ) to (5).

As explained above, according to the data extraction circuit of this embodiment, the data that is periodically and repeatedly transmitted through the double loops ① and ② can be maintained with high reliability under any circumstances. This makes it possible to extract with high efficiency by making full use of the characteristics of the double loop.

In this embodiment, the set count number N (value set in the count number setter 60) is a value that satisfies (data transmission period) x N < (data stabilization time: time during which data contents do not change). is set as .

By the way, in the above embodiment, one, for example, the first
The condition for the count number related to the loop (the contents of the count number latch 67 or 68) to be reset to "0" is 0. When the count number related to the first loop reaches the set count number N.

0 When the count number regarding the other second loop reaches the set count number N.

However, regarding the same conditions, 0: When the count number related to the first loop reaches the set count number N.

0 When a break in the first loop is detected.

It may be set as either one of the following. This also maintains the reliability of the extracted data when the disconnection is restored.

Further, in the above embodiment, data writing to the second data latches 31b or 32b is performed without data errors or disconnections in each loop, and the content of the data latched in the second data latches 31b or 32b and the frame signal are However, data writing to these second data latches 31b or 32b is limited to the case where the content of the data latched in each corresponding first data latch 31a or 32a differs due to the arrival of the data. As long as there is no data error or disconnection in the loop, any of these may of course be implemented, regardless of the content of the comparison described above, that is, it may be performed each time with the data launched into the corresponding first data latch 31a or 32a. Regardless of the case, the data content latched in each second data latch 31b or 32b is the same, and each time the first data latch 31a or 32a is transmitted in one frame word, a new data content is latched. These second functions function as a new data latch means in which data is latched.
Alternatively, the data latch 31b or 32b functions as an old data latch means in which, after new data is launched into the new data latch means, the data latched by the new data launch means is latched as old data. There is no.

In addition, in the above embodiment, for convenience, Raku sensor data (
Although the data D1 to D4 in FIG. 4 are made up of one bit, each of these data may be made up of a plurality of bits.

Although the manner in which the address signal AD is generated may change somewhat depending on the format (number of bits) of these data, even in such a case, the basic data judgment and extraction operations of the circuit of this embodiment are the same as described above. will be realized.

In addition, the data transmitted each time is transmitted from a single data source (
If the signal is from a sensor), the address signal AD is unnecessary, and therefore the address counter 35, the data number holding circuits 12 and 22, etc. are not required.

Further, in the above embodiment, the count number setting device 6
The count number N is set to 0, and when the latch count number for each loose reaches this count number N, the relevant latch pig is extracted as true data. A configuration is adopted in which the latch data is counted down in accordance with the latch count number and when this value reaches "0", the latch data is extracted.
Alternatively, N latch means may be provided corresponding to each loop, and the latch data may be extracted on the condition that the data latched by these 98 latch means are all equal.

In addition, in the above embodiment, the change history of the output data from each sensor group that is arranged in the main controller 100 of the series control 5I+ device as shown in FIG. 6 and transmitted thereto is recorded. Although a configuration example has been shown for the case where the present invention is applied to the data extraction circuit, the data extraction circuit according to the present invention is arranged in each node of the same series control device and is connected to a group of actuators transmitted from the main controller 100. It goes without saying that the present invention can be similarly applied to a circuit that extracts the change layer and history of drive data.

Further, when the data extraction circuit according to the present invention is applied to a serial control device, the serial control device is limited to the configuration shown in FIG. 6, that is, the configuration shown as <a> above, and other < Of course, the same applies to the configurations shown together as b> to <f>.

Incidentally, the frame signal may also have an arbitrary frame configuration depending on the configuration of these serial control devices, and is not limited by the data extraction circuit according to the present invention or the frame configuration of these frame signals. . In short, it is sufficient that it has at least a circuit section for extracting only the desired data portion from these frame signals.

The data extraction circuit according to the present invention performs various processing based on the change history of data that is periodically and repeatedly transmitted from the same data source through the first and second signal lines, respectively. If the system performs control,
The same applies to any system other than the above-mentioned series control device.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to efficiently extract data that is periodically and repeatedly transmitted via a double data transmission system with high reliability.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the data extraction circuit according to the present invention, FIG. 2 is a block diagram showing a specific configuration example of the transfer timing generation circuit shown in FIG. 1, and FIG. 1 is a block diagram showing a specific configuration example of the determination circuit shown in FIG. 1, FIG. 4 is a timing diagram showing an example of the operation of the embodiment circuit shown in FIG. 1, and FIG. , a diagram briefly showing specific examples of extracted movable assets, FIG. 6 is a block diagram showing the general configuration of a series control device that adopts a double loop horizontal transfer, and FIG.
The figure is a time chart showing an example of the structure of a frame signal and an example of a protocol for signal transmission/reception adopted in such a serial control device. 910...Loop ■Processing circuit, 20...
Loop ■ Processing circuit, 30... Extraction processing circuit, 31a,
31b32a, 32b...data latch, 33...
Transfer timing generation circuit, 34... Write clock generation circuit, 35... Address counter, 36... Judgment circuit, EOR31 to EOR33... Exclusive OR circuits as first to third data comparators. Figure 5

Claims (5)

[Claims] (1) A data extraction circuit that extracts a history of changes in data based on matching data that is periodically and repeatedly transmitted from the same data source via first and second signal lines, respectively. , regarding the data transmitted via the first signal line,
A first new data latch means that latches the latest data each time, and after new data is latched in the first new data latch means, the data latched in the first new data latch means is Regarding the first old data latch means that is separately latched as old data, and the data transmitted via the second signal line,
A second new data latch means that latches the latest data each time, and after new data is latched in the second new data latch means, the data latched in the second new data latch means is a second old data latch means that is separately latched as old data; and a first method that compares the data latched by the first new data latch means and the data latched by the first old data latch means. a comparing means, a second comparing means for comparing the data latched by the second new data latch means and the data latched by the second old data latch means, and the first new data latch means and a third comparing means for comparing the data latched by the second new data latch means with the data latched by the second new data latch means, on the condition that the comparison results each time by the third comparing means match. ,
When the comparison result of at least one of the first and second comparing means matches a predetermined number of data, a determining means determines the matching data as true data and extracts and outputs the same. , a data extraction circuit comprising: (2) On the condition that the comparison results each time by the third comparison means match, when the comparison results by the first comparison means match, each time the comparison result matches, the determination means performs an initial A first unit that counts up by one from the value and forcibly sets the count value to the first count value when the comparison results in the first comparison unit do not match.
On the condition that the comparison results of the counter circuit and the third comparison means match each time, when the comparison results of the second comparison means match, each time there is a match, 1 is removed from the initial value. and when the comparison results of the second comparison means do not match, the second comparison means forcibly sets the count value to the first count value.
a counter circuit, a setting device in which a predetermined value is preset for the count value by the first and second counter means, and a predetermined value preset in the setting device for the count value by the first counter circuit. When the value is reached, the data latched by the first old data latch means or the first new data latch means is output, and the count values of the first and second counter circuits are set to initial values. When the count value by the first control circuit and the second counter circuit reaches a predetermined value preset in the setting device, the second old data latch means or the second new data latch means a second control circuit that outputs the latched data and initializes the count values of the second and first counter circuits; and outputs a logical sum of the output data from the first and second control circuits. 2. The data extraction circuit according to claim 1, further comprising: an OR circuit whose output is the true data extraction output. (3) The data extraction circuit includes a first disconnection detection means for detecting whether or not the first signal line is disconnected; and a second disconnection that detects whether or not the second signal line is disconnected. detection means; first error detection means for detecting the presence or absence of an error in the data transmitted via the first signal line; and detection means for detecting the presence or absence of an error in the data transmitted via the second signal line. a second error detection means for detecting the presence or absence of a wire; and when a wire breakage is detected by the first wire breakage detection means;
or a first prohibition that prohibits the data latched by the first new data latch means from being latched to the first old data latch means when an error is detected by the first error detection means; and when a disconnection is detected by the second disconnection detection means,
or a second prohibition that prohibits the data latched by the second new data latch means from being latched by the second old data latch means when an error is detected by the second error detection means; The data extraction circuit according to claim 2, further comprising: means. (4) The first counter circuit holds the current count value when a disconnection is detected by the first disconnection detection means or when an error is detected by the first error detection means. , when a wire breakage and an error are not detected by the first wire breakage detection means and the first error detection means and a wire breakage is detected by the second wire breakage detection means, or when the wire breakage is detected by the second wire breakage detection means, or by the second error detection means. When an error is detected, regardless of the comparison result by the third comparing means, the counting operation is performed on the assumption that the comparison result matching condition is satisfied; When a wire breakage is detected by the wire breakage detection means, or when an error is detected by the second error detection means, the count value at that time is held, and the second wire breakage detection means and the second error detection means When a wire breakage and an error are not detected by the means and the first wire breakage detection means detects a wire breakage, or when an error is detected by the first error detection means, the third comparison means detects a wire breakage and an error. 4. The data extraction circuit according to claim 3, wherein the counting operation is performed on the assumption that the comparison result matching condition is satisfied, regardless of the comparison result. (5) The first counter circuit sets the count value to an initial value when a wire breakage is detected by the first wire breakage detection means, and when an error is detected by the first error detection means. The count values of these first
When a wire breakage and an error are not detected by the wire breakage detection means and the first error detection means, and a wire breakage is detected by the second wire breakage detection means, or when an error is detected by the second error detection means. the second counter circuit performs the counting operation on the assumption that the comparison result match condition is satisfied, regardless of the comparison result by the third comparison means, and the second counter circuit When a disconnection is detected, the count value is set as the initial value,
When an error is detected by the second error detection means, the count value at that time is held, and if the second error detection means does not detect the wire breakage or error, the second error detection means detects the error. When a wire breakage is detected by the first wire breakage detection means or an error is detected by the first error detection means, this comparison result matching condition is satisfied regardless of the comparison result by the third comparison means. 4. The data extraction circuit according to claim 3, wherein the data extraction circuit performs the counting operation.