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JPH02165603A - Varistor - Google Patents

Varistor

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Publication number
JPH02165603A
JPH02165603A JP63322294A JP32229488A JPH02165603A JP H02165603 A JPH02165603 A JP H02165603A JP 63322294 A JP63322294 A JP 63322294A JP 32229488 A JP32229488 A JP 32229488A JP H02165603 A JPH02165603 A JP H02165603A
Authority
JP
Japan
Prior art keywords
electrode
varistor
electrode film
substrate
varistor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63322294A
Other languages
Japanese (ja)
Inventor
Hiroaki Taira
浩明 平
Kazuyoshi Nakamura
和敬 中村
Yasunobu Yoneda
康信 米田
Yukio Sakabe
行雄 坂部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP63322294A priority Critical patent/JPH02165603A/en
Publication of JPH02165603A publication Critical patent/JPH02165603A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To improve the surge strength of a varistor without enlarging a varistor substrate by a method wherein high resistance parts are formed in the electrode isolation parts of the varistor substrate. CONSTITUTION:Electrode isolation parts 7 having required widths W are formed between a first electrode film 5 on the edge part of the second main surface 2b of a varistor substrate 2 and a second electrode film 4 and between a second electrode film 6 on the edge part of the first main surface 2a of the varistor substrate 2 and a first electrode film 3. High resistance parts 8 are formed in both the electrode isolation parts 7 and 7 of the varistor substrate 2 so as to penetrate into the substrate 2 to the thickness direction. Therefore, even if both the electrode films facing each other with the electrode isolation part 7 between are made to come closer to each other, a current does not flow between the electrodes. With this constitution, effective electrode areas can be increased without enlarging the dimensions of the varistor substrate, so that the surge strength of the varistor can be improved while the small size is maintained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、電圧非直線性抵抗として機能するチップ型バ
リスタに関し、特にバリスタ基板の寸法を大きくするこ
となくサージ耐量を向上できるようにした構造に関する
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a chip-type varistor that functions as a voltage non-linear resistor, and in particular to a structure that can improve surge resistance without increasing the dimensions of the varistor substrate. Regarding.

〔従来の技術〕[Conventional technology]

従来から、印加電圧に応じて抵抗値が非直線的に変化す
る抵抗体素子として、第3図に示すチップ型バリスタが
ある。このバリスタ10は、酸化亜鉛を主成分とする矩
形状のバリスタ基板11の上面11a、及び下面11b
にそれぞれ第1電極膜12.第2電極膜13を形成し、
上記バリスタ基板11の両側面11c、11dに、上記
第1゜第2電極膜12.13にそれぞれ接続された第1
゜第2外部電極膜14.15を形成するとともに、該第
1外部電極膜14と上記第2電極膜13との間、及び第
2外部電極膜15と上記第1電極膜12との間に所定の
幅Wを有する電極分離部16を形成して構成されている
2. Description of the Related Art Conventionally, there has been a chip-type varistor shown in FIG. 3 as a resistor element whose resistance value changes non-linearly depending on an applied voltage. This varistor 10 has an upper surface 11a and a lower surface 11b of a rectangular varistor substrate 11 whose main component is zinc oxide.
respectively, the first electrode film 12. forming a second electrode film 13;
First electrode films connected to the first and second electrode films 12 and 13 are respectively connected to both side surfaces 11c and 11d of the varistor substrate 11.
゜A second external electrode film 14.15 is formed, and between the first external electrode film 14 and the second electrode film 13, and between the second external electrode film 15 and the first electrode film 12. It is configured by forming an electrode separation part 16 having a predetermined width W.

ここで、上記電極分離部16を挟んで対向する電極膜1
2.15及び13.14同士が近づき過ぎる。と、この
間に電流が漏れてバリスタ特性を悪化させるおそれがあ
る。そのため、従来から上記電極分離部16は、その幅
Wがバリスタ基板11の厚さHの1.5倍程度になるよ
う設定されており、これにより電流が流れるのを防止し
ている。
Here, the electrode films 1 facing each other with the electrode separation part 16 in between are
2.15 and 13.14 are too close to each other. During this time, current may leak and deteriorate the varistor characteristics. Therefore, the width W of the electrode separation section 16 has conventionally been set to be approximately 1.5 times the thickness H of the varistor substrate 11, thereby preventing current from flowing.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ところで、上記バリスタIOにおいてサージ耐量を大き
くするには、上記バリスタ基板11を挟んで対向する第
1.第2電極膜12.13の有効電極長さし、ひいては
電極面積を大きくすることにより実現できる。しかしな
がら、上記従来のバリスタ10では、有効電極長さしを
大きくするにはバリスタ基板11を大きくするしかな(
、それだけバリスタが大型化するという問題点がある。
By the way, in order to increase the surge withstand capacity in the varistor IO, the first . This can be achieved by increasing the effective electrode length of the second electrode film 12, 13, and by extension the electrode area. However, in the conventional varistor 10 described above, the only way to increase the effective electrode length is to increase the size of the varistor substrate 11 (
However, there is a problem in that the varistor becomes larger accordingly.

本発明は上記従来の問題点を解決するためになされたも
ので、バリスタ基板を大きくすることなく、サージ耐量
を向上できるバリスタを提供することを目的としている
The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a varistor that can improve surge resistance without increasing the size of the varistor substrate.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、バリスタ基板の第1主面、第2主面にそれぞ
れ第1t極膜、第2電極膜を形成し、上記バリスタ基板
の第1側面、第2側面に上記第1゜第2電極膜にそれぞ
れ接続された第1.第2外部電極膜を形成し、かつ該第
1外部電極膜と上記第2電極膜との間、及び第2外部電
極膜と上記第1電極膜との間に所定幅の電極分離部を形
成してなるバリスタにおいて、上記バリスタ基板の上記
電極分離部部分に高抵抗部を形成したことを特徴として
いる。
In the present invention, a first t electrode film and a second electrode film are formed on the first main surface and the second main surface of the varistor substrate, respectively, and the first and second electrode films are formed on the first side surface and the second side surface of the varistor substrate. the first . each connected to the membrane. forming a second external electrode film, and forming an electrode separation part of a predetermined width between the first external electrode film and the second electrode film and between the second external electrode film and the first electrode film; The varistor is characterized in that a high resistance portion is formed in the electrode separation portion of the varistor substrate.

ここで、上記高抵抗部は、例えばZnOを主成分とする
バリスタ基板の電極分離部に、Liの化合物の1つであ
るLlgCOsをペースト状にしたものを塗布し、これ
を焼き付けてLiをバリスタ基板内に拡散させることに
より実現できろ。
Here, the above-mentioned high-resistance part is made by applying a paste of LlgCOs, which is one of the Li compounds, to the electrode separation part of a varistor substrate mainly composed of ZnO, for example, and baking the paste to transfer Li to the varistor substrate. This can be achieved by diffusing it into the substrate.

〔作用〕[Effect]

本発明に係るバリスタによれば、バリスタ基板の電極分
離部部分に高抵抗部を形成したので、この電極分離部を
挟んで対向する電極膜同士を近接させても、この間に電
流が流れることはない、その結果、バリスタ基板の寸法
を大きくすることなく育効電極面積を大きくでき、従っ
て小型のままでサージ耐量を向上できる。
According to the varistor of the present invention, since the high resistance part is formed in the electrode separation part of the varistor substrate, even if the electrode films facing each other are brought close to each other with the electrode separation part in between, current will not flow between them. As a result, the area of the growth electrode can be increased without increasing the dimensions of the varistor substrate, and therefore the surge resistance can be improved while remaining small.

〔実施例〕〔Example〕

以下、本発明の実施例を図について説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

第1図及び第2図は本発明の一実施例によるバリスタを
説明するための図である。
FIGS. 1 and 2 are diagrams for explaining a varistor according to an embodiment of the present invention.

図において、1は本実施例のチップ型バリスタであり、
これのバリスタ基板2の上面の第1主面2aには第1電
極1I13が、下面の第2主面2bには第2電極膜4が
それぞれ形成されている。また、上記バリスタ基板2の
第1側面2Cには第1外部電極M5が形成されており、
該第1外部電極JI15の一端面は上記第1電極膜3に
接続され、他端面ば上記第2主面2bの縁部に延びてい
る。さらに、上記第1側面2cと対向する第2側面2d
には第2外部電極lll6が形成されており、該第2外
部電極1I16の一端面は上記第2電橿lllI4に接
続され、他端面ば上記第1主面2aの縁部に延びている
In the figure, 1 is a chip type varistor of this embodiment,
A first electrode 1I13 is formed on the upper first main surface 2a of the varistor substrate 2, and a second electrode film 4 is formed on the lower second main surface 2b. Further, a first external electrode M5 is formed on the first side surface 2C of the varistor substrate 2,
One end surface of the first external electrode JI15 is connected to the first electrode film 3, and the other end surface extends to the edge of the second main surface 2b. Furthermore, a second side surface 2d opposite to the first side surface 2c
A second external electrode Ill6 is formed on the second external electrode Ill6, one end surface of the second external electrode II16 is connected to the second electric rod IllI4, and the other end surface extends to the edge of the first main surface 2a.

上記バリスタ基板2の第2主面2bの縁部に位置する第
1外部電極膜5と第2電極膜4との間、及び上記第1主
面2aの縁部に位置する第2外部電lfI膜6と上記第
1電極膜3との間には所定幅Wからなる電極分離部7が
形成されている。
A second external electrode lfI located between the first external electrode film 5 and the second electrode film 4 located at the edge of the second main surface 2b of the varistor substrate 2, and a second external electrode film 4 located at the edge of the first main surface 2a. An electrode separation part 7 having a predetermined width W is formed between the film 6 and the first electrode film 3.

そして、上記バリスタ基板2の上記画電極分離部7.フ
には高抵抗部8が厚さ方向に浸透するように形成されて
いる。この高抵抗部8は、Llを上記バリスタ基板2内
に拡散させて絶縁部を形成してなるものであり、上記高
抵抗部8は表面抵抗率で100MΩノロ以上有している
。これにより、上記電極分離部7の幅Wはバリスタ基板
2の厚さHの1/4程度になっている。
Then, the picture electrode separation section 7 of the varistor substrate 2. A high resistance portion 8 is formed in the film so as to penetrate in the thickness direction. This high resistance portion 8 is formed by diffusing Ll into the varistor substrate 2 to form an insulating portion, and has a surface resistivity of 100 MΩ or more. As a result, the width W of the electrode separation section 7 is approximately 1/4 of the thickness H of the varistor substrate 2.

次に本実施例の作用効果について説明する。Next, the effects of this embodiment will be explained.

本実施例のチップ型バリスタlによれば、バリスタ基板
2の画電極分離部7部分に、Liを拡散させてなる高抵
抗部8を形成したので、第1外部電極膜5と第2電極膜
4との間、及び第2外部電極膜6と第1電極膜3との間
の輻Wを狭くできるから、それだけ第1.第2電極膜3
.4が対向する有効1i極長さLlつまり電極面積を大
きくでき、その結果バリスタ基板の寸法を大きくするこ
となくサージ耐量を向上できる。即ち、本実施例のバリ
スタ基板2の外形寸法り、を従来の外形寸法L゛ (第
3図参照)と同じにした場合は、有効電極長さLi・を
従来の長さしより太き(することができる、またサージ
耐量を同じにした場合は、従来より外形寸法を小さくで
き、小型化を実現できる。
According to the chip type varistor l of this embodiment, the high resistance part 8 made by diffusing Li is formed in the picture electrode separation part 7 of the varistor substrate 2, so that the first external electrode film 5 and the second electrode film 4 and between the second external electrode film 6 and the first electrode film 3, the width W between the second external electrode film 6 and the first electrode film 3 can be narrowed. Second electrode film 3
.. The effective length Ll of the poles 1i facing 4, that is, the electrode area can be increased, and as a result, the surge resistance can be improved without increasing the dimensions of the varistor substrate. That is, when the external dimensions of the varistor substrate 2 of this embodiment are made the same as the conventional external dimensions L' (see Fig. 3), the effective electrode length Li is set to be thicker than the conventional length ( Furthermore, if the surge resistance is kept the same, the external dimensions can be made smaller than in the past, and miniaturization can be achieved.

例えば、従来のバリスタにおいて(第3図参照)、バリ
スタ基板の外形寸法L゛を20鶴、厚さHを2fi、電
極分離部の幅W′を3鶴(厚さH×1.5倍)、バリス
タ基板の端から電極分離部までの各外部電極膜の長さl
′を1鶴とすると、第1゜第2電極膜の有効電極長さし
は、 L−20−(3+1)X2−12寵 となる。
For example, in a conventional varistor (see Figure 3), the external dimension L of the varistor substrate is 20mm, the thickness H is 2fi, and the width W' of the electrode separation part is 3mm (thickness H x 1.5 times). , the length l of each external electrode film from the edge of the varistor substrate to the electrode separation part
If ' is one crane, the effective electrode length of the first and second electrode films is L-20-(3+1)X2-12.

これに対して、本実施例では、電極分離部7の輻Wを0
.5 M (バリスタ基板の厚さの1/4)に短くでき
るから、バリスタ基板2の外形寸法Ll+厚さH1外部
電極膜の長さlを従来と同じにした場合、 有効電極長さL+ −20(0,5+1)X2 =17
mmとなり、有効電極長さし、を5鶴(約40%)長く
できる。また、育効長り、を従来と同じ12鶴とすると
、サージ耐量を下げることなく外形寸法L8を15mま
で小さ(できる。
On the other hand, in this embodiment, the radiation W of the electrode separation section 7 is set to 0.
.. Since it can be shortened to 5 M (1/4 of the thickness of the varistor substrate), if the external dimension Ll + thickness H1 of the varistor substrate 2 and the length l of the external electrode film are kept the same as before, the effective electrode length L+ -20 (0,5+1)X2 =17
The effective electrode length can be increased by 5 mm (approximately 40%). Furthermore, if the growth length is set to 12 cranes, which is the same as before, the external dimension L8 can be reduced to 15 m without lowering the surge resistance.

また、上記高抵抗部8は、バリスタ基板2に電極ペース
トを塗布して各電極膜を形成する工程時に、l、 11
 COxペーストを塗布しておき、これを−緒に焼き付
けることによって形成できるから、製造コストを上昇さ
せることはない。
Further, the high resistance portion 8 is formed by applying electrode paste to the varistor substrate 2 to form each electrode film.
Since it can be formed by applying a COx paste and baking it together, the manufacturing cost does not increase.

〔発明の効果〕〔Effect of the invention〕

以上のように本発明に係るバリスタによれば、バリスタ
基板の電極分離部に高抵抗部を形成したので、バリスタ
基板の寸法を大きくすることなく第1.第2電極膜の有
効電極面積を増大でき、それだけサージ耐量を向上でき
る効果がある。
As described above, according to the varistor according to the present invention, since the high resistance portion is formed in the electrode separation portion of the varistor substrate, the first varistor can be removed without increasing the dimensions of the varistor substrate. This has the effect of increasing the effective electrode area of the second electrode film and improving surge resistance accordingly.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図は本発明の一実施例によるチップ型バ
リスタを説明するための図であり、第1図はその斜視図
、第2図はその側面図、第3図は従来のチップ型バリス
タを示す側面図である。 図において、1はチップ型バリスタ、2はバリスタ基板
、2aは第1主面、2bは第2主面、2Cは第1側面、
2dは第2側面、3は第1電極膜、4は第2電極膜、5
は第1外部電極膜、6は第2外部電極膜、7は電極分離
部、8は高抵抗部、Wは電極分離部の幅である。 第1図
1 and 2 are diagrams for explaining a chip type varistor according to an embodiment of the present invention, in which FIG. 1 is a perspective view thereof, FIG. 2 is a side view thereof, and FIG. 3 is a conventional chip varistor. FIG. 3 is a side view showing a mold varistor. In the figure, 1 is a chip type varistor, 2 is a varistor substrate, 2a is a first main surface, 2b is a second main surface, 2C is a first side surface,
2d is the second side surface, 3 is the first electrode film, 4 is the second electrode film, 5
is the first external electrode film, 6 is the second external electrode film, 7 is the electrode separation part, 8 is the high resistance part, and W is the width of the electrode separation part. Figure 1

Claims (1)

【特許請求の範囲】[Claims] (1)バリスタ基板の第1主面,第2主面にそれぞれ第
1電極膜,第2電極膜を形成し、上記バリスタ基板の第
1側面,第2側面に上記第1,第2電極膜にそれぞれ接
続された第1,第2外部電極膜を形成し、かつ該第1外
部電極膜と上記第2電極膜との間,及び第2外部電極膜
と上記第1電極膜との間に所定幅の電極分離部を形成し
てなるバリスタにおいて、上記バリスタ基板の上記電極
分離部部分に高抵抗部を形成したことを特徴とするバリ
スタ。
(1) A first electrode film and a second electrode film are formed on the first main surface and the second main surface of the varistor substrate, respectively, and the first and second electrode films are formed on the first side surface and the second side surface of the varistor substrate. forming first and second external electrode films connected to each other, and between the first external electrode film and the second electrode film, and between the second external electrode film and the first electrode film. A varistor comprising an electrode separation part of a predetermined width, characterized in that a high resistance part is formed in the electrode separation part of the varistor substrate.
JP63322294A 1988-12-20 1988-12-20 Varistor Pending JPH02165603A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63322294A JPH02165603A (en) 1988-12-20 1988-12-20 Varistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63322294A JPH02165603A (en) 1988-12-20 1988-12-20 Varistor

Publications (1)

Publication Number Publication Date
JPH02165603A true JPH02165603A (en) 1990-06-26

Family

ID=18142021

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63322294A Pending JPH02165603A (en) 1988-12-20 1988-12-20 Varistor

Country Status (1)

Country Link
JP (1) JPH02165603A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019165103A (en) * 2018-03-20 2019-09-26 パナソニックIpマネジメント株式会社 Laminated varistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019165103A (en) * 2018-03-20 2019-09-26 パナソニックIpマネジメント株式会社 Laminated varistor

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