JPH02165124A - Active matrix type liquid crystal display device and its driving method - Google Patents

Abstract

PURPOSE:To hold the charge after write by setting a gate bias voltage to a negative potential against a drain at the time of non-selecting and holding a TFT in a nonconducting state. CONSTITUTION:Two pieces of adjacent scan bus lines SB, SB' for placing a picture element in the line direction between them are bridged by two capacitors C1, C2 connected in series at every picture element, and a gate G of a thin film transistor (TFT) 1 for constituting the picture element is connected to both the capacitors. Also, one source S of the TFT 1, and the other drain D are connected to a display electrode E being on the TFT substrate side of a liquid crystal cell LC, and the scan bus line SB' whose scanning sequence is the second, respectively. In such a case, as for the capacitors C1, C2, a negative charge accumulation is executed to the drain of the TFT after the address, therefore, as for the gate connected to a midpoint of two capacitors C1, C2, a negative potential is applied to the drain, and the TFT can always be set completely to a turn-off state.

Description

[Detailed Description of the Invention] [Summary] Regarding the improvement of a thin film transistor matrix, particularly a thin film transistor matrix of a gate-connected opposing matrix type, the following steps are taken: In the gate-connected opposing matrix type, the gate bias voltage is set to a negative potential with respect to the drain when not selected. With the aim of making this possible, a plurality of display electrodes for electrically controlling the liquid crystal and a plurality of thin film transistors for driving the display electrodes are arranged in a matrix on one surface of a pair of insulating substrates arranged opposite to each other. If the pixels are arranged in a pattern and a scan canvas line is arranged along the row direction between each pixel consisting of a pair of the display electrode and the thin film transistor,
The control electrodes of the thin film transistors in the row direction are commonly connected to the corresponding scan canvas line, one of the pair of controlled electrodes is connected to the corresponding display electrode, and the other is connected to the next adjacent scan canvas line in the scanning order. In the configuration of the gate-connected facing matrix method, two adjacent scan canvas lines with a pixel in the row direction in between are bridged by two capacitors connected in series for each pixel, and the pixel is connected to the connection point of both capacitors. The control electrodes of the constituent thin film transistors are connected.

[Industrial application field]

The present invention relates to an improvement in a thin film transistor matrix, particularly a gate-connected opposed seven-trix type thin film transistor matrix.

In this type of active matrix liquid crystal display device, thin film transistors (TPTs) act as switching elements to supply voltage to the liquid crystal cells, so the voltage of each cell can be accurately controlled, making it suitable for large-capacity five-gradation display. It is a display device with Therefore, in recent years, active development has been carried out aiming at display devices for OA terminal equipment, including displays that have already been commercialized as display devices for pocket TVs.

[Conventional technology]

In order to realize a display device with a large screen size, such as a display device for OA terminal equipment, it is necessary to form a large number of transistors without defects according to the number of pixels, and this is not necessarily easy.

In order to facilitate the production of a large number of transistors without defects, TFTI has no pass line intersections and the number of manufacturing steps can be reduced.
A thin film transistor matrix called a gate-connected facing matrix type has been proposed in Japanese Patent Application No. 61-212696.

In this method, there is no intersection of pass lines on the surfaces of either the TPT substrate P and the counter substrate P', which are disposed facing each other with a display medium such as a liquid crystal in between.

FIGS. 5(a) and 5(b) are an equivalent circuit diagram showing the configuration of one pixel of the above system, and an exploded perspective view showing the configuration of a TPT matrix.

As seen in the figure, in this method, T P T substrate 2
On the surface, there are a plurality of pixel electrodes arranged in a matrix, a scan canvas line SB arranged corresponding to each row of the pixel electrodes, and a driving T provided for each pixel electrode.
The gate i-electrode G of the TFTI for driving each pixel is connected to the scan canvas line SB for selecting that pixel electrode, and the drain electrode is connected to the adjacent scan canvas line ( On the other hand, a data bus line for supplying display data to each pixel is formed in a stripe shape on the back surface of the counter substrate P° corresponding to the columns of the pixel electrodes. It also serves as a counter electrode.A liquid crystal cell is formed by a pixel electrode and a counter electrode that face each other with a liquid crystal in between.

Normally, the drain electrode is connected to a common path line provided separately from the scan path line SB and the data bus line DB mentioned above, but in this method, the drain electrode is connected to the adjacent scan path line to connect the common path. Eliminates the need for line, scan canvas line SB is TFT
On the substrate, the data bus line DB is arranged on the counter substrate P', so that the pass lines do not intersect at all.

[Problems to be Solved by the Invention] As shown in (g) below, this method has the structural advantage that there is no intersection of pass lines, but when driving, the gate of the transistor is removed during the voltage holding period of the liquid crystal cell LC. Since the electrode G and the drain electrode are at the same potential, the gate voltage =
The off-state current at 0 is sufficiently low, that is, the dark value voltage ■
It is necessary to correct the situation.

However, positive fixed charges tend to occur in the gate insulating film used in the TPT, and as a result, the dark value voltage vtt+ tends to become negative.

An object of the present invention is to maintain the TPT in a non-conductive state by setting the gate bias voltage to a negative potential with respect to the drain when not selected in the gate-connected facing matrix method, so that the charge after writing can be retained.

[Means to solve the problem]

The present invention will be explained in detail with reference to FIG.

As seen in the figure, in a gate-connected facing matrix type liquid crystal display device, the present invention provides a method for connecting two scan canvas lines SB and SB' that are adjacent to each other with a pixel in the row direction in between.
Each pixel is bridged by two capacitors CI and Ct connected in series, and the TF forming the pixel is connected to the connection point of both capacitors.
The gate G of Tl was connected.

Note that in the gate-connected facing matrix type, one controlled electrode (for example, source S) of the TFTl is connected to the liquid crystal cell LCOT.
As described above, the other controlled electrode (for example, the drain D) is connected to the scan canvas line SB' which is next in the scanning order next to the display electrode on the FTI board side.

[For production]

In this configuration, negative charges are stored in the capacitors C2 and 02 with respect to the drain of TPT after addressing, so the gate connected to the midpoint of the two capacitors C1 and 02 is stored with respect to the drain. A negative potential is applied, and the TPT can always be completely turned off.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 2 to 4.

FIG. 2 is an equivalent circuit diagram showing the configuration of one embodiment of the present invention. As shown in the figure, in this embodiment, the scan canvas line (for example, SB) corresponding to each pixel and the scanning order are determined for each pixel. The next scan canvas lines (for example, 582) are bridged by two series-connected capacitors C, , C2. Here, capacitor C5 is placed on the front scanhas line side.
It is assumed that a capacitor C2 is connected to the rear scan canvas line side.

Furthermore, for each pixel, the midpoint P of two capacitors c, , C2
+, Pz, Ps, thin film transistor T for driving each pixel
I T2 and the gate G of Tel are connected.

One of the controlled electrodes (for example, a source electrode) S of each of the thin film transistors T1, Tt, and T3 is the same as the display electrode of the liquid crystal cell LC, and the other (for example, a drain electrode) D is the scan canvas line SBt, which has the next scanning order. Connect to SB,,SB,.

Note that Pa, P2. Pa. P indicates a connection point between each scan canvas line SB+, SBz, SB3, SB4 and a capacitor.

In this embodiment, the capacitance of the capacitors C+ and Cz was approximately 5 pF.

The operation of this embodiment configured in this way is shown in FIGS. 3(a) to 3(a).
This will be explained using (f).

Time, smell, scan canvas line SB.

The impedance of the drive circuit as seen from SB is set to low (L), and the scanning signal is sent to the scan canvas line SB +.
A positive potential of 0 [■] is applied to SB2 (see FIG. 3(a)). In synchronization with this, display data is supplied from the data bus line DB.

Here, if the gate input capacitance is about 0.05 pF, it is much smaller than the capacitance of capacitors C+ and Cz, so
The influence of this can be almost ignored, and the voltage at the midpoint P1 [3rd
(see figure (d)) is approximately half the voltage (2) applied between the scan canvas lines SB, SBz, and the thin film transistor T1 can be turned on, and the display data supplied from the data bus line DB is displayed on the liquid crystal display. Written to cell LC.

The address of scan canvas line SB + ends,
At time t2 when the address of the next scan canvas line SB, starts, scan canvas lines SB, SB,
, lower the impedance of the drive circuit seen from SB3 (
L), the potential of the scan canvas line SB is 0 [■
], and when a positive potential of ■ is applied to the scan canvas line SB [see Fig. 3 (b)], the potential at the midpoint P3 of the two capacitors becomes approximately V/2 [Fig. 3 (
(see (to)), the thin film transistor T is turned on.

The capacitor C of the pixel that ended the address in this sale,,
The potential at the midpoint P1 of C is - with respect to the drain D of T.
Since the voltage becomes V/2 [see FIG. 3(d)], the thin film transistor T1 that has finished addressing is turned off.

At time, if the impedance of the drive circuit seen from the scan canvas line SB is "high" (H), then this impedance and the capacitor C provided at each pixel are
, C, the potential across C2 is attenuated by the CR time constant. However, since one frame is about 30 ms, if this time constant is about 0.1 S, this attenuation is very small, and the thin film transistor T can be turned off sufficiently until the next address.

The impedance R required at this time, assuming that the number of pixels in one line is 1000, is R≧0.1/1000(5/2)・10-” = 40M
Ω, which can be realized by the output impedance of the gate-grounded MO3 output circuit. Therefore, capacitor C,,
Since the negative voltage at the midpoint P of CR can be maintained at 100 m5 or more, the thin film transistor T can be sufficiently turned off for one frame.

Similarly, at time, a positive voltage of ■ is applied to the scan canvas line SB, and the scan canvas line SB is set to 0 (V) [see FIG. 3(C)], and the thin film transistor T is turned on. Make it.

At this time, the potential of the thin film transistor Tt is approximately 1 /
2 [see FIG. 3(f)], and T2 is turned off.

In this way, in this embodiment, the output impedance of the drive circuit is set to "low degree" with respect to the scan canvas line to be addressed and the scan canvas lines before and after it, and "high degree" with respect to other scan canvas lines. It can be driven by applying a scanning signal and display data in the same way as usual, and the gate potential of the thin film transistor can be made negative with respect to the drain potential except when addressing, so when not selected, The thin film transistor can be turned off reliably.

Next, an example embodying the above embodiment is shown in FIGS.
This is explained by C).

Figure (a) is a plan view of the main parts showing the arrangement of each part for one pixel, where SB is the scan canvas line for selecting the pixel, SB' is the scan canvas line with the next highest scanning order,
It is formed from a conductive film such as an An film. Also, E is IT
A display electrode made of a transparent conductive film such as an O film, G is Cr(
S and D are the source and gate electrodes.
Drain electrodes C9 and C2 represent capacitors.

The source/drain electrodes S and D are made of a SiN film 3 that covers the gate electrode G formed on the glass substrate 2, as shown in FIG. A-3i film as gate insulating film and active semiconductor layer 4.
nia-Si film as contact layer5. Conductive films such as a Ti (titanium) film 6 are laminated and selectively etched according to a predetermined pattern.

One of the source and drain electrodes formed in this way (
(indicated by reference numeral S) is connected by partially overlapping with the display electrode E described above.

The other side (indicated by reference numeral) is irradiated with a laser beam to the overlapping part with the next scan canvas line SB' to melt that part and form the scan canvas line SB' with the upper Ti film 6. The SiN film 3 is connected to the A1 film through the SiN film 3.

The structures of the capacitors C1 and C2 are derived from the scan canvas lines SB and SB', as shown in FIG. A Cr film 9 is formed via a TazOs film 8 so as to bridge the A1 film 7 formed in the above and 7° above. The extended portion of this Cr film 9 forms the aforementioned gate electrode G.

The Al films 7, 7' and the Cr film 9 are insulating films of TazO.
Since they face each other with the S film 8 in between, they constitute two parallel plate type capacitors CI and Ct.

This embodiment can be implemented in the manner described above. The materials used to construct the two capacitors C, C2 in this example are materials that are normally used for thin film transistor matrices. Since it can be fabricated using a thin film transistor for driving a gate-connected facing matrix type liquid crystal display device, the gate bias voltage is at a negative potential with respect to the drain when it is not selected. Therefore, the non-conducting state can be maintained during that time, and the charge after writing can be sufficiently retained.

Since it can be completely turned off, sufficient data storage is possible and clear images can be obtained.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the configuration of the present invention, Fig. 2 is an explanatory diagram of the configuration of one embodiment of the invention, and Figs.
(f) is a drive waveform diagram of the above embodiment, and FIGS. 4(a) to (
C) is a structural explanatory diagram of the above embodiment, FIG. 5(a), (
b) is a diagram illustrating the problems of the conventional gate-connected opposing matrix method. In the figure, 1 is a thin film transistor (TPT), 2 is an insulating substrate (glass substrate), G is a gate electrode, S, D are source/drain electrodes, SB, SB'SB, ~SB are scan canvas lines, DB is a Data bus line, T, ~T
3 indicates a thin film transistor. [Effects of the Invention] As explained above, according to the present invention, the TPT can be completed / ￥￮口子子 A″ Establishment of the Ming Dynasty Moon diagram Fig. 2 tet + tztstststit& Present invention - Arrow and snake example bow oto and low form diagram Fig. 3

Claims (2)

[Claims] (1) A plurality of display electrodes (1, 1') for electrically controlling the liquid crystal are provided on one surface of a pair of insulating substrates (1, 1') arranged facing each other.
E) and a plurality of thin film transistors (1) for driving the display electrodes are arranged in a matrix in correspondence with each other, and a plurality of thin film transistors (1) are arranged in a matrix along the row direction between each pixel consisting of a pair of the display electrode (E) and the thin film transistor (1). scan canvas line (SB
, SB'), and the control electrodes (G) of each thin film transistor (1) in the row direction are commonly connected to the corresponding scan canvas line (SB), and one of the pair of controlled electrodes (S) is connected in common to the corresponding scan canvas line (SB). In a gate-connected opposing matrix configuration in which the corresponding display electrode (E) is connected to the other (D) to the adjacent scan canvas line (SB') having the next highest scanning order, two adjacent pixels across the row direction are connected. The scan canvas lines (SB, SB') of the book are bridged by two capacitors (C_1, C_2) connected in series for each pixel, and the control electrode (G) of the thin film transistor constituting the pixel is at the connection point of both capacitors. An active matrix liquid crystal display device characterized by connecting. (2) The output impedance of the drive circuit that drives the scan canvas lines (SB, SB') can be switched,
The output impedance of the drive circuit is set to 'low impedance' for the scan canvas line to be addressed and the scan canvas lines that precede and follow this scan canvas line, and for other scan canvas lines. '
2. The method of driving an active matrix liquid crystal display device according to claim 1, wherein the driving method is characterized in that the driving method is a high impedance.