JPH02164128A - A phase locked loop circuit, charge pump used for the circuit and operating method for the circuit - Google Patents

Abstract

PURPOSE:To avoid the production of a dead band when a phase difference is nearly zero providing a charge pump operated at the time of pulling in phase and at the time of locking phase, and providing a charge current source and a discharge current source whose operation is switched by a switch. CONSTITUTION:A phase comparator 1 generates INC signals 13H, 13N and DEC signals 14H, 14N when pulling in phase and when locking phase by using a readout signal 11 and a VCO clock 12 and supplied them to phase pulling in and phase locking charge pumps 2H, 2N respectively. The pumps 2H, 2N consist respectively of charge current sources 21H, 21N, discharge current sources 22H, 22N, 32H, 32N, INC current switches 26H, 26N and DEC current switches 27H, 27N. A current switching circuit 4 switches the current of the sources 22H, 22N by using a read/write signal 18 and a pull-in signal 19. A loop filter 3 smooths the output current of the pumps 2H, 2N to generate a VCO control voltage.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a phase synchronized circuit for a data separator 1 used for reading data in a magnetic disk drive, a charge pump used therein, and a method of operating the phase synchronized circuit. Regarding.

[Prior Art] In magnetic disk devices and the like, it is necessary to distinguish signals read from a disk into data and clock. The part that generates the synchronized clock signal necessary for this discrimination is a phase synchronized circuit.

FIG. 5 shows a block diagram of the phase locked circuit. The phase locked circuit shown in the figure includes a phase comparator 1, a charge pump 2. It is composed of a loop filter 3 and a voltage controlled oscillator (hereinafter abbreviated as vCO) 5.

The phase comparator 1 receives a read signal 11 from the disk,
The phase of the vC○ clock 12 outputted by the VCO 5 is compared, and if the phase of the readout signal 11 is ahead of the phase of the VC○ clock 12, the INC signal 1 is output by that time.
3, and conversely, if it is behind the vCO clock 12, it outputs the DEC signal 14 for that time.

The charge pump 2 receives this rNC signal 13 and D
An EC compensation signal 1 is provided, and a charging operation is performed on the loop filter 3 only during the time when the rNc signal 13 is input.

On the other hand, a discharge operation is performed on the loop filter 3 only during the time that the DEC signal 14 is input.

The loop filter 3 generates a VCO control voltage 16 by integrating the charge amount 15 resulting from the charge operation or discharge operation.

The VCO 5 has a frequency v corresponding to the vC○ control voltage 16.
Outputs CO clock 12.

In this way, the phase synchronized circuit operates and ■ CO clock 12
The phase of the data 11 is read out and matched with the phase of the data 11.

For the general circuit configuration of the phase comparator 1, charge pump 2, and loop filter 3 described above, see, for example, "Latest Floppy Disk Devices and Their Application Know-how J CQ
Publisher (1984), p. 164. 6th
The figure shows such a general circuit configuration.

In FIG. 6, the phase comparator 1 includes a D type flip-flop (hereinafter abbreviated as DFF) 23° 24 and a NAN
D gate 25.

Further, the charge pump 2 is turned on by a charge current source 21, a discharge current source 22, and an INC signal 13 which is the output of the DFF 23, and a charge current g2
1 to the loop filter 3, and a switch 27 which is turned off by the DEC signal 14 which is the output of the DFF 24 and connects the discharge current source 22 to the loop filter 3.

Further, the loop filter 3 is constituted by an integrating circuit including a resistor R11 and a capacitor C1l connected in series, and a capacitor C21 connected in parallel with these.

The circuit shown in FIG. 6 operates as follows.

Now, assuming that the phase of the read signal 11 is ahead of the phase of the CO clock 12, first, the read data 11
At the rising edge of INC which is the output of DFF23
(ffi signal 13 is asserted. In response to the assertion of this INC signal -13, the charge pump 2 turns on the switch 26 and charges the loop filter 3 with the charge current source 21. Thereafter, the vC○ clock 12
When the DEC signal 14, which is the output of the DFF 24, is asserted at the rising edge of the
Both the NC signal 13 and the DEC signal 14 are negated.

That is, the switch 26 is turned on for a time corresponding to the phase difference between the read signal 11 and the vCO clock 12 to perform charging. Conversely, if the phase of the readout clock 11 lags behind the phase of the CO clock 12, the switch 27 is turned on for a time corresponding to the phase difference to perform discharging.

[Problems to be Solved by the Invention] In the above conventional technology, when the one-phase synchronization circuit completes phase locking and the phases of the readout signal 11 and the vCO clock 12 almost match, the output pulse width of the phase comparison F'uf1 is becomes almost equal to zero.

However, the charge pump current on/off switch 26
．． There is a limit to the switching speed of 27. Furthermore, the switches 26 and 27 have different switching speeds due to the difference in circuit configuration. The switch 26 cannot respond to inputs below the pulse Iut.

Further, the switch 27 cannot respond to inputs less than the pulse @tD. This phenomenon is shown in FIG.

In FIG. 7, the horizontal axis is the phase difference between the read data 11 and the vCO clock 12, and the vertical axis is the amount of charge and discharge that is the output of the charge pump. In an ideal linear response, the graph would be a straight line through the origin, but in reality.

As shown in the figure, when the phase difference is around zero, the output charge amount becomes zero.

In this state, feedback control does not work in the phase-locked circuit (dead zone), resulting in an open loop state, reducing the stability of the system. This causes system jitter and the like, leading to performance deterioration.

On the other hand, a discharge current source capable of canceling out the charge current of the corresponding charge current source is added to the discharge current source in addition to the original discharge current source, and a switch is provided only in the discharge current source to charge the discharge current source. It is conceivable to configure a pump. In this case, a plurality of discharge current sources are provided.

According to the method described above, when all the switches on the discharge current source side are turned off, the charge current source acts; on the other hand, when all the switches are turned on, the effect of the charge current source is canceled and the discharge current source acts, resulting in a discharge operation. Therefore, since the charging operation is continuously shifted to the discharging operation, the above-mentioned dead zone is prevented from occurring.

However, even with this method, the conventional phase-locked circuit has a first-order gap.

The switch of a charge pump in a phase-locked circuit is generally composed of a transistor. in this case.

The transistor used is one formed so that a large current can flow during one phase pull-in. By the way, the phase locked circuit does not require much current during phase locking, and is rather desired to be able to respond at high speed. However, the above-described large current transistor has a problem of poor response characteristics. Furthermore, there is a difference in characteristics between when a large current is flowing and when a small current is flowing, and there is a gap in which it is difficult to expect the characteristics to match the designed values.

In this way, in conventional phase-locked circuits, a dead zone occurs and operation becomes unstable, and during phase synchronization, accurate synchronization cannot be achieved due to poor response characteristics, resulting in a one-phase shift. There was a problem.

The present invention was made to solve the above-mentioned problems, and can avoid the open loop state of the phase locked circuit when the phase difference is near zero, that is, the generation of a dead zone, and can also cope with phase pull-in that requires a large current. It is an object of the present invention to provide a phase synchronization circuit capable of synchronizing accurately during one phase synchronization.

Another object of the present invention is to provide a charge pump suitable for the above phase locked circuit.

Furthermore, another object of the present invention is to provide a method of operating the above-mentioned phase locked circuit.

[Means for Solving the Problem] The present application provides the following invention as a means for achieving the above object.

A first invention includes a phase comparator that detects a phase difference between an external input signal and an oscillation signal of a voltage controlled oscillator, a charge pump that charges and discharges a current according to an output signal of the phase comparator, and a charge pump that charges and discharges a current according to an output signal of the phase comparator. In a phase locked circuit comprising a loop filter that smooths an output current to generate a control voltage for the voltage controlled oscillator, and the voltage controlled oscillator that changes the frequency of an oscillation signal by the control voltage of the loop filter.

The above charge pump is provided with one used for phase pull-in and another used for phase synchronization.

Each charge pump is characterized by having a charge current source and a discharge current source whose charging operation and discharging operation are switched by a switch.

Further, a second invention is a phase-locking charge pump used in a phase-locked circuit, which includes a charge current source and a discharge current source, and one of which is configured to perform a charge operation and a discharge operation of the charge pump. The present invention is characterized in that it is provided with a switch for switching the operation, and is further provided with a disabling means for substantially disabling the operation except during phase pull-in.

Furthermore, a third invention is a method of operating a phase locked circuit.

During phase pull-in, charge and discharge operations are performed primarily by the charge pump for phase pull.

At the time of phase synchronization, the operation of the phase locking charge pump is stopped or the current value is suppressed, and the phase synchronization charge pump performs charging and discharging operations.

Similar to the charge pump of the second invention, the phase-locked circuit of the first invention has a disabler that substantially disables the operation of the charge pump for phase pull-in except during phase pull-in. Preferably, means are provided.

This invalidating means also includes a current switching circuit that controls the charge current source and the discharge current source so as to suppress the current values of the charge current and the discharge current except when the phase is drawn. It can be configured by

This current switching circuit generates a current switching circuit using a read/write signal for setting a read state and a write 1-state and a pull-in signal for setting a pull-in period, and thereby controls each of the above current sources. It is preferable to have a configuration in which:

The discharge current source provided in the charge pump of each of the above inventions is separated into an original discharge current source and a current source for canceling the charge current of the charge current source.

It is preferable that each of them be provided with a switch for switching between a charging operation and a discharging operation of the charge pump.

It is preferable that the separately provided switches are constituted by semiconductor circuits having the same structure. For example, each switch separated.

It can be configured to be aligned with an NPN transistor or configured to be aligned with a PNP transistor. Preferably, it is composed of an NPN I-transistor.

[Function] The invention of the present application has two types of charge pumps, one used for one phase pull-in and one used for phase synchronization. It would be possible to accurately handle phase synchronization, which requires accurate synchronization without causing a phase shift.

In the phase pull-in process, it is necessary to draw in the phase of the ■C○ clock with respect to the read signal at high speed, and the INC11 current and DEC current are increased in order to increase the loop gain. On the other hand, in the one-phase synchronization process, the INC current and DEC current are made smaller than in the phase pull-in process because it is necessary to stably follow the VCO clock with respect to the read signal. Therefore, by providing charge pumps for phase pull-in and phase synchronization, the INC current switch and DECfl flow switch can be changed to fr! , the switching speed can be increased because it can be configured appropriately according to the current value. As a result, a high-performance charge pump can be constructed, so that the one-phase synchronized circuit is always kept in a closed loop state, and the tracking characteristics are not deteriorated.

As a result, the operating characteristics shown in FIG. 8 are obtained.

In addition, the current value of the current source of the charge pump for phase pull-in is switched between the phase pull-in period and the phase synchronization period 11■, that is, a large current is passed only during one phase pull-in period, and a small current value is set during the other periods. By doing so, it is possible to achieve a significant reduction in power consumption.

Also, INCWi style switch and DEC? 1! A pair of flow switches with the same size NPN type! - By using transistors, the characteristics of the charge current and discharge current can be matched, so a high-performance charge pump circuit can be obtained.

Furthermore, in one aspect of the present invention, the charge pump has a canceling type structure, and the side having a canceling current source, for example,
A changeover switch is provided on the discharge current source side,
Charge operation and discharge operation can be switched. As a result, the INC current and DECfli current are reduced to 1
Even when the phase difference is near zero, continuous transition can be achieved without creating a dead zone.

[Embodiment] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows an outline of a phase locked circuit which is an embodiment of the present invention. Note that the VCO is not shown in FIG. 1. A known vCO can be used.

The phase synchronized circuit of the embodiment shown in FIG. Smoothing the output currents of the phase pull-in charge pump 2II and phase synchronization charge pump 2N that charge (flow out) and discharge (draw) current, and these charge pumps 2H and 2N,
A loop filter 3 that generates a control voltage for vCo (not shown in FIG. 1), a current switching circuit 4 that switches the discharge current value of the charge pump 2H based on a read/write signal 18 and a pull-in signal 19; The filter 3 is configured to include a VCO connected after the filter 3.

The phase comparator 1 receives the read signal 11 and the vC○ clock 1.
2, INC signal 13H and DE during phase pull-in
C signal 14H1 and INC signal 13N during phase synchronization
and a DEC signal 14N are generated and sent to the respective charge pumps 2H and 2N.

The charge pump 2H for phase pulling, the charge current source 21H, the discharge current sources 22H, 32H,
INC? tl flow switch 26I (and DEC'W
It is composed of a first-stream switch 27H. Furthermore, the configuration of the phase synchronization charge pump 2N is as follows:
Similarly to H, it is configured with a charge current source 21N, discharge current sources 22N and 32N, an INC current switch 26N, and a DEC current switch 27N.

Specifically, the charge pumps 2H and 2N have a configuration as shown in FIG. 2. Note that the circuit configuration shown in FIG. 2 is that of a phase pull-in charge pump 2H having a Wi flow switching function.

The charge current source 21H is a PNP transistor Q2.
Discharge current source 3 with Q3 and resistors R3 and R4
2H, 22H is Q8. Each is composed of R5 and Q9°R6. The INC current switch is a pair of NPN type 1 transistors Q4, Q5, and the DECflt current switch is a pair of NPN type 1 to Q6 transistors. Consists of Q7. The transistors Q2 and Q3 constitute a current mirror circuit.

The current switching circuit 4 controls the discharge current sources 22H and 32 by the read/write signal 18 and the pull-in signal 19.
It is provided to switch the current value of H. That is, as shown in FIG.

An OR gate 41 that logically ORs the read/write signal 18 and the pull-in signal 19, a parallel resistance circuit of resistors R2 and R1 including a transistor Q1 that is on/off controlled by a current switching signal 42 output from the OR gate 41; By the output of the parallel resistance circuit, the above charge current 'r
X21YI and discharge current sources 22H, 32H
The transistor Qll controls the current value of the transistor Qll, and the transistor QIO is controlled by the transistor Qll.

The INC current and the DECffi current can be set by resistors R1 and R2 of the current switching circuit 4. Here, the relationship between resistors R1 and R2 is R1>R2. When transistor Q1 is off, the current is approximately (-Vcc-Vp)/R
It becomes 1. On the other hand, during the phase pull-in period, the transistor Q1 is turned on.

becomes. Therefore, the current factor can be set larger when the transistor Q1 is on than when it is off.

The transistor Qll is the one transistor QIO
and the discharge current source 22H.

Transistor Q8.32H. A current mirror circuit is formed with Q9.

Next, the operation of this embodiment will be explained with reference to FIGS. 3 and 4.

First, the operation of the phase comparator 1 will be explained with reference to the timing chart of FIG.

When the VCO clock 12 is input to the phase comparator 1 at the timing shown in the figure in response to the read signal 11, the phase comparator outputs an INC signal 13 and a DEC signal 14. INC signal 13 is.

The rising edge of the read signal 11 causes it to go low, and the falling edge of the VCO clock 12 changes it to high level. On the other hand, DEC (if number 14 is a readout signal 11 with a constant pulse width corresponding to the data transfer rate)
This corresponds to

According to the INC signal and DEC signal, charge and discharge currents 15 are output from charge pumps 2H and 2N, respectively.

Note that in one phase synchronization period and phase pull-in period, I N
Cf! The magnitudes of the i and DECflX flows are different.

For this reason, in this embodiment, the corresponding charge pumps 2H and 2N are used separately. Therefore, the above-mentioned INC signal and DEC signal are respectively applied to the charge pump 2.
13H for H, 2N.

It is output as 13N and 14H, 14N.

Next, the charge pump operation for the one-phase synchronization charge pump 2N will be explained.

(Left below) If the phase of the read signal is ahead of the phase of the VCO clock, the charge current source 2
Since the charging operation is performed by 1N, both the INC current switch 26N and the DEC current switch 27N are opened. Conversely, when the phase of readout No. 43 lags behind the phase of the vCo clock, the loop filter 3 is discharged by the discharge current source 22N, so both the INCfu current switch 26N and the DEC current switch 27N are closed.

That is, in this circuit system, the current of the charge current source 21N is canceled by the discharge current source 32N. Therefore, in this current canceling type charge pump 2N, the output charge amount becomes zero when the phase difference is close to zero (dead zone), which is a problem with the conventional technology.
Never.

When reading data from a disk, v
There is a phase pull-in state for quickly matching the phase of the CO clock. In this case, INC of charge pump 2H
The loop gain is increased by increasing the It current and the D E CWi current.

Next, when the phase pull-in is completed, in order to output valid read data, the charge pump is switched from the phase pull-in mode to the phase synchronization mode and a 1-phase synchronization process begins. In this phase synchronization process, since the VCO clock stably follows the readout signal, the I
Reduce NCff1 flow and DECffi flow.

Next, the operation of the current switching circuit will be explained with reference to FIG.

In the current switching circuit 4, by inputting the read/write signal 18 and the pull-in signal 19 to the OR gate 41,
A current switching signal 42 is obtained. This current switching signal 42 becomes low level when both input signals 18 and 19 are low level.

When this current switching signal 42 becomes low level.

Transistor Q1 turns on. As a result, the resistances R1, R
The current consumption of the parallel resistance circuit consisting of 2 increases. Along with this, transistor Q8. The base currents of Q9 and Qlo increase.

Therefore, the discharge current value of the discharge current sources 32H and 22I can be increased.Similarly, the current of the transistor Q2 connected in series with the transistor QIO also increases, and a current mirror circuit is formed with the transistor QIO. The current in transistor Q3 also increases,
The charging current value can be increased.

In the above embodiment, the NPN transistor Q4 shown in FIG. Q5. Q6. By making the structure and size of Q7 the same, switching characteristics can be matched.

As a result, a high-performance charge pump can be realized.

[Effects of the Invention] As explained above, according to the present invention, it is possible to avoid the open loop state of the phase locked circuit when the phase difference is near zero, that is, the generation of a dead zone, and it is also possible to cope with phase pull-in that requires a large current. At the same time, it becomes possible to achieve accurate synchronization during phase synchronization.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic configuration of an embodiment of the present invention, FIG. 2 is a circuit configuration diagram showing a charge pump circuit and a current switching circuit used in an embodiment of the present invention, and FIG. 3 is a block diagram showing a schematic configuration of an embodiment of the present invention. FIG. 4 is a timing chart showing the operation of the current switching circuit, FIG. 5 is a block diagram showing the general configuration of the phase locked circuit, and FIG. 6 is the conventional one. FIG. 7 is a block diagram showing the circuit configuration of the phase-locked circuit, FIG. 7 is a graph showing the operating characteristics of the conventional phase-locked circuit, and FIG. 8 is a graph showing the operating characteristics of the phase-locked circuit of the present invention. 1... Phase comparator, 2I (... charge pump for phase pull-in, 2N... charge pump for phase synchronization, 3
...Loop filter, 4...Current switching circuit, 5...
-VCO (voltage controlled oscillator), 21H, 21N...Charge current source, 22H, 22N, 32H, 32N. ...discharge current source, 26H, 26N...I
N Cflil inflow switch, 27II, 27N...D
EC current switch.

Claims (1)

[Claims] 1. A phase comparator that detects a phase difference between an external input signal and an oscillation signal of a voltage controlled oscillator, a charge pump that charges and discharges a current according to an output signal of the phase comparator, and the charge pump that In a phase-locked circuit comprising a loop filter that smoothes an output current of a pump to generate a control voltage for the voltage-controlled oscillator, and the voltage-controlled oscillator that changes the frequency of an oscillation signal by the control voltage of the loop filter, the charge pump There are two types of charge pumps, one used during phase pull-in and the other used during phase synchronization, and each charge pump is configured with a charge current source and a discharge current source whose charging operation and discharging operation are switched by a switch. phase-locked circuit. 2. The phase synchronized circuit according to claim 1, wherein one of the charge pumps for phase pull-in is provided with a disabling means for substantially disabling its operation except during phase pull-in. 3. The phase synchronized circuit according to claim 2, wherein the invalidation means includes a current switching circuit that controls the charge current source and the discharge current source so that the current values of the charge current and the discharge current are suppressed except during phase pull-in. 4. The disabling means generates a current switching circuit in the current switching circuit using a read/write signal for setting a read state and a write state, and a pull-in signal for setting a pull-in period, so that each of the above-mentioned 4. The phase locked circuit according to claim 3, which is configured to control a current source. 5. The above-mentioned discharge current source is provided separately into an original discharge current source and a current source for canceling the charge current of the charge current source, and each is configured to switch between the charge operation and the discharge operation of the charge pump. Claims 1 and 2, comprising a switch.
5. The phase locked circuit according to 3 or 4. 6. The phase locked circuit according to claim 5, wherein the separately provided switches are constructed of semiconductor circuits having the same structure. 7. A phase locking charge pump used in the phase-locked circuit according to claim 1, comprising a charge current source and a discharge current source, and one of which is configured to perform a charge operation and a discharge operation of the charge pump. A charge pump characterized in that it is provided with a switching switch, and further provided with a disabling means for substantially disabling its operation except during phase pull-in. 8. The charge pump according to claim 7, wherein the separately provided switches are constituted by semiconductor circuits having the same structure. 9. The method of operating a phase-locked circuit according to claim 1, wherein during phase locking, a charge pump for phase locking mainly performs charging and discharging operations, and during phase locking, the operation of the charge pump for phase locking 1. A method for operating a phase synchronized circuit, characterized in that the current value is stopped or the current value is suppressed, and a phase synchronized charge pump performs charging and discharging operations.