JPH0213274A - Current limiting method for inverter - Google Patents

Abstract

PURPOSE:To limit overcurrent by pruning the central rectangular section of the inverter output voltage waveform. CONSTITUTION:Three-phase output from a generator 2 coupled with an automobile engine 1 is converted into DC power through a rectifier 3 and fed through a voltage regulation circuit 4 to transistors(Tr) Q1 to Q4 constituting the output stage of an inverter. Furthermore, a voltage signal generating circuit 25 for detecting overcurrent flowing through the lines between the voltage regulation circuit 4 and the Tr Q1 to Q4 and providing the detected overcurrent to a hold circuit 9, a pulse oscillator 10, decimal output counters 11, 6 and an input OR gate 12 are provided. Inverting analog switches 13, 14 are arranged at the input terminal of the OR gate 12 and they are controlled through the output from the hold circuit 9 to produce rectangular waves having pause from the output terminals 6a, 6b of the inverter. Furthermore, a signal split section 26 is formed with a NOT gate 20 and AND gates 18, 19. When an overcurrent flows, the central section of the pulse is pruned as the pruned section 27 thus suppressing the load current.

Description

[Detailed Description of the Invention] (Field of Industrial Application) The present invention relates to a current limiting method in an inverter for temporarily limiting the output current when the output of the inverter enters a transient overcurrent state. .

(Conventional technology) Automotive AC power generation that uses the car engine as a power source to generate commercial AC output? t51 is conventionally known.

This automotive alternating current generator is provided with an inverter that exchanges the output generated by the generator into an alternating current output at a commercial frequency. The output stage of this inverter is constituted by a switching element including, for example, four transistors, and since transistors are susceptible to instantaneous overcurrent, the inverter is provided with an overcurrent protection circuit.

<Problem to be solved by the invention> However, whenever a motor connected to the output terminal of the inverter is started or when the load on the motor becomes temporarily heavy, the overcurrent protection circuit is activated and the inverter is There is a problem if the output stops.

By the way, inverters known for starting motors usually use a variable voltage/variable frequency method to reduce overload conditions at startup, but with this method, the output frequency of the inverter changes at startup. This poses a problem when supplying commercial AC power to multiple loads at the same time.

In particular, in automotive AC generators, there are restrictions on the mounting space and weight of the inverter, and it is difficult to install multiple inverters. The condition is that it can be supplied.

Therefore, the present invention was proposed in order to solve such conventional problems, and when the output of the inverter is placed in a transient overcurrent state, the output of the inverter is stopped or the output frequency is changed. An object of the present invention is to provide a current limiting method in an inverter that can temporarily limit the current without changing the current.

Means for Solving the Problems To achieve this object, the current limiting method for an inverter according to the present invention is such that when the output of the inverter is placed in a transient overcurrent state in an inverter that outputs a rectangular wave, The present invention is characterized in that the output current is temporarily limited by thinning out the center portion of the rectangular wave of the output voltage waveform of the inverter.

(Function) According to the present invention, when the output of the inverter is in a transient overcurrent state, the central part of the rectangular wave of the inverter output can be thinned out to temporarily limit the output current.

By thinning out the central portion of the rectangular wave in this way, a large current limiting effect can be obtained, although the output voltage will drop slightly.

Furthermore, even if the center portion of the rectangular wave is thinned out, the commercial frequency of the inverter output will not change.

<Example) Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 shows a circuit diagram of a current limiting device to which a current limiting method according to an embodiment of the present invention is applied.

In FIG. 1, the output of, for example, three-phase 100V generated by a generator 2 connected to an engine 1 of an automobile is:
Once converted into direct current by the rectifier 3 in the inverter, it is then passed through the voltage adjustment circuit 4 to the switching elements such as the transistor QI-
Qs. Note that at the output end of the voltage adjustment circuit 4.

A smoothing capacitor 5 is connected in parallel.

The transistors QI-Qa are transistors Q+,
Qs is turned on, and transistor Q2. Output terminal 6a when Q3 is turned on.

6b so as to generate an output of opposite polarity.

Further, a current detection circuit 7 is provided in series between one line connecting the voltage adjustment circuit 4 and the output stage of the transistors Q+-Qs. The above output terminal 6a.

An overcurrent flowing transiently through a load 8 connected to the load 6b is detected by the current detection circuit 7, amplified, and outputted as a detection signal to a hold circuit 9, which will be described later.

Also, the output of the pulse oscillator 10 is set so that 20 pulses are equal to one cycle of the commercial frequency.

The signal is supplied to a decimal automatic counter 11, which sequentially outputs pulses from the No. 0 output terminal every time a pulse is input. The 0th to 5th output terminals of the counter 11 are connected to input terminals of a six-person OR circuit 12, respectively. Here, the second output terminal and the third output terminal are connected to the OR circuit 12 via inverting analog switches 13 and 14.

The second and third output terminals of the counter 11 are connected to a hold circuit 9 via an OR circuit 15, and the output terminals of the hold circuit 9 are connected to control input terminals of inverting analog switches 13 and 14, respectively. It is connected.

The 6th to 9th output terminals of the counter 11 are as follows:
The terminals are vacant, and as shown in FIG. 2, a rectangular wave having a rest period 16 is outputted from the output terminals 6a and 6b of the inverter.

Further, the No. 0 output terminal of the counter 11 is connected to the input terminal of the TW flip-flop circuit 17, and the output terminal of this T-type flip-flop circuit 17 is connected to the AND(A N
D) It is connected to one input terminal of the circuit 19 and also connected to one input terminal of the AND circuit 18 via the NOT circuit 20.

Furthermore, the output terminal of the six-person OR circuit 12 described above is an AND
are respectively connected to the other input terminals of circuits 18 and 19. The output terminal of this AND circuit 18 is connected to the buffer circuit 21. and the bases of transistors Q+ and Q2 via an inverting buffer circuit 22, respectively, and AN
The output terminal of the D circuit 19 is connected to the buffer circuit 23. and inversion 4
It is connected to the bases of transistors Q3 and Q4 via a 777 circuit 24, respectively.

Here, a pulse oscillator 10, a counter 11 . OR circuit 12
．． 15. Reversing analog switch! 3.14, the hold circuit 9 and the current detection circuit 7 constitute the waveform signal generation section 25, and the NOT circuit 20 and the AND circuits 1B and 19
constitutes the signal dividing section 26.

Next, the operation of the current limiting device configured in this way will be explained.

First, if the current detection circuit 7 does not detect an overcurrent state, the hold circuit 9 sends a signal to the inverting analog switch 13.
．． Since no control signal is output to 14, 1-inverting analog switches 13 and 14 are in a conductive state.

At this time, when pulses are sequentially input from the pulse oscillator 10 to the counter 11, the output terminals of the counter 11 become active (high level) sequentially starting from terminal 0, and the output pulses are sequentially input to the input terminals of the six-man OR circuit 12. It is being done.

The OR circuit 12 calculates the logical sum of the counter outputs, and outputs a timing pulse of No\ level (H level) to the signal dividing unit 26 when the output terminal 5 from the 0fIr output terminal of the counter 11 is sequentially active. do. The pulse width of this timing pulse is the output terminal 6 of the inverter.
This corresponds to the pulse width T of the rectangular wave output from a and 6b.

Further, in the T-type flip-flop circuit 17, the output is inverted every time a pulse is input to the input terminal.

When the No. 0 output terminal of the counter 11 becomes active, an H level output is supplied to the signal dividing section 26, for example. This H level output goes through the output of the counter 11,
This continues until the No. 0 output terminal becomes active again.

Therefore, at this time, the AND circuit 18 of the signal dividing section 26
The output becomes low level (L level), transistor Q1 is turned off, and transistor Q2 is turned on. Also AND
The output of the circuit 19 is at H level during the period when the timing pulse is output from the OR circuit 12, the transistor Q3 is in the on state i, and the transistor Q* is in the off state.

Further, when the output of the counter 11 goes around and the No. 0 output terminal becomes active again, the T-type flip-flop circuit 1
When the output of transistor 7 is inverted and becomes L level, transistor Q+ is turned on, Q2 is turned off, transistor Q3 is turned off, and Q4 is turned on. Then, there is a period (rest time) in which there is no output signal from the OR circuit 12.
In this case, both AND circuits 18 and 19 are at the L level, transistors Q+ and Q3 are turned off, and transistor Q2.94 is turned on, so that the back electromotive force from the load 8 is absorbed.

This operation is repeated thereafter, and the output terminal 6 of the inverter
A and 6b output a rectangular voltage waveform as shown in FIG. This output is set equal to the commercial frequency.

On the other hand, when a transient overcurrent condition is detected by the current detection circuit 7, such as when a load 8 such as a motor is started, the hold circuit 9 to which the detection signal of the current detection circuit 7 is supplied receives the 21I of the counter 11. Only during the period when it is detected by the output of the OR circuit 15 that the output terminal and the No. 3 output terminal have become active, the control input terminal of the inverting analog switch 13.
11 control signal is output.

As a result, the 1-inverting analog switches 13 and 14 are turned off, and pulses from the second and third output terminals of the counter 11 are no longer supplied to the OR circuit 12.
The OR circuit 12 outputs a timing pulse in which the center portion of the pulse width T is missing and the timing pulse is at zero level.

Therefore, from the output terminals 6a and 6b of the inverter,
As shown in FIG. 3(a), an output is obtained in which the central portion of the rectangular wave of the output voltage waveform is thinned out. In addition, in FIG. 3(a), the part 27 indicates the thinning part. By thinning out the central part of the voltage waveform in this way, the current flowing to the load 8 is as shown in FIG. 3(b). As a result, the output current is temporarily limited. Note that the current waveform shown by the dotted line in FIG. 3(b) shows the current flow when no thinning is performed. When such an excessive current IO flows, the output is turned off to protect the transistors QI-Q4. Temporarily stopped (trip state)
I will have to.

Thinning out the central part of the output voltage waveform as described above is
Although the output voltage slightly decreases, a large current limiting effect can be obtained. Even if the central portion of the waveform is thinned out, the output of the inverter remains at the commercial frequency and does not affect the unspecified number of negative W8s.

In the above-described embodiment, the hold circuit 9 is provided to keep the 1-inversion analog switches 13 and 14 in the OFF state for a certain period of time even if the overcurrent state is temporarily removed. It may be configured such that the inverting analog switches 13 and 14 are turned off only when the current flowing through the load 8 is in an overcurrent state without providing the above.

Further, in the above-described embodiment, the current limiting method according to the present invention is applied to an inverter of an automotive AC generator, but it can also be applied to an inverter of other devices.

(Effects of the Invention) As explained above, according to the present invention, by thinning out the central part of the rectangular wave of the output voltage waveform of the inverter, current is temporarily limited at the time of overcurrent, so that the output voltage is reduced. Although it decreases slightly, a large current limiting effect can be obtained.

Conventionally, a protection circuit was activated to stop the inverter output when an overcurrent occurred, but the present invention can eliminate this problem.

Furthermore, even if the central portion of the rectangular wave output is thinned out, the output frequency of the inverter will not change, so it is suitable for a general-purpose power source that simultaneously supplies commercial power to an unspecified number of loads.

According to the present invention, although the electromotive time is somewhat longer for an object with a large electromotive load such as a motor, it is possible to shift to a stable state while limiting the starting current.

Further, even when a plurality of loads are in use, or when a load having a large capacitor is additionally connected, the inrush current when the power is turned on can be limited by the present invention.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a current limiting device to which a current limiting method for an inverter according to the present invention is applied. Figure 2 is a voltage waveform diagram output from the inverter during normal times, Figure 3 (a) is a voltage waveform diagram output from the inverter during overcurrent, and w43 Figure (b) corresponds to Figure 3 (a). It is a voltage waveform diagram. 1 is the engine, 2 is the generator, 3 is the rectifier, 4 is the voltage adjustment circuit, 6a, 6b are the output terminals, 7 is the current detection circuit, 8 is the load, 9 is the hold circuit, 1O is the pulse oscillator, 11 is the decimal notation Power type counter, 12 is 6-man power OR circuit, 13.1
4 is an inverting analog switch, 15 is an OR circuit, 17 is a Tfi flip 7o +7 pull circuit, 18.19 is an AND
circuit, 2o is the N07 circuit, 21.23 is the buffer circuit,
22. 24 is an inverting buffer circuit, 25 is a waveform signal generation circuit, 26 is a signal dividing section, 27 is a thinning section, Q1 to Q4
is a transistor.

Claims (1)

[Claims] In an inverter with a square wave output, when the output of this inverter is placed in a transient overcurrent state, the output current is temporarily limited by thinning out the center part of the rectangular wave of the output voltage waveform of the inverter. A current limiting method in an inverter characterized by the following.