JPH02134828A - Manufacture of schottky barrier junction gate type field effect transistor - Google Patents

Abstract

PURPOSE:To acquire a small source resistance and a large drain pressure resistance by providing an N<+> type GaAs crystal layer by performing epitaxial growth only for a source electrode side. CONSTITUTION:After an N-type GaAs operation layer 12 is formed on a semi- insulating GaAs substrate 11, a gate electrode 13 consisting of Schottky barrier junction metal is formed on the operation layer 12. Impurity which acts as a donor in GaAs is ion-implanted at least to a drain region on the operation layer 12. Then, an insulating film 15 is formed all over, a photoresist film 16 is formed thereon, and patterning is carried out to form an opening section in a source region and a source region on the gate electrode 13. After the insulating film 15 is etched through anisotropic dry etching method using the photoresist film 16 which is provided with an opening as a mask, a GaAs crystal layer 19 of high concentration N-type is formed selectively through epitaxial growth method using the remaining insulating film 15 and the gate electrode 13 as a mask.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a Schottky barrier junction gate type field effect transistor.

[Conventional technology]

A Schottky barrier junction gate field effect transistor, particularly a GaAs Schottky barrier junction gate field effect transistor (hereinafter referred to as MESFET) using an n-type gallium arsenide (hereinafter referred to as n-type GaAs) crystal layer as an active layer, It has been developed and commercialized as a high frequency/amplification element.

In order to improve the performance of GaAsM ESFETs, it is important to reduce parasitic resistance such as source resistance and maintain a high breakdown voltage.

FIG. 3 is a cross-sectional view of a semiconductor chip shown in order of steps for explaining a conventional method of manufacturing a GaAsME SFET.

First, as shown in FIG. 3(a), by implanting St ions into a semi-insulating GaAs substrate 11, the carrier concentration I
After forming an n-type GaAs active layer 12 with a thickness of 10 cm and a thickness of 0.2 μm, a high melting point metal (for example, tungsten) with a thickness of 0.6 μm is formed to form a Schottky junction with the n-type GaAs active layer 12. A gate electrode 13 made of (silicide) is formed. Next, an insulating film 15 made of 5i02 or the like is deposited over the entire surface by CVD or the like.

Next, as shown in FIG. 3(b), photoresist I is applied to the entire surface.
- After forming the film 14A, patterning is performed to form openings on the drain region 31, source region 30, and source region side above the gate electrode 13.

Next, as shown in FIG. 3(C), the insulating film 15 is etched by an anisotropic dry etching method using the photoresist film 14A in which this opening is formed as a mask.
The photoresist film 14A is removed.

Next, as shown in FIG. 3(d), using the gate electrode 13 and the remaining insulating film 15 as a mask, St as an impurity serving as a donor is ion-implanted into the GaAs to form an n1 type Ga.
As region 18 is formed.

Next, using the gate electrode 13 and the remaining insulating film as a mask, as shown in FIG. 3(e), the carrier density is 5×
An n+ type GaAs crystal layer 19 of 1018 cm-' is selectively grown epitaxially, and finally this n+ type GaAs crystal layer 19 is grown epitaxially.
Source electrode 2 making ohmic contact with crystal layer 19
0 and a train electrode 21 are formed, and GaAsM E S
Complete FET.

[Problem to be solved by the invention]

GaAsFET is used by first grounding the source electrode, setting the drain electrode to a positive potential, and biasing the gate electrode to a negative potential. When a voltage is applied, the drain current increases rapidly, and good FET characteristics are no longer exhibited.

This critical voltage is called drain breakdown voltage, and especially for high-output FETs, improving this drain breakdown voltage is important for improving performance, such as raising the output power limit and improving reliability.

However, Ga produced by the conventional production method mentioned above
In the AsM E S F E T, the n+ type Ga crystal layer 19 with a high concentration of carrier density of 5 x 10 l8 cm-3 was provided under the drain electrode 21, so the critical electric field that causes avalanche breakdown of the crystal is small. However, the drain breakdown voltage was only about 10V, which was insufficient as a high-output FET.

[Means to solve the problem]

The method for manufacturing a Schottky barrier junction gate field effect transistor of the present invention is to fabricate an n-type G field effect transistor on a semi-insulating GaAs substrate.
After forming the aAs active layer, forming a gate electrode made of a Schottky barrier junction metal on the n-type GaAs active layer, and acting as a donor in GaAs in at least the drain region on the n-type GaAs active layer. a step of forming an insulating film on the entire surface after ion-implanting impurities; a step of forming a photoresist film on the insulating film and patterning it to form an opening on the source region side above the source region and the gate electrode; a step of etching the insulating film by an anisotropic dry etching method using the photoresist film on which a portion has been formed as a mask, and selectively etching the high concentration n-type by an epitaxial growth method using the remaining insulating film and the gate electrode as a mask. The method includes a step of forming a GaAs crystal layer.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1A to 1G are cross-sectional views of a semiconductor chip shown in order of steps for explaining a first embodiment of the present invention.

First, as shown in FIG. 1(a), Si ions are implanted into a semi-insulating GaAs substrate 11 at a carrier density of 1×10 17 .
CIO-3, 0.2 μm thick n-type GaAs active layer 12
After forming a gate electrode 13 made of tungsten silicide with a thickness of 0.6 μm, which forms a Schottky junction with the n-type GaAs film 112, a first gate electrode 13 having an opening only on the train region 31 side is formed. A photoresist film 14 is formed.

Next, as shown in FIG. 1(b), using the first photoresist film 14 provided with this opening as a mask, Si as an impurity serving as a donor in gallium arsenide is accelerated by an energy of 1.
After ion implantation is performed under the conditions of 00 keV and a dose of 5×10 12 ions/cI 112 to form an n+ type Ga^S region 18, the first photoresist film 14 is removed.

Next, as shown in FIG. 1(c), after depositing an insulating film 15 with a thickness of 0.3 μm (for example, a SiO3 film by CVD method) 15 on the entire surface, the source region 31 and the source region on the gate electrode 13 are A second photoresist film 16 having an opening on the side is formed.

Next, as shown in FIG. 1(d), using this second photoresist film 16 as a mask, the insulating film 15 is etched by an anisotropic dry etching method, and then the second photoresist film 16 is removed. An insulating film 15 is left on the side surface of the gate electrode 13 on the source region side.

Next, as shown in FIG. 1(e), using the gate electrode 13 and the insulating JI 115 as a mask, St is accelerated with an energy of 1
After ion implantation under the conditions of 00 keV and a dose of 5 x 1012 ions/Cl112, annealing is performed for activation to form an n+ type (iaAs region 17) in the source region 30. At this time, an n+ type GaAs region 18 in the drain region is formed.
is also activated.

Next, as shown in FIG. 1(f), using the gate electrode 13 and the insulating film 15 as a mask, the carrier concentration is 5×1.
An n+ type GaAs crystal layer 19 of 0''cm-3 is selectively epitaxially grown.

Finally, as shown in Figure 1(g), this n+ type GaA
A source ring f making ohmic contact with the s crystal layer 19
! A drain electrode 21 is formed without ohmic contact with the n+ type GaAs region 18 and the GaAsM E
Complete S FET.

In this way, according to the embodiment of Mizui 1, the n+ type GaAs crystal layer that is likely to cause avalanche breakdown on the drain electrode side, where a high electric field is easily applied, is removed, so the train breakdown voltage is improved to about 25V, and the source electrode n+ type GaA on the side
Since the s-crystal layer 19 is provided, the source resistance is 0,
A small one of 7Ω open was obtained.

FIG. 2 is a cross-sectional view of a semiconductor chip shown in the order of steps for explaining a second embodiment of the present invention.

First, as shown in FIG. 2(a), similarly to the first embodiment, Si ions are implanted into a semi-insulating GaAs substrate 11 to form an n-type GaAs layer 112, and then a gate electrode 13 made of tungsten silicide is formed. form. Next, using this gate electrode 13 as a mask, Si ions are implanted at an acceleration energy of 50 keV and a dose of 1.times.10@12 ions/CIn2 to form an n-type GaAs region 22. This is provided to eliminate the phenomenon of overcrowding of mutual conductance. Next, a first photoresist film 14 having an opening in the train region is provided.

Next, as shown in FIG. 2(b), using this first photoresist film 14 as a mask, Si ions are accelerated on the drain side at an energy of 100 keV and a dose of 5x l Q 12
The n+ type Ga S region 18 is formed by implanting under the condition of Ga/cm2. Next, an insulating film 15 having an opening on the source side is formed.

Next, as shown in FIG. 2(C), using the gate electrode 13 and the insulating film 15 as a mask, Si is accelerated at an acceleration energy of 100.
After implantation under the conditions of keV and a dose of 2×10 13 atoms/cm 2 , annealing is performed for activation, and an n + type GaAs region 23 is also provided in the source region 30 . This second
In this embodiment, the source resistance can be reduced compared to the first embodiment by changing the ion implantation conditions on the source region side to the ion implantation conditions on the drain region side.

Next, as shown in FIG. 2(d), using the gate electrode 13 and the insulating film 15 as a mask, the carrier density is 5×1.
An n+ type GaAs crystal layer 19 of 018 cm-3 is selectively epitaxially grown.

Next, after removing the insulating film 15, as shown in FIG. 2(e), a second insulating film M24 made of 5i02 or the like is formed, and then a second photoresist film 16 is formed on the entire surface.

Next, as shown in FIG. 2(f), the insulating film 24 and the second photoresist film 16 are etched back by dry etching to expose the upper surface of the gate electrode 13.

Next, as shown in FIG. 2(g), a low-resistance metal layer (for example, a stack of titanium, platinum, and gold) is deposited, and then patterned by dry etching to form a low-resistance metal layer on the gate electrode 13. 25 will be provided.

Finally, as shown in FIG. 2(h), a source electrode 20 and a drain electrode 21 are formed without ohmic contact with the n1 type GaAs crystal layer 19 and the n+ type GaAs region 18, and the GaAsM E S F E T is formed. Finalize. GaAsM E S F E T produced in this way
has the advantage that the source resistance and gate resistance are smaller than the GaAsM ESFET of the first embodiment.

In the above embodiment, the gate electrode is made of tungsten silicide, but the invention is not limited to this, and W, Mo, and their silicides may also be used. Although Si was used as the acting impurity, Sn may also be used.

〔Effect of the invention〕

As described above, the present invention provides a Schottky barrier junction gate field effect transistor with low source resistance and high drain breakdown voltage by providing an n+ type GaAs crystal layer only on the source electrode side by epitaxial growth.

[Brief explanation of the drawing]

1 and 2 are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the first and second embodiments of the present invention, and FIG. FIG. 2 is a cross-sectional view of a semiconductor chip shown in the order of steps for explanation. 11...Semi-insulating GaAs substrate, 12...n-type Ga
As operating layer, 13... Gate electrode, 14... First photoresist film, 15... Insulating film, 16... Second photoresist film, 17.18-n+ type GaAs region,
19 - n + type GaAs crystal layer, 20 - source electrode, 21 - drain electrode, 22 - n type GaAs region, 23 - n + type GaAs region, 24 - second insulating film, 25 - . . . low resistance metal layer, 30 . . . source region,
31...Drain region. 30V-Sui 1 Takumi Figure voice? Seki sword diagram

Claims (1)

[Claims] forming an n-type GaAs active layer on a semi-insulating GaAs substrate and then forming a gate electrode made of a Schottky barrier junction metal on the n-type GaAs active layer; A process of ion-implanting an impurity that acts as a donor in GaAs into the region and then forming an insulating film on the entire surface, and forming a photoresist film on the insulating film and patterning it on the source region and the source region side above the gate electrode. a step of forming an opening, a step of etching the insulating film by an anisotropic dry etching method using the photoresist film in which the opening has been formed as a mask, and epitaxial growth using the remaining insulating film and the gate electrode as a mask. 1. A method of manufacturing a Schottky barrier junction gate type field effect transistor, comprising the step of selectively forming a highly doped n-type GaAs crystal layer by a method.