JPH02128449A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form uniformly connecting holes, to hold almost constantly an interlayer insulating distance and to contrive the speedup of a device by a method wherein a dummy pattern is provided on a wiring non-formation region and the step difference of a base layer is relaxed. CONSTITUTION:An insulating film 2 is formed on the surface of a semiinsulative GaAs substrate 1 and a layer wiring 3 is formed on the upper part of the film 2. Then, a resist 4 is applied on the substrate surface, is exposed and developed in a pattern larger than that of the wiring 3 to obtain a resist pattern 4 for flattening use and this pattern is cured. Then, a resist 5 for connecting hole formation use is applied. At this time, the heights up to the surfaces of the resist 4 and the wiring 3 are nearly the same height and the film thickness of the resist 5 becomes uniform. An exposure and a developing are performed on the resist 5 to obtain connecting holes (W1 and W2), whose aperture dimensions are almost equal. Then, an upper layer wiring 6 is formed and the resists 4 and 5 are removed to obtain an air bridge wiring structure.

Description

Detailed Description of the Invention [Objective of the Invention] (Industrial Application Field) The present invention relates to a method of manufacturing a semiconductor device, and particularly relates to an air bridge (air bridge) in which the layers of multilayer wiring are insulated and separated using air or another type of gas. Related to the manufacturing method of the wiring) structure.

(Prior art) The layers of multilayer wiring are insulated and separated using air or another type of gas. So-called aerial wiring (air bridge wiring) is advantageous for increasing speed because it can reduce the capacitance of upper layer wiring and the crossover capacitance of alternating parts, and is especially used for devices such as GaAsFETs that feature high-speed operation and want to reduce parasitic capacitance. It is being Although this technology is naturally promising as a multilayer interconnect for LSI, several problems arise in this case. FIG. 2 shows a conventional method for manufacturing air bridge wiring. A first layer wiring (3) is formed on a semiconductor substrate (1) and an insulating film (2) formed on the surface thereof. (Fig. 2 (a)) After this, a photoresist (4) is applied to the entire surface to form a connection part (contact hole) between the lower layer and the upper layer wiring and to insulate and isolate the upper layer and the lower layer wiring (Fig. 2 (a)). b)). Connecting holes are made in this resist by exposure and
It is formed by development (FIG. 2(C)). Subsequently, upper layer wiring (6) is formed on this resist (Figure 2(d)).
.

Finally, the photoresist (4) is removed to complete the air bridge structure (FIG. 2(e)).

However, in the wiring pattern of an LSI, the wiring width is not constant as shown in FIG. 2(a).

For this reason, when a photoresist is applied on top of this, due to the flattening effect of the resist, as shown in Figure 2(b),
The resist is formed thinly on thin wiring, and thickly formed on thick wiring. That is, in Fig. 2(b), d <
d and d<d3.

When exposing the connection hole in such a state, the optimum exposure amount for the resist depends on its film thickness, so the optimum exposure amount varies depending on the location. For example, if the exposure amount is set for a thick part with a thickness of d2, d1tq) will result in overexposure, and as a result, the sizes of the openings formed (W1 and W2 in FIG. 2(C)) will be different, making it difficult to control the process. Furthermore, the film thickness of this photoresist plays an important role in determining the separation distance between the lower layer and the upper layer wiring, but if the film thickness varies depending on the location due to the above-mentioned reasons, it may occur as shown in Fig. 2(d) to (e). )
As shown in the figure, the distances between d and d4 are different, and as a result, the capacitance of the alternating portions varies depending on the pattern. This complicates the design of the device, and also reduces the capacitance reduction effect of the air bridge structure, especially in areas where the resist is thin, such as d4, making it impossible to obtain the expected performance. .

These problems can be alleviated to some extent by making the resist (4) thicker, but this requires a thickness approximately three times the wiring film thickness. In other words, the wiring film thickness is 0.6μ
A resist with a thickness of about 2 μm is required.
This hinders miniaturization when forming connection holes, making C4) unsuitable for high integration.

(Problems to be Solved by the Invention) As described above, in the manufacturing method of the conventional technology, due to non-uniformity of the resist film thickness due to the step difference in the underlying wiring,
It is difficult to control the opening size of the connection hole, which causes a decrease in manufacturing yield, and it is difficult to control the space between the lower and upper layers, making device design difficult and not achieving the expected capacity reduction effect. there is a possibility. There was a problem.

[Structure of the Invention (Means for Solving the Problems) The present invention provides a method for solving the problems when applying the above-mentioned air bridge wiring to LSI, and more specifically, , in the area where wiring is not formed,
A dummy pattern with a thickness similar to that of the wiring film is provided, and a resist for forming connection holes is applied with the level difference in the base layer relaxed, and the film thickness is approximately equalized.

(Function) According to the present invention, the formation of the connection hole can be made uniform regardless of the difference in level between the substrates, leading to an improvement in manufacturing yield. Also,
The interlayer insulation distance (space) between the lower and upper layers can also be kept approximately constant, making device design easier, and the air bridge structure provides the expected capacitance reduction effect, achieving faster device speeds. can.

(Example) An example of the manufacturing method of the present invention will be described in detail below with reference to FIG.

Using a semi-insulating GaAs substrate (1) as a semiconductor substrate,
An insulating film is placed on the surface and SiO2(2) is 5oooX
It is formed to a thickness of . The process is the same as the conventional example up to the point where a 0.8 μ thick Ti/Pt/Au layer is formed as a first layer wiring on top thereof by patterning by ion milling (FIG. 1(a)). Although not shown in this figure, there are FETs and FETs on the GaAs substrate (1).
Elements such as diodes are formed.

Next, a resist (4) is applied to the surface of this substrate to a thickness of 0.8 μm, and exposed and developed in a pattern that is one size larger than the first layer wiring (3), as shown in Figure 1(b). A resist pattern (4) is obtained. In this example, the resist (4) was exposed using a mask 1.0 μm wider than the wiring pattern so that the space between the resist (4) and the wiring (3) would not affect the subsequent planarization effect. .

Subsequently, the resist (4) is cured by beta at 150° C. for 30 minutes so that this resist does not dissolve when the upper resist is applied.

After this, a resist (5) for forming connection holes is applied (FIG. 1(C)). At this time, the 1.0 μm space between the planarization resist (4) and the wiring (3) is filled by the planarization effect of the upper layer resist (5), and the planarization resist (
4) and the surface of the wiring (3) are approximately at the same height, so the film thickness of the resist (5) applied thereon is as shown in Figure 1 (C).
It becomes uniform as shown in the figure, and the main part thickness in the figure is d1 ~ d2 ~
d3 to d4 are satisfied.

This resist is exposed and developed to open connection holes in the required areas, but since the resist (5) film thickness is approximately the same regardless of the width of the wiring, the optimum exposure amount is independent of the underlying pattern. Since it is almost constant over the entire surface, the connection holes with almost equal opening dimensions (i.e., W1 to
W2) is obtained.

After this, Au was formed to a thickness of 1.0 μm as the upper layer wiring (6) (Fig. 1(e)), and finally resist (4) (
5) is removed using an organic solvent and 0□ Ashing to complete the air bridge wiring structure (FIG. 1(C)). At this time, the resist film thickness on the lower layer wiring becomes approximately constant due to the flattening effect mentioned above, so the space d between the lower layer and the upper layer wiring is
, d is determined by the film thickness of the cyst (5), and the expected distance can be obtained with good uniformity.

[Effects of the Invention] According to the present invention, a resist for opening connection holes and determining the distance between upper and lower layers can be coated on a flattened base, and the film thickness can be made substantially the same regardless of the base pattern. can be formed. As a result, the controllability of the process regarding the opening of the connection hole is greatly improved, and the manufacturing yield is improved. In addition, since it is possible to form a substantially constant distance between the upper and lower layers without depending on the underlying pattern, device design becomes easier, and the capacitance reduction effect achieved by using an air bridge wiring structure can be obtained as expected. , it becomes possible to achieve faster device speeds.

In particular, the present invention is extremely effective in highly integrated devices such as ICs and LSIs in which the underlying pattern shape is complex and its density is not constant.

[Brief explanation of drawings]

FIG. 1 is a sectional view for explaining a method of manufacturing an air bridge wiring according to an embodiment of the present invention. FIG. 2 is a cross-sectional view for explaining a conventional method of manufacturing air bridge wiring. 1...GaAs substrate 2...
・・・・・・SiO2 film 3・・・・・・・・・・・・
1st layer wiring 4.5...Photoresist 6......Upper layer wiring

Claims (3)

[Claims] (1) A step of forming a metal wiring pattern on a semiconductor substrate, a step of forming a dummy pattern with approximately the same thickness as the metal wiring in an area other than the wiring pattern, and a step of forming a photoresist on the metal wiring and the dummy pattern. The photoresist is characterized by comprising the steps of applying the photoresist, patterning connection holes in the resist, forming an upper layer metal wiring that connects to the metal wiring through the connection holes, and removing the photoresist. A method for manufacturing a semiconductor device. (2) The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is GaAs. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the dummy pattern is formed by applying a resist, exposing and developing a pattern substantially the same as or slightly larger than the wiring pattern.