JPH02128201A - Programmable controller - Google Patents

Abstract

PURPOSE:To attain a high speed communication processing by connecting a transfer-only processor to a common bus and directly reading and writing a transmission/reception signal from and into a memory without through a bus interface. CONSTITUTION:The transfer-only processor 500 is connected to the common bus 100 and the transmission/reception signal is directly read and written from and into the memory 200 without through the bus interface. Consequently, the selecting processing of a connecting transmission line with respect to the bus interface is eliminated compared to a conventional programmable controller which reads from and writes into the memory 200 through the bus interface, and the communication processing is shortened for the processing time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a programmable controller that sends and receives operation control signals to and from controlled equipment.

(Prior Art) FIG. 5 shows the configuration of a communication circuit of a generally well-known programmable controller.

In FIG. 5, when the programmable controller receives data signals to be subjected to sequence calculations from a plurality of devices to be controlled, the CPIII instructs the bus interface 8 which Ilo should be connected to the mother bus,
The corresponding I10 bus m and mother bus l are connected.

The signal sent from the device to be controlled is converted by the interface (Ilo) 7 from a serial signal to a parallel signal, or the voltage level of the signal is converted from a transfer level to a control processing level, and the I10 bus m, bus Interface 8, mother bus (common bus)
The zero-order CPIII sent to the CPUI via the JZ identifies the contents of the received signal, such as the numerical value and control command, and writes the identification result into a specified area of the data memory 5 corresponding to the device to be controlled.

Thereafter, cput repeats the above-mentioned procedure, sequentially reads data signals from the second l107, and then writes them into the data memory 5. Next, when the data signal reception processing is finished, the CPIII executes the sequence program created by the user based on the data signal stored in the data memory 5, writes the calculation results to the data memory 5, and then sends the data to the data memory 5. Information to be transmitted to each controlled device is sequentially read from the memory 5, and a control signal instructing the controlled device to operate is sent via the bus interface 8 and l107.

(Problem to be Solved by the Invention) However, in conventional programmable controllers, for example, in reception processing, it is not possible to send data signals directly from the bus interface 8 to the data memory 5. The signal must be read and the read data signal must be written to the data memory.

As a result, each time the bus interface 8 and data memory 5 are accessed, the CPljl must perform a complicated control operation of sending an address signal, write signal, read signal, and data signal to the communication-related circuits in a time-series manner. , there was a problem that communication processing took time.

Therefore, the purpose of the present invention is to eliminate such problems and provide a programmable controller that can execute communication processing with controlled equipment at higher speed by directly reading and writing signals sent and received from multiple interfaces to memory. It is about providing.

(Means for Solving the Problems) In order to achieve such an object, the present invention provides a memory that is connected to a common bus and stores a booter for sequence calculations, and a memory that is connected to a common bus and reads data from the memory. A sequence calculation processor that executes sequence calculations and writes the calculation results to memory, and has two signal input/output terminals, one of which is connected to a plurality of signal transmission paths to a plurality of external control target devices. and connect the other signal input/output terminal to the common bus, and send/receive signals to and from multiple external control target devices through the signal input/output terminal as sequence operation data in memory according to a predetermined transfer order. and a transfer-only processor that reads or writes data to the data.

[Effect]

In the present invention, the transfer-dedicated processor is connected to a common bus and the transmitting/receiving signals are directly read and written to the memory without going through the bus interface, so compared to conventional programmable controllers that read and write signals to the memory through the bus interface. Since the process of selecting a connection transmission path for the bus interface is not necessary, the communication process is shortened by the processing time, and communication process can be performed faster than before.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows the basic configuration of an embodiment of the present invention.

In FIG. 1, 200 is a memory connected to the common bus 100 and storing data for sequence calculations.

A sequence calculation processor 300 is connected to the common bus, reads the data from the memory, executes the sequence calculation, and writes the calculation result to the memory.

500 has two signal input/output terminals, connects one of the signal input/output terminals to a plurality of signal transmission paths 400 for a plurality of external control target devices, and connects the other signal input/output terminal to the common bus. a transfer-dedicated processor that reads or writes signals transmitted and received between the plurality of externally controlled devices through the signal input/output terminal as data for the sequence calculation to the memory according to a predetermined transfer order; be.

FIG. 2 shows a specific circuit configuration of an embodiment of the present invention.

In FIG. 2, the same parts as in the conventional example shown in FIG. 5 are denoted by the same reference numerals, and detailed explanation thereof will be omitted.

In FIG. 2, 6 is a read-only memory (ROM) for storing the control procedure shown in FIG. 3 related to the present invention during a power outage, and 3 is a read-only memory (ROM) for storing the control procedure shown in FIG. 3 during system operation. This is a random access memory (RAM), and control procedures are transferred from the ROM 6 when the system power is turned on.

Note that since the transfer process of this control procedure is conventionally well known, detailed explanation will be omitted.

Reference numeral 2 denotes an arithmetic circuit (processor) that executes control procedures for communication processing stored in the RAM 3 when the system power is turned on, and in this example, an integrated LSI chip is used. Instead of LSI, it is also possible to use a CPU or an arithmetic circuit having two input/output terminals.

The transfer-only LSI2 has a mother bus λ and an I10 bus m.
, and performs processing for directly writing data signals sequentially read from each l 107 into the data memory 5 and processing for transmitting data signals directly read from the data memory 5 to a predetermined l 107.

This embodiment is provided with a circuit (transfer-only LSI 2) that directly accesses the data memory 5 for signals sent and received from a plurality of Ilo's without going through the bus interface, and during the access, the operation with the CPU is stopped, and the sequence calculation of the CPU 2 The feature is that processing is prohibited.

FIG. 3 shows specific signal contents of the circuit shown in FIG.

In Figure 3, mother bus (common bus) I! , is CP
The next signals that can be output from each of the old and transfer-only LSIs 2 are transmitted to each memory. That is, a read signal that instructs writing to the memory, a write signal that instructs reading from the memory, an address signal that instructs the address area of the memory to be read or written, and a data signal to be read/written are used for reading and writing from each memory.

The signal bus between the transfer-only LSI 2 and the transfer program memory 3 and the connection bus between the transfer LSI and each l107 also have the above-described signal line configuration. Also, when performing communication processing, stop () IOLD from transfer-only LSI 2 to CP old.
) Request HOLD request signal 2A and H from CPUI
The signal IA responding to the OLD request is connected to the CPU 2 and the transfer L
It is exchanged between SI2 and SI2.

Next, the operation of the circuit shown in FIG. 3 will be explained with reference to the flowchart in FIG.

The control procedure shown in FIG. 4 is stored in the transfer program memory 3 when the system is activated, and is sequentially read out from the transfer-only LSI 2 in response to system startup, and is used to perform signal reception processing,
It is repeatedly executed at a fixed period according to the transmission process.

When this control procedure is read out, the transfer-only LSI 2 will perform the LSI specified by the transfer program when performing reception processing.
107 and takes in the data signal from l107. Next, the content of this data signal, e.g. a numerical value,
After identifying the control command, etc., a HOLD request signal 2^ is generated to the CPU (steps s1→S2→S3→S4).
).

After receiving the response signal IA from CPt1l and confirming that the CPUI has stopped, the transfer-only LSI 2 specifies the address of the data memory 5 specified by the control program, generates a write signal, and writes the identification result for the above-mentioned data signal to the data. Write to memory 5 (step S5→S6).

Subsequently, the transfer-only LSI 2 releases the HOLD request signal 2^ that was held as an output, activates the CPDI, and then finishes receiving the signal from the first l107.

Next, the control command of the transfer program is read, and if this control command is for example data transmission processing to the second l107, the transfer-only LSI 2 outputs a HOLD request signal 2A to the CPU 2 (steps 51 to S2→ SO).

Next, after stopping the CPU 1, the LSI 2 specifies the address specified by the transfer program in the data memory 5 and reads out the signal to be transmitted from the data memory 5. It also releases HOLD of CPU2 (step S12→
513). Next, the read signal is converted into a transmission signal that corresponds to the bus protocol or transmission method corresponding to the second l107, and the second l107 is addressed and output (
Step 514).

Thereafter, the transfer program is executed sequentially, and the transfer LSI 2 repeatedly executes data transmission/reception processing and read/write processing for the data memory 5 between each l107.

Furthermore, when the CPU reads the stored contents from the data memory 5 in order to execute a sequence operation, it is sufficient to send a HOLD request signal from the CPDI 2 to the transfer-only LSI 2.
While receiving the OLD request signal, the transfer LSI 2 stops.

In this embodiment, the transfer-only LSI 2 selectively sends and receives data signals from multiple l107s, so the process of specifying the l107 for communication and the process of reading and writing to l107, which were necessary in the conventional example, are performed twice. In this example, only one process is required. As a result, it is clear that the signal communication processing with the controlled device becomes faster.

Regarding the application form of the first embodiment, the following can be considered.

1) In this embodiment, CPt1l for arithmetic processing and LS for transfer
In order for I2 to share the data memory 5, arithmetic processing C
(IOLD request signal between PUI and transfer LSI2)
is sent and received, and one of the arithmetic circuits is stopped.

However, if you want to operate the partner arithmetic circuit in parallel for other processing, enable the bus only between the data memory 5 and the transfer LSI 2 during communication processing, and enable the bus between the data memory 5 and the transfer LSI 2 during arithmetic processing. The connection signal line of the data memory may be switched using a bus separation circuit or a switch so that only the bus with the CPIll is valid.

2) In this embodiment, the transfer program R is
The transfer program is written to AM3 from the ROMB, but the transfer program RAM3 is connected to the keyboard and the data read/write circuit, and the transfer program can be input from the keyboard to the transfer program RAM3, or the stored contents of the transfer program RAM3 can be input using the keyboard. It may be configured so that it can be modified.

In this case, the transfer program can be set variably, so each
The access order to 107 and the storage address of data memory 5 can be determined as desired by the operator without being restricted by the device configuration.

(Effects of the Invention) As explained above, according to the present invention, a transfer-dedicated processor is connected to a common bus and transmit/receive signals are directly read and written to the memory without going through the bus interface. Compared to conventional programmable controllers that read and write signals to memory using the controller, there is no need to select the connection transmission path for the bus interface, so the communication processing time is shortened by the processing time, allowing faster communication processing than before. Can be done.

In addition, by rewriting the control program that drives the transfer-dedicated processor, it is possible to identify signals of various transmission methods and to variably set the signal transfer order by simply changing the software web without changing the hardware configuration. This also has the effect of making it possible.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the basic circuit configuration of an embodiment of the present invention, Figure 2 is a circuit diagram showing a specific circuit configuration of an embodiment of the invention, and Figure 3 is a signal diagram of the circuit shown in Figure 2. 4 is a flowchart showing the operation procedure executed by the transfer-only LSI 2 shown in FIG. 2; FIG. 5 is a circuit diagram showing the circuit configuration of a conventional example; 1...c
po. 2...Transfer-only LSI 3...RAM. 4... System memory, 5... Data memory, 7... Ilo, 8... Path interface. 70 tsuku map of Banni Ming Huangpu Asahi g0 70th diagram ri diagram Kiso Ming × Sei sequence/) colloquial language diagram Figure 2 ne → Euming relief Ding Ba I sequence 0 flowchart Figure 4 i Nongmai I sequence's rotation circle figure

Claims (1)

[Scope of Claims] A memory connected to a common bus and storing data for sequence calculation; A sequence calculation processor for writing in a memory, and two signal input/output terminals, one of which is connected to a plurality of signal transmission paths to a plurality of external control target devices, and the other signal input/output terminal is connected to a plurality of signal transmission paths to a plurality of external control target devices. Connecting the output terminal and the common bus, and reading or writing signals transmitted and received between the plurality of external control target devices through the signal input/output terminal as data of the sequence operation to the memory according to a predetermined transfer order. A programmable controller characterized by comprising a transfer-dedicated processor.