JPH021008A - Reset signal generating device - Google Patents

Abstract

PURPOSE:To reset a device without inputting a signal for reset by using two signal lines of a clock signal having a specific period and a synchronizing signal and generating a reset signal at the time of detecting that the pulse width of the synchronizing signal is wider than a preliminarily determined width. CONSTITUTION:A reset signal generating device receives a synchronizing signal S1 from an input terminal 1 and a clock signal S2 from an input terminal 2 and supplies both of these signals to another device and inputs them to a pulse width monitor circuit 10 to monitor the pulse width of the signal S1. When detecting the pulse width wider than a preliminarily set certain time, the circuit 10 generates a specific pulse width excess detection signal S3 and sends it to a reset signal generating circuit 20. When receiving the signal S3, the circuit 20 generates a reset signal S4 and sends it to another device. Consequently, when the circuit 10 judges that the pulse width of the signal S1 is shorter than the preliminarily set certain time, another device is normally operated because the circuit 10 does not send the signal S4 to another device.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a reset signal generating device.

[Conventional technology]

Conventionally, a reset method for resetting a device configured with a logic circuit resets the device by using an independent signal line dedicated for reset, separate from other signals.

[Problem to be solved by the invention]

The conventional reset method described above uses an independent reset signal line, so in custom LSIs, etc., where the appropriate case is selected from among several types of cases with a predetermined number of terminals, a single reset signal line is used. In some cases, a larger case with many terminals must be used for the reset signal, and in logic devices connected by cables, connectors are subject to the same number of terminals as LSI cases. In both cases, the disadvantage is that the equipment becomes larger and the cost increases, such as requiring the use of cables with an unnecessary large number of cores.

[Means to solve the problem]

The reset signal generating device of the present invention monitors the time of the pulse width by inputting a clock signal of a predetermined specific period and a synchronization signal and counting the pulse width of the synchronization signal using the clock signal. It has a pulse width monitoring circuit that outputs a specific pulse width excess detection signal when a pulse width longer than a predetermined specific time is detected, and a reset signal generation circuit that generates a reset signal in response to the specific pulse width excess detection signal. are doing.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention;
The figure is a circuit diagram showing a second embodiment of the present invention, FIG. 3(a)
, (b) are waveform diagrams showing examples of waveforms of input and output signals in the second embodiment shown in FIG. 2, respectively.

First, a first example will be described.

In FIG. 1, the reset signal generating device of the embodiment of the wooden tablet 1 receives a synchronization signal Sl from an input terminal 1 and a clock signal S2 from an input terminal S2, and supplies these two signals to another device (not shown). The pulse width monitoring circuit 10 monitors the pulse width of the synchronizing signal S1, and when a pulse width longer than a preset certain time is detected, generates a specific pulse width excess detection signal S3 to reset the signal generation circuit 2.
The reset signal generation circuit 20 is configured to generate a reset signal S4 and send it to the other device upon receiving the specific pulse width excess detection signal S3.

b'C When the pulse width monitoring circuit 10 determines that the pulse width of the synchronization signal S1 is less than a predetermined period of time, the other device does not send out the reset signal S4, so the other device performs normal operation. perform an action.

Next, a second embodiment will be described.

In FIG. 2, the embodiment of the wooden tablet 2 has a counter 11 and a flip-flop 21. instead of the pulse width monitoring circuit 10 and reset signal generation circuit 20 in the first embodiment shown in FIG. This uses a NAND gate circuit 22.

Next, the operation of the embodiment of the wooden tablet 2 is shown in Figs. 2 and 3 (a>,
This will be explained using (b).

In FIG. 2 and FIG. 3(b), the counter 11 is in a reset state when the synchronization signal S1 is at a low level, and when the synchronization signal S1 is at a high level, the reset is released and the rising edge of the clock signal S2 is 4.
When the signal is input twice, the output level of the output Q2 of the counter 11 changes from a low level to a high level, and a specific pulse width excess detection signal S3a is output.

However, when the synchronization signal SL with a pulse width as shown in FIG. 3(,a) is input, the counter 11
1's output Q2 does not change.

As shown in FIG. 3(b), when the synchronization signal S1 reaches the counter 1 by 420 times or more of the clock signal S2, the counter 1
1, the synchronizing signal S1 becomes high level, during which time the counter 11 is released from reset 1, and the clock signal S2
At the fourth rising edge of , the output Q2 changes from a low level to a high level and sends out a specific pulse width excess detection signal S3m.

Next, the flip-flop 21 is set by the logical product of the specific pulse width excess detection signal S38 and the falling edge of the clock signal S2. Output for the input.

A specific pulse width excess detection signal 33a is input to the other input of the two-man powered NAND gate circuit 22, and as shown in FIG. The level is output and the reset signal S4a is output.

〔Effect of the invention〕

As explained above, the present invention uses two signal lines, a clock signal with a predetermined specific period and a periodic signal, and generates a reset signal when it detects that the pulse width of the synchronization signal is wider than the predetermined width. By doing so, it is possible to perform a reset without inputting an independent reset signal as in the past, so the terminal for a signal line dedicated to reset can be eliminated, and the LSI case can be made smaller, for example. The number of core wires of the cable used can also be reduced, which has the effect of making the entire device smaller and reducing costs.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
The figure is a circuit diagram showing a second embodiment of the present invention, FIG. 3(a)
, (b) are waveform diagrams showing examples of waveforms of input and output signals in the second embodiment shown in FIG. 2, respectively. 1.2...Input terminal, 10...Pulse width monitoring circuit,
20... Reset signal generation circuit, 11... Counter, 21... Flip-flop, 22... NAND game circuit, Sl... Synchronization signal, S2... Clock signal, S3. S, ... specific pulse width excess detection signal,
S4゜34a...Reset signal, SF...Output Q signal. Thatch

Claims (1)

[Claims] A clock signal with a predetermined specific period and a synchronization signal are input, and the pulse width of this synchronization signal is counted with the clock signal to monitor the time of the pulse width and determine a pulse width longer than the predetermined specific time. A reset signal generating device comprising: a pulse width monitoring circuit that outputs a specific pulse width excess detection signal when detecting the specific pulse width excess detection signal; and a reset signal generation circuit that generates a reset signal in response to the specific pulse width excess detection signal. .