JPH02109436A - Synchronizing pull-in circuit - Google Patents

Abstract

PURPOSE:To prevent the increase in the start time while being mis-convergence to remote end crosstalk noise by using a circuit applying synchronizing pull-in control with an equalizing converging signal and a synchronizing establishing signal so as to inhibit the equalization of a line equalizer circuit for a prescribed time at the start. CONSTITUTION:An input mask circuit 31 masking a reception signal from an input terminal 11 is provided before a line equalizer circuit 12. An output of the circuit 12 is inputted to an AND gate 15 and inputted to a frame synchronizing circuit 14 and a training signal detection circuit 32. A synchronizing establishing signal (c) of the circuit 14 and a detection signal (d) of the circuit 32 are inputted to a synchronizing pull-in control circuit 13. The circuit 13 outputs the reset signal (a) to the circuit 12 and inputs a line equalizing circuit converging signal (b) to the circuit 12. Moreover, a mask control signal (f) from the circuit 13 is inputted to the circuit 31. Furthermore, the synchronizing pull-in end signal (e) from the circuit 13 is outputted to a gate 15 and the output of the gate 15 is led to an output terminal 16.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is used in a time division transmission device that performs automatic line equalization using a training signal at the start of startup, and is used for synchronized pull-in to shorten the startup time for synchronized pull-in. Regarding circuits.

[Conventional technology]

FIG. 5 shows an example of the configuration of a time division transmission system.

That is, it is a transmission system in which digital line termination devices 21 and 22 and in-office line termination boards 23 and 24 are connected via a metallic cable 25.
Time-division transmission is performed between the digital line termination device 22 and the in-office line termination board 23, and between the digital line termination device 22 and the in-office line termination board 24, respectively.

FIG. 6 shows a block diagram of a conventional synchronization pull-in circuit provided in the digital line termination devices 21, 22 and the in-office line termination boards 23, 24, respectively.

In this FIG. 6, reference numeral 11 is an input terminal to which transmission signals and training signals are input manually, and input terminal 1
1 is connected to a line equalization circuit 12 that automatically equalizes the line. The output of the line equalization circuit 12 is inputted to a frame synchronization circuit 14 for performing frame synchronization, and also inputted to an AND gate 15. A frame synchronization establishment signal C is output from the frame synchronization circuit 14 to the synchronization pull-in control circuit 13. The line equalization circuit 12 includes a synchronous pull-in control circuit 1
3, a reset signal a is inputted manually, and a line equalization circuit convergence signal S is outputted to the synchronization pull-in control circuit 13. The synchronization control circuit 13 outputs a synchronization completion signal e to the AND gate 15 based on the line equalization circuit 120 line equalization circuit convergence signal and the synchronization establishment signal C of the frame synchronization circuit. The AND gate 15 outputs an automatically equalized output to the output terminal 16 in response to the output of the synchronization pull-in completion signal e from the synchronization pull-in control circuit 13.

Next, the operation of this circuit will be explained with reference to the flowchart of FIG.

First, upon start-up, the synchronous pull-in control circuit 13 outputs a reset signal a to reset the line equalization circuit 12 and starts the timer TO in the synchronous pull-in control circuit 13. The value of this timer TO is line equalization circuit 1.
2 and the synchronization establishment time of the frame synchronization circuit 14, and are set in advance.

Next, the convergence of the line equalization circuit 12 is determined based on the line equalization circuit convergence signal of the line equalization circuit 12, and if the line equalization circuit 12 has not converged, the line equalization circuit 12 continues to control the input terminal 11 until the timer TO expires. The line equalization operation and convergence determination of the line equalization circuit for the received signal from the line are repeated. Timer TO
If the line equalization circuit 12 does not converge even after expiration,
Clear timer TO and return to initial state. On the other hand, if the line equalization circuit] 2 has converged, the establishment of frame synchronization is determined based on the frame synchronization establishment signal C from the frame synchronization circuit 14. If frame synchronization has not been established, the frame synchronization circuit 14 repeats the frame synchronization operation and determination of frame synchronization establishment until timer TO expires. If frame synchronization is not established even after timer To expires, timer TO is cleared and the process returns to the initial state.

When frame synchronization is established, timer To is cleared, synchronization pull-in completion signal e is input to AND gate 15, and a reproduced signal is output from output terminal 16.

[Problem that the invention seeks to solve]

However, this conventional synchronous pull-in circuit configuration has a problem in that the startup time increases due to far-end crosstalk noise at startup.

In other words, in the time-division digital transmission system shown in Fig. 5, the influence of near-end crosstalk noise between time-division transmission lines during communication can be removed by establishing burst phase synchronization, but at startup, the influence of near-end crosstalk noise between adjacent time-division transmission lines Due to far-end crosstalk noise from the digital line termination devices 21, 22 of the time-division transmission line, the in-office line termination boards 23, 240 and the line equalization circuits 12 that are being started up erroneously converge, increasing the start-up time.

This is shown in Fig. 8 in the transmission system of Fig. 5, when the in-office line terminating board 24 and the data line terminating unit 22 start up while the digital line terminating unit 21 is communicating with the in-office line terminating board 23. This will be explained by showing a time chart of the burst waveform at startup.

ASB and CSD in FIG. 8 correspond to burst waveforms at each point in FIG. 5, where S is a transmission burst containing general data being communicated, R is a reception burst for S,
S, represents the transmit burst containing the training signal during activation, R1 represents the receive burst for the three guns, and R' represents the far-end crosstalk noise.

Here, the training signal is sent for the automatic equalization operation of the line equalization circuit 12, and usually an isolated pattern is used. When the line equalization circuit 12 converges and the line equalization operation is completed, the transmission burst S containing the training signal being activated is transmitted.

is switched to the transmission parse) S containing the general data being communicated. Further, in FIG. 8, T is a time period indicating the burst repetition frequency of time-division transmission.

In FIG. 5, when communication is started between the digital line termination device 22 and the in-office line termination board 24, first the in-office line termination unit 24 sends a transmission parse (SA) to the digital line termination device 22, and the digital line A line equalization operation and a frame synchronization operation are performed in the terminal device 22 (downlink training). When the line equalization operation converges in the digital line #-terminal device 22, frame synchronization is established, and synchronization pull-in is completed, the digital line #-terminal device 2
2 to the in-office 11" J board 24, and the in-office line termination board 24 performs a line equalization operation and a frame synchronization operation (upward training).

At this time, due to the far-end crosstalk characteristics of the metallic cable 25, as shown in FIG. Therefore, the synchronization pull-in circuit of the intra-office line termination board 24 performs a line equalization operation and a frame synchronization operation for the far-end crosstalk noise R'. As a result, the in-office line termination board 24 completes synchronization with respect to the far-end crosstalk noise R' before receiving the normal reception pulse (RT) from the digital line termination device 22. after that,
A regular reception burst R7 is received from the digital line termination device 22, but the gain of the line equalization circuit 12 of the synchronous pull-in circuit of the in-office line termination board 24 converges to the far-end crosstalk noise R' from the digital line termination device 21. Therefore, the normal reception burst R7 from the digital line # end device 22
Frame synchronization cannot be achieved. Therefore, it is necessary to reset the line equalization circuit 12 and perform the synchronization pull-in operation from the beginning again, resulting in a drawback that the start-up time increases.

The present invention solves the above-mentioned drawbacks, and provides a synchronization pull-in circuit that enables normal equalization convergence and synchronization pull-in even in the presence of far-end crosstalk noise, and can shorten the synchronization pull-in time at startup. The purpose is to

[Means for solving problems]

The present invention provides a line equalization circuit that automatically equalizes a line using a training signal at the start of startup, a frame synchronization circuit that performs frame synchronization using the training signal, an equalization convergence signal of the line equalization circuit, and the frame synchronization circuit. A synchronization pull-in circuit comprising a synchronization pull-in control circuit that performs synchronization pull-in control based on a synchronization establishment signal of the circuit, characterized in that the synchronization pull-in circuit includes means for inhibiting the equalization operation of the line equalization circuit for a certain period of time at startup.

[Effect]

In the present invention, the line equalization operation using the training signal is performed at startup by masking the received signal using an input mask circuit for a certain period of time,
Alternatively, by resetting the line equalization circuit, it is prohibited for a certain period of time, and then the line equalization operation and frame synchronization establishment using the training signal are performed.

Therefore, during the line equalization operation using the training signal at startup, the line equalization will not converge due to far-end crosstalk noise and frame synchronization will not be achieved due to the regular received signal, and the synchronization pull-in time at startup will be reduced. Can be shortened.

〔Example〕

The present invention will be described in detail below based on the drawings.

FIG. 1 is a block diagram showing the configuration of a synchronization pull-in circuit according to a first embodiment of the present invention.

This synchronous pull-in circuit is connected to the input terminal 1 where the received signal is manually input.
1, an input mask circuit 31 for masking the received signal is provided in front of the line equalization circuit 12, and the output of this line equalization circuit 12 is input to the AND gate 15, as well as to the frame synchronization circuit 14 and training signal detection. The circuit 32 is manually powered. The synchronization establishment signal C of the frame synchronization circuit 14 and the detection signal d of the training signal detection circuit are input to the synchronization pull-in control circuit 13. Synchronous pull-in control circuit 13
outputs a reset signal a to the line equalization circuit 12, and also inputs a line equalization circuit convergence signal of the line equalization circuit 12 manually.

In addition, the human mask circuit 31 includes a synchronous pull-in control circuit 1
The mask control signal f from 3 is input manually. Furthermore, the synchronization pull-in completion signal e from the synchronization pull-in control circuit 13 is output to an AND gate 15 , and the output of the AND gate 15 is led to an output terminal 16 .

The feature of this embodiment is that a manual mask circuit 31 is provided before the line equalization circuit 12, and a training signal detection circuit 32 is provided for the output of the line equalization circuit.

Next, FIG. 2 shows a flowchart showing the synchronization pull-in operation of this embodiment, and the operation will be explained.

First, at the start of startup, the timer T of the synchronous pull-in control circuit 13 is started, and the human power of the line equalization circuit 12 is applied to the line equalization circuit 12 until the timer TII expires, and the mask control signal f from the synchronous pull-in control circuit 13 is applied to the human power mask circuit. It is prohibited by outputting to 31. The value of this timer T defines the manual masking time of the line equalization circuit 12, and is the time until the synchronization pull-in is completed in the digital line termination device 22 in FIG. It is set in advance to the time until receiving the regular reception burst RT from No. 22. By masking the human power of the line equalization circuit 12 by the input mask circuit 31 in this way, the line equalization circuit 12 is prevented from converging on the far-end crosstalk noise R' from the digital line termination device 21 of the adjacent line. can.

When the timer T expires, the input mask of the line equalization circuit 12 is released and a synchronization pull-in operation is started. That is, the training signal detection signal Tp is set to "0", the line equalization circuit 12 shown in FIG. 1 is reset, and the timer TO of the synchronization pull-in control circuit 13 is started. Here, the training signal detection signal T.

indicates the detection state for the training signal, “
1” indicates that the training signal is being detected, and “
0'' indicates that no training signal is detected.

After the timer TO starts, it is determined whether the line equalization circuit 12 has converged, and if it has not converged, the equalization operation and the convergence determination of the line equalization circuit 12 are repeated until the timer TO expires. If the timer TO does not converge even after expiration, the timer TO is cleared and the line equalization circuit reset state is returned. At this time, at the same time as the line equalization operation, a training signal detection judgment is performed using the detection signal d from the training signal detection circuit 32. If detected, the training signal detection signal Tp is set to "1", and if not detected, the training signal detection operation is performed. I do.

On the other hand, if the line equalization circuit 12 has converged, the training signal detection signal Tp is determined. When the training signal detection signal T is "1", the received burst R containing the training signal from the digital line termination device 22
1 is received, the establishment of frame synchronization is determined based on the frame synchronization establishment signal C from the frame synchronization circuit 14.

If frame synchronization has been established, timer TO is cleared, the synchronization pull-in operation is completed, and a synchronization pull-in completion signal C is output.

If frame synchronization has not been established, the frame synchronization circuit 14 repeats the frame synchronization operation and determination of frame synchronization establishment until timer TO expires. If frame synchronization is not established even after timer To expires, timer TO is cleared and the line equalization circuit reset state is returned.

If the determination result of the training signal detection signal T is "θ", since a regular reception burst has not been received, the timer TO is cleared and the line equalization circuit reset state is returned.

As shown in FIG. 8C, during upstream training, the receiving end of the in-office line termination board 24 contains the far-end crosstalk noise R' from the digital line termination device 21 and the training signal from the digital line termination device 22. Both reception bursts are received, but since the reception burst (normal reception burst) RT is sufficiently large compared to the far-end crosstalk noise R', the synchronization pull-in circuit of the in-office line termination board 24 is connected to the reception burst l'Rr. It is possible to converge line equalization and establish frame synchronization.

FIGS. 3 and 4 show the configuration and operation flowchart of a second embodiment of the present invention.

In this second embodiment, instead of using the input mask circuit 31 of the first embodiment to mask the human power of the line equalization circuit 12,
The line equalization circuit 12 is reset by the mask control signal f during the time of the timer T1 of the synchronous pull-in control circuit 13, thereby prohibiting the line equalization operation for a certain period of time. That is, an OR gate 41 is provided between the synchronous pull-in control circuit 13 and the line equalization circuit 12, and the reset signal a and mask control signal f from the synchronous pull-in control circuit 13 are passed through the OR gate 41 to the line equalization circuit 12. The configuration is such that it leads to the reset input terminal of.

Its operation differs from that of the first embodiment only in that when the timer T starts, the line equalization circuit 12 is reset by the mask control signal f during that time, and the other operations are the same as those of the first embodiment. This is the same as in one embodiment.

〔Effect of the invention〕

As described above, the present invention has the effect of preventing the line equalization circuit in a time-division transmission system from erroneously converging on far-end crosstalk noise from an adjacent line at startup, thereby preventing an increase in startup time. .

Therefore, even when far-end crosstalk noise is present, it is possible to perform synchronization normally, and the range of application of the time division transmission apparatus can be expanded.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a synchronization pull-in circuit according to a first embodiment of the present invention. FIG. 2 is a flowchart showing the operation of the first embodiment. FIG. 3 is a block diagram showing the configuration of a synchronization pull-in circuit according to a second embodiment of the present invention. FIG. 4 is a flowchart showing the operation of the second embodiment. FIG. 5 is a diagram showing the configuration of a time division transmission system. FIG. 6 is a block diagram showing the configuration of a conventional synchronous pull-in circuit. FIG. 7 is a flowchart showing the operation of the conventional example. FIG. 8 is a time chart explaining the synchronization pull-in operation shown in FIG. 5. 11... Input terminal, 12... Line equalization circuit, 13.
... Synchronization pull-in control circuit, 14 ... Frame synchronization circuit, 15 ... AND gate, 16 ... Output terminal, 21
．． 22...Digital line termination device, 23.24...
・Internal line line board, 25...Metallic cable, 3
1... Human mask circuit, 32... Training signal detection circuit, 41... OR gate. Patent applicant: Nippon Telegraph and Telephone Corporation Representative: Patent attorney Naotaka Ide? ! '--1 Plan - Sea 325 + Siri 1 Whistle = Soukoma Reiichi 3 Roya, sending power Tekuta (17 Teshi diagram conventional example fan 6 times shoulder rotation

Claims (1)

[Claims] 1. A line equalization circuit that automatically equalizes a line using a training signal at the start of startup, a frame synchronization circuit that synchronizes frames using the training signal, and an equalization convergence signal of the line equalization circuit. and a synchronization pull-in control circuit that performs synchronization pull-in control based on the synchronization establishment signal of the frame synchronization circuit, further comprising means for inhibiting the equalization operation of the line equalization circuit for a certain period of time at startup. Features a synchronous pull-in circuit.