JPH02105569A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To make a wiring lifetime long and expand the degree of freedom of a circuit design after relieving the limitation on fan-out by providing a plurality of pieces of output points of a unit circuit according to the load of the unit and distributing circuit load uniformly to a plurality of the output points. CONSTITUTION:The first wiring layer 2 is installed in a basic gate 1 which is disposed in a matrix form and the second wiring layer 3 is installed at the lower layer of the first wiring 2 after intersecting at right angles to the first wiring 2 and then, it is constructed that an interval between the first and second wiring layers 2 and 3 are connected with a through hole 4. In this way, a plurality of pieces of output points are provided according to load applied to circuit output. This approach effectively brings about the extension of a wiring lifetime or relieves the lifetime of operating frequency of a circuit and then, the degree of freedom of a circuit design is improved by relieving the limitation on fan-out.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and more particularly to an integrated circuit device with improved wiring life, that is, with increased reliability.

[Conventional technology]

In general, a gate array type integrated circuit device (hereinafter simply referred to as a gate array) realizes its circuit function by connecting various circuit units such as NAND and flip-flops by automatic wiring using a computer. For each of these circuit units, a wiring pattern is prepared in advance as a functional block, and its input and output points are defined and designed to be compatible with automatic wiring processing by a computer.

On the other hand, the wiring life, which is one of the reliability standards for integrated circuit devices (hereinafter referred to as IC), is generally measured by the average time t50 until the failure rate reaches 50% given by the following equation.

j50=AJ−”eXp (φ/kT)・(1)(
In equation 1), k is Boltzmann constant, T is junction temperature,
J is the current density, A and φ are constants determined by the material and structure of the wiring, and the constant n is mainly determined by the type of circuit current, that is, steady current, pulsed current, DC or AC, and is determined by experiment. . In addition, the current density J is
Circuit electrician.

It is expressed by the following equation using the wiring width W and the wiring film thickness t.

J = I / w -t ... (2) As mentioned above, it is necessary to ensure a wiring life corresponding to the required reliability in gate arrays as well, but as explained next, this is currently quite difficult. It has become.

(2) As devices become larger, the wiring pitch tends to be reduced, and the wiring width W tends to become smaller.

■Similarly, multilayer wiring technology has become necessary as the scale increases, but increasing the wiring film thickness t is a negative factor in ensuring coverage.

(2) The circuit current I tends to increase as the speed of circuit operation increases. For example, the increase in speed in a CMO3 circuit is due to the improvement in mutual inductance gm by shortening the gate length, and as is clear from gm = dI/dV, the speed can be increased while maintaining a constant voltage (constant power supply voltage). This means that the circuit current 1 increases.

(2) A CMO3 circuit is required to have a high circuit operating frequency f, and the power consumption P in the operating state increases in proportion to this, and the junction temperature T approximated by the following equation increases during use.

T=T,-)-θj,P (3) In this equation, T is the ambient temperature and θc is the thermal resistance of the IC package.

In actual gate arrays, wiring life conditions are particularly severe for outputs of functional blocks. In this case, the output current I of the CMO3 circuit is a function of the output load CL, and as a −th order approximation, it is expressed as a function of the load CL and the operating frequency f as a square CLf.

Furthermore, the output load CL is the fanout F connected to the output, where α and β are constants. and the wiring length l, it can be approximated as shown in the following equation.

It is approximated by CL−αFo+βff−(4) (
α and β are constants). From the above, it is necessary to ensure the wiring life of an IC configured with a CMO8 circuit, so even if the circuit operates satisfactorily, the operating frequency f and fanout F O + wiring length l must be limited. Sometimes.

Now, the basics of the conventional gate array wiring method is to use the total wiring length (in this case, the wiring length is not limited to the actual wiring length, but may be the wiring length in units of one gate) as an index. After several layout trials, I selected the one that would make this the shortest possible layout, and then connected the outputs of each gate to the shortest possible wiring.

For example, FIG. 4 is a plan view showing an example of a wiring pattern.
This shows the case where the shortest wiring is made from output point A to the other four input points B to E. In the figure, block 1 is the basic gate arranged in a matrix, solid line 2 is the first layer wiring, and dotted line 3
The symbol 4 represents the second layer wiring, and the triangle mark 4 represents the first layer wiring 1. A through hole between the second layer wirings 2 is shown.

The problem here is that the circuit current I is
~ G is the maximum, and the wiring life in this section is the input/output point A.
It is the smallest among the nets that reach ~E. In particular, the area between points FG and FG of the first layer wiring 1, which is thin and narrow, becomes a bottleneck in the life of the wiring.

Therefore, in actual design, a statistical value is assumed for the wiring length l, and fan-out restrictions are imposed on the product design according to the operating frequency.

[Problem to be solved by the invention]

In the above-mentioned conventional semiconductor integrated circuit devices, the operating frequency has increasingly moved into the high frequency range in recent years, and the wiring length has become longer due to the expansion of the internal wiring area as chips become larger as part of higher integration. ing. On the other hand, the required value for fan-out is expected to increase as systems become more chip-based and parallel processing expands from 8 bits to 16 bits to 32 bits. It is an object of the present invention to solve such problems and provide a semiconductor integrated circuit device that extends the life of wiring, alleviates restrictions on the number of fan-outs, and expands the degree of freedom in circuit design. It's about doing.

[Means for Solving the Problems] The configuration of the present invention provides a semiconductor integrated circuit device that realizes various functions by combining unit circuits constituting various circuit units. The present invention is characterized in that a plurality of output points of a unit circuit are provided, and the circuit load is equally distributed among the plurality of output points.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a schematic plan view of an embodiment of the present invention. In this embodiment, a first
A layer wiring 2 is provided, a second layer wiring 3 is provided below the first wiring 1 and perpendicular to the first wiring 2, and a second layer wiring 3 is provided below the first wiring 1. The second layer wiring 2 and 3 are connected by a through hole 4. In the figure, the input and output points of basic gate 1 are circled point A,
A'.

They are indicated by B to E, and J to O are indicated by triangular marks in the through hole 4. In this example, the bottleneck in the wiring life is the section J to K or the section N to O, but if the operating frequency is the same, the current flowing there will be a fan-out component compared to the case of Fig. 3. It can be seen that the fanout is reduced by two fanouts.

This fan-out reduction has a great effect in alleviating the situation in which the operating frequency f has to be limited in terms of wiring life, for example in the wiring method shown in FIG. 4. On the other hand, in the wiring method of FIG. 4, if there is a situation where the number of fan-outs must be limited from the viewpoint of wiring life, this also has the effect of alleviating this.

FIGS. 2(a) and 2(b) are two example circuit diagrams illustrating the effect of relaxing the restriction on the number of fan-outs. show.

Figure 2 (a) shows the case where the fan-out number limit is 4,
FIG. 2(b) shows the case of 6 or more.

FIG. 2(a) requires one more stage of buffer gates 3 than FIG. 2(b).

In FIG. 1, the wiring length is somewhat longer, but by assuming the wiring connection method of the present invention from the placement stage, the increase in wiring length can be kept to the necessary minimum. can.

FIG. 3 is a schematic plan view of a second embodiment of the present invention,
The difference from FIG. 1 is that wiring for input/output points A' to P to Q to ■ is added.

The feature of this embodiment is that after connecting from the output point A in exactly the same way as the conventional wiring method, the second output point A' is connected in parallel to the connection point H or ■ for 1/2 of the total load. It has the advantage that existing placement and routing programs can be used as is. Further, this additional wiring can be freely selected to be attached or not depending on the number of fan-outs, operating frequency, or wiring length.

Although a CMOS gate array has been described here as an example, the present invention also applies to a bipolar CMO9 circuit,
It can be applied to circuits such as ECL circuits, and can be applied not only to gate array systems but also to standard cell systems, ROM,
It can also be applied to semiconductor integrated circuits having memory circuits such as RAM and analog circuits such as operational amplifiers as functional blocks.

〔Effect of the invention〕

As explained above, the present invention effectively extends the life of the wiring by providing a plurality of output points of the circuit according to the load applied to the output of the circuit, or relaxes the operating frequency limit of the circuit. Alternatively, relaxing this fan-out number restriction has the effect of improving the degree of freedom in circuit design.

[Brief explanation of the drawing]

FIG. 1 is a schematic plan view of a wiring button part according to an embodiment of the present invention, FIGS. 2(a) and (b) are circuit diagrams of a shift register illustrating the fan-out of FIG. 1, and FIG. Second aspect of the present invention
FIG. 4 is a schematic plan view of an example of a conventional wiring button part. DESCRIPTION OF SYMBOLS 1... Basic gate, 2... 1st layer wiring, 3... 2nd layer wiring, 4... Through hole, 5... Buffer gate, 6... D-FF.

Claims (1)

[Claims] In a semiconductor integrated circuit device that realizes various functions by combining unit circuits constituting various circuit units, a plurality of output points of the unit circuit are provided according to the load of the unit circuit, and these multiple output points A semiconductor integrated circuit device characterized in that the circuit load is evenly distributed between the circuit loads.