JPH0156418B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] A main processor (MPU) and a main memory (MS) are connected to a main bus, and a plurality of sub-processors are connected to an expansion bus that is provided independently of the main bus. By connecting (SPU),
In a computer system that performs multitasking by expanding the system, a communication register (CR) and an address translation register (ACR) are provided between the main bus and the expansion bus, and the main processor (MPU) ) requests a task by interrupting the subprocessor (SPU), it transfers the task bit that identifies the request destination and the control block (CB) information selected on the main memory (MS) to the address translation register ( By providing a means for storing information in the ACR), when the sub-processor (SPU) executes the task, it simply accesses the control block (CB) recognized by the sub-processor (SPU), and the above address is stored. The control block (CB) selected by the main processor (MPU) can be accessed by the task bit and control block (CB) information stored in the conversion register.

[Industrial application field]

The present invention uses one main processor (MPU)
A computer system in which the system can be expanded by connecting a main memory (MS) to a main bus and multiple subprocessors (SPU) to an expansion bus that is provided independently of the main bus. This paper relates to a multi-task processing method.

With recent advances in computer technology, the amount of data processed by computer systems has increased and become more diverse, and it has become necessary to add corresponding functions. With advancement, large functional blocks (e.g. processors)
It is becoming more common for computer system functions to be added on a per-unit basis, and with conventional methods, each addition of a function has an impact on the existing operating system (OS), making it difficult to handle. It's here.

Under these circumstances, there has been a demand for a method that allows the addition of processor-based options and easily enables multitasking without making any changes to the existing system.

[Problems to be solved by conventional technology and invention]

FIG. 4 is a diagram illustrating a conventional task execution method.

That is, in the conventional system, the host processor {main processor (MPU)}1 on the main bus
When a processor instructs a task to a subprocessor (SPU) 2 on an expansion bus via a communication register (CR), for example, a main memory (MS) 3 on the main bus that can be accessed by both processors is control block (CB) 3
1 was established to issue commands and receive processing results of the task.

Furthermore, to be more specific, while both processors are using the control block (CB) 31 on the main memory (MS) 3, the control block (CB) 31 on the main memory (MS) 3 is being However, there was a problem where it was not possible to request multiple tasks.

Therefore, when multiplexing tasks, host side 1
The problem was that not only the operating system (OS) on the subprocessor (SPU) 2 side had to be changed significantly, but also the operating system (OS) on the subprocessor (SPU) 2 side.

Further, control was required to prevent collision between the timing at which the main processor (MPU) 1 outputs separate tasks and the timing at which the sub-processor (SPU) 2 returns the status.

In view of the above-mentioned conventional drawbacks, the present invention provides that when a sub-processor (SPU) accesses a main memory (MS) on a main bus to which a main processor (MPU) is connected, the main processor (MPU) The purpose of this invention is to provide a method that facilitates multiplexing of tasks from both the main and sub processors by converting addresses from the sub processor (SPU) based on the information of the sub processor (SPU). .

[Means for solving problems]

FIG. 1 is a diagram for explaining the concept of the present invention, and FIG. 2 is a block diagram showing an embodiment of the present invention.

In the present invention, as shown in Figure 1, the main processor (MPU) is connected to the main memory (MS).
When the empty blocks of multiple control blocks (CB0 to CBn) provided on 3 are captured and a task is requested to the subprocessor (SPU),
Subprocessor (SPU) that received the task request
Apparently, the main processor (MPU) is accessed by accessing the control block (CB) 31' at a specific fixed address as shown in the figure.
Control block (CB0~n) 3 selected by
The configuration is such that an address translation register 4 is provided so that 1 can be accessed.

Specifically, as shown in the example of FIG.
A main processor (MPU) 1 and a main memory device (MS) 3 are connected to a main bus, and a plurality of subprocessors (SPU1 to SPU n) 2 are connected to an expansion bus that is provided independently of the main bus. In particular, in a computer system where the system is expanded, a communication register (CR) 5 and an address translation register (ACR) 4 are provided between the main bus and the expansion bus, and the main processor When the (MPU) 1 instructs a task to the sub-processors (SPU1 to n) 2, the main processor (MPU) 1 executes a control block (CB) on the main memory (MS) 3.
In addition to setting the control information in the free area of 31,
After setting the interrupt request bit and task bit for the sub-processors (SPU1 to SPU n) 2 in the communication register (CR) 5, the control block (CB) 31 information and the task bit are set in the address translation register (ACR) 4. The information is stored, and the sub-processors (SPU1 to SPU n) 2 recognize that the interrupt request is for itself by taking in the task bit, echo-reset the interrupt bit, and send the request to the main processor. When accessing the control block (CB) 31 to execute a task instructed by the (MPU) 1,
By simply accessing the address of the control block (CB) 31' recognized by the sub-processor (SPU1-n) 2, the address can be converted to the task bit information stored in the address conversion register (ACR) 4 and the control block. (CB) 31 information, so that the control block (CB) 31 on the main memory (MS) 3 of the main bus can be accessed.

[Effect]

That is, according to the present invention, one main processor (MPU) and main memory (MS) are connected to a main bus, and a plurality of sub-processors (SPUs) are connected to an expansion bus that is provided independently of the main bus. )
In a computer system that expands the system and executes multitasking by connecting a communication register (CR) and an address translation register (ACR) between the main bus and the expansion bus. When the main processor (MPU) requests a task by interrupting the sub-processor (SPU), the task bit that identifies the request destination and the control block (CB) information selected on the main memory (MS) are and,
By providing a means for storing information in the address translation register (ACR), the sub-processor (SPU) accesses the control block (CB) recognized by the sub-processor (SPU) when executing the task. The control block (CB) selected by the main processor (MPU) is determined based on the task bit information and control block (CB) information stored in the address translation register (ACR).
The system can be accessed without changing the software on the main processor (MPU) and sub-processor (SPU) sides, making it possible to easily perform multitasking.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.
The above-mentioned FIG. 2 is a block diagram showing one embodiment of the present invention, and FIG. 3 is a diagram showing details of the communication register (CR), and the address translation register (CR) in FIG. ACR) 4 and communication register (CR) 5 are the functional blocks necessary to implement the present invention.
Note that the same reference numerals indicate the same objects throughout the figures.

First, the main processor (hereinafter referred to as MPU) 1 is the sub-processor (hereinafter referred to as SPU).
When requesting a task to a subprocessor (SPU1 to SPUn) 2, a task bit 51 corresponding to the subprocessor (SPU1 to SPUn) 2 to which the task is requested is set in the communication register (CR) 5. {Indicated by diagonal lines in FIG. 3a} The MPU 1 continues to use the main memory (MS) 3
Select the available blocks (1 to n) of the upper control block (CB) 31 (see FIG. 1) and set the control information.

At this time, the address translation register (ACR)
4.Which control block (CB0~n)
and remember which task bit it corresponds to.

Next, MPU 1 sets the interrupt request bit to communication register (CR) 5 {Figure 3a
}, indicated by the MSB bit,
Interrupt any one of SPU(1 to n)2. (See Figure 3.) SPU(k)2, which received the interrupt, checks whether the task request is for itself by checking the task bit position 51, and if it is different, sends the interrupt request to SPU(k)2. k+1)2
be notified via Daisy Chain.

When the corresponding SPU(j) 2 recognizes from the task bit position 51 that the interrupt is for itself, it echo-resets the interrupt bit on the communication register (CR) 5 (see FIG. 3).

The SPU(j)2 sets its own task bit in the corresponding position of the communication register (CR)5 (indicated by diagonal lines in FIG. 3b), interrupts the MPU1, and responds to the task. Control block (CB) 31
access. (See Figure 1) When the SPU(j) 2 accesses the control block (CB), the bus arbitration controller 6 generates a main bus usage permission signal and accesses the control block (CB) 31. For example, specific 4 bits of address information are address translated in the address translation register (ACR) 4,
By being sent to the main bus through the multiplexer 7, access to the corresponding area of the control block (CB) 31 is performed in cooperation with other address information that is not subjected to the address conversion.

The SPU(j) 2 executes a task based on the control information read from the control block (CB) 31, and when the task is finished, the end information is sent to the control block (CB) in the same way as above. )31 area.

The SPU(j)2 finally has a task bit 52,
Interrupt request to MPU1 {Figure 3b
MSB bit reference} is set in communication register (CR) 5.

An interrupt request was received from the SPU(j)2.
The MPU 1 looks at the task bit 52 of the communication register (CR) 2, echo-resets the bit, and receives the completion information from the control block (CB).
Finish executing a series of tasks.

Note that normal access to the main memory (MS) 3 operates without undergoing the above address conversion.

In this way, the present invention selects an empty block of the control block (CB) on the main memory (MS) when the main processor (MPU) requests a task to the sub-processor (SPU) using an interrupt. The selected information and the task bit information that identifies the subprocessor (SPU) are
Store it in the address translation register (ACR),
When the subprocessor (SPU) accesses the control block (CB) necessary to execute the task, the address is transferred to the main processor based on the control block (CB) selection information and the task bit information. Control block (CB) selected by (MPU)
The feature is that it enables multiplexing of tasks corresponding to multiple subprocessors (SPUs) by converting the addresses into addresses of .

〔Effect of the invention〕

As explained above in detail, the multitask processing method of the present invention connects one main processor (MPU) and main memory (MS) to a main bus, and is provided independently from the main bus. In a computer system that expands the system and executes multitasking by connecting multiple subprocessors (SPUs) to an expansion bus, a communication register (CR) is installed between the main bus and the expansion bus. ) and an address translation register (ACR), and when the main processor (MPU) requests a task by interrupting the sub-processor (SPU), it uses a task bit that identifies the request destination and a main memory (MS ) and the control block (CB) information selected above.
By providing a means for storing information in the address translation register (ACR), the sub-processor (SPU) accesses the control block (CB) recognized by the sub-processor (SPU) when executing the task. The control block (CB) selected by the main processor (MPU) is determined based on the task bit information and control block (CB) information stored in the address translation register (ACR).
The system can be accessed without changing the software on the main processor (MPU) and sub-processor (SPU) sides, making it possible to easily perform multitasking.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the concept of the present invention, Fig. 2 is a block diagram showing an embodiment of the invention, and Fig. 3 is a diagram illustrating the concept of the present invention.
The figure shows details of a communication register (CR), and FIG. 4 is a diagram explaining a conventional task execution method. In the drawing, 1 is the main processor (MPU), 2 is the sub-processor (SPU0~n), and 3 is the main processor (MPU).
31 is the main memory (MS), 31 is the control block (CB, CB0 to n), 4 is the address translation register (ACR), 5 is the communication register (CR), and 6 is the bus arbitration controller. .

Claims (1)

[Claims] 1. One main processor (MPU) 1 and main memory (MS) 3 are connected to a main bus, and a plurality of sub-processors ( In a computer system that expands the system and executes multitasking by connecting SPU1 to n)2, a communication register (CR) 5 and address A conversion register (ACR) 4 is provided, and when commanding a task from the main processor (MPU) 1 to the sub-processors (SPU1 to SPU n) 2, the main processor (MPU) 1
sets control information in the free area of the control block (CB) 31 on the main storage device (MS) 3, and also sets interrupt request bits for the subprocessors (SPU1 to n) 2 in the communication register (CR) 5. After setting the task bit corresponding to the subprocessor (SPU1 to SPU n) 2 that requests the task, the control block (CB) 31 information and task bit information are stored in the address translation register (ACR) 4, and the above The sub processors (SPU1 to SPU n) 2 recognize that the interrupt request is for themselves by taking in the task bit, echo-reset the interrupt bit, and respond to the instruction from the main processor (MPU) 1. In order to execute the task, the above control block (CB) 3
1, by simply accessing the control block (CB) 31' recognized by the subprocessor (SPU1 to SPU n) 2, the task bit and control block stored in the address translation register (ACR) 4 can be accessed. (CB) 31 information, the access address is converted and the main processor (MPU) on the main memory (MS) 3 of the main bus
Control block (CB) 31 captured by 1
A multitasking processing method characterized by controlling access to.