JPH01300338A - Floating point multiplier - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary of the Invention] Regarding a high-speed floating point multiplier that uses non-normalized numbers as input operands in addition to normalized numbers, the delay time of the multiplier when using a multi-order Booth algorithm A circuit for converting a denormalized number into a normalized number in a floating point multiplier that takes normalized numbers and denormalized numbers as input operands and uses Booth's algorithm of degree 3 or higher, with the aim of shortening the number. Multiple generators including multiples are arranged in parallel, and if the input operand is a normalized number, a selector is provided for inputting it to the multiple generator side, and if it is a non-normalized number, inputting it to the conversion circuit.

[Industrial application field]

The present invention relates to a high-speed floating point multiplier that uses non-normalized numbers as input operands in addition to normalized numbers.

Recently, the bit length of numbers used in floating point operations has tended to increase, and double-precision 64-bit lengths are often used. Also, the format of the operand (input operand) is:
IEEE standard formats are often used.

In the IEEE standard format, the number is 0.00110, for example.
....l is normalized and the mantissa part is 1. lO...
・Represented by l and an exponent part indicating the shift amount of the decimal point, and a mantissa part 1. lO...The first value of l is 1. But 0
．． If there are many O's like 00... and 1 still does not appear even after using the entire exponent part (shifting the decimal point by that much), consider it as a denormalized number and set the mantissa part to 0.0010.
・・・・・・1 etc.

Let the biased exponent part be 000...0.

For even smaller numbers, the entire mantissa part becomes 0, but such numbers are treated as underflows and are excluded from calculations.

After all, denormalized numbers exceptionally appear as numbers that are smaller than normalized numbers and larger than underflow. Some arithmetic units handle only normalized numbers, while others handle both normalized numbers and non-normalized numbers, and the present invention relates to the latter arithmetic unit.

In arithmetic units that also handle denormalized numbers, the operation target (
It is necessary to know whether the input operand) is a normalized number or a denormalized number, and process it accordingly. By the way, IEE
It is not possible to tell whether the input operand of the E standard formant is a normalized number or a non-normalized number just by looking at the mantissa part. This is because the beginning of the mantissa (1. or O, above) is removed from the mantissa as a hidden bit. However, you can tell whether it is a normalized number or a non-normalized number by looking at the exponent part; if the exponent part is 1 or more, it is a normalized number, and if it is all 0, it is a non-normalized number.

As the bit length of the input operand increases, the multiplier array (or tree) of multipliers can be made faster by using a multi-order Booth algorithm.

Furthermore, when the input operand includes a denormalized number, the conventional method inputs the input operand to a ramp number conversion circuit and multiplies its output, but this results in a large delay.The present invention solves this problem. The aim is to improve and speed up the process.

[Conventional technology]

When performing floating point multiplication, Booth's algorithm is generally used when the bit width of the mantissa becomes large. This means that, for example, when using the second-order Booth algorithm, the hard amount of the multiplying array or tree is approximately 1
/2, and the propagation delay time is also approximately 1/2.

Furthermore, when the number of bits in the mantissa increases, it is better to use a cubic Booth algorithm, which reduces the hard amount of the multiplication array or tree to about 2/3 of that when using a quadratic Booth. be able to. However, in reality, in calculations of about 64 bits, the cubic Booth algorithm is often not used, but the quadratic Booth algorithm is used. In the quadratic Booth algorithm, this is the multiplicand and the 2 of the multiplicand.
Whereas the cubic Booth algorithm requires a multiplicand of 2.3, 4. This is because twice the number is required. In the case of binary numbers, the number twice as large as a certain number can be obtained by shifting 1 bit to the left, and the number four times the number can be obtained by shifting 2 bits to the left, so the increase in hardware and delay is not a problem. To obtain this, it is necessary to add the multiplicand and a number obtained by shifting the multiplicand one bit to the left, which causes a delay. Therefore, even though the delay of the multiplier array or tree is reduced, the overall delay tends to be larger than using the second-order Booth algorithm when adding the generation time of three times the multiplicand operand.

Also, as mentioned above, the rEEE format is often used as a floating point format these days.
In the IEEE format, for example, the double-precision format for 32 bits is expressed with 1 bit for the sign, 11 bits for the exponent, and 52 bits for the mantissa, for a total of 64 bits. In the case of normalized numbers, the mantissa has a hidden bit of 1
There is always l.

It is expressed as exists, and a denormalized number has a biased exponent part of 0, a mantissa part with a loose bit of 0, and 0. ×××
It is expressed as XX.

Further, as described above, when performing multiplication in IEEE format, this denormalized number poses a problem. In terms of normalization/denormalization, the types of input operands are: when two operands (X, Y) are both normalized numbers, when one is a normalized number and the other is a denormalized number, The case of non-normalized numbers can also be considered.

When performing multiplication that includes operands that are denormalized numbers, the mantissa will lose digits if the multiplication is performed as is, so the denormalized number is usually converted to a wrap number before multiplication is performed.A ramp number is a denormalized number. The mantissa part is normalized and the hidden bit is set to 1), and the exponent part is expressed as a two's complement number to represent a negative number. Therefore, a wrap number conversion circuit is required as preprocessing for multiplication. FIG. 3 shows a general block diagram of a floating point multiplier that uses the cubic Booth algorithm and can handle denormalized numbers in IEEE format.

As shown in the figure, in this method, the X and Y operands are added to the lamp number conversion circuit 11, and the non-normalized number conversion/knob number conversion is performed. Since the operand check flag FLG indicates whether the operand is a normalized number or a non-normalized number, the above processing is possible. When converting a denormalized number to a wrapped number, the exponent part becomes negative (normalized numbers are biased so that the exponent part does not become negative, but this bias is not enough for denormalized numbers and it becomes negative), but this , it is sufficient to simply change the addition of the exponent part to subtraction (negative addition). Note that a normalized number with a negative exponent part is called a wrap number.

The exponent parts ez and ey of the X and Y operands that have passed through the wrap number conversion circuit 11 are added to the exponent part adder 12, and the mantissa parts Mx and My are added to the triple generator 14.3rd order Booth decoder 13.3rd order Booth The mantissa part and the exponent part M o of the product 2-X-Y are added to the multiplier section composed of the selector 15, the multiplication tree 16, and the partial product adder 17, and are multiplied.
* eo is required.

The selector 15 of the tertiary booth receives the mantissa part Mx, the triple of Mx from the triple generator 14, and the double and quadruple numbers (these are generated by shifting by 15 and inputting them). These are selected by the output of the tertiary Booth decoder 13 and input to the multiplication tree 16, and the final partial products are determined and added by the adder 17 to form the mantissa part Mo. The exponent part adder 12 adds or subtracts the exponent parts ez and ey of the operands X and Y, and the result becomes the exponent part eo.

The second-order Booth algorithm is shown in Table 1, and the third-order Booth algorithm is shown in Table 2. Here, X is the multiplicand,
Let Y be a multiplier. Also, func indicates the number to be selected with the booth selector, that is, X is the multiplicand itself,
2X is twice the multiplicand (number shifted 1 bit to the left),
3X is three times the multiplicand.

Table 1 Y−Σ(y2i ” )'21+1−y2i+2 )・
2Table 2 Y=Σ(yji +ys++t +23'si+2"
3i+2).2 The delay time of the multiplication circuit shown in FIG. 3 is the delay time of the multiplier itself plus the delay of the triple generator and the wrap number conversion circuit. As mentioned above, the hardware amount of this circuit block is smaller than that of a second-order Booth multiplier when the input operand is approximately 64 bits long, but the overall delay time tends to be large.

[Problem to be solved by the invention]

The present invention aims to improve this point and shorten the delay time of the multiplier when using a multi-order Booth algorithm.

[Means to solve the problem]

As shown in FIG. 1, in the present invention, the wrap number conversion circuit 11
and a triple generator 14 are placed in parallel, and a selector 18 is provided, to which an operand check flag FLG is input. The rest is the same as in Figure 3, 12 is an exponent adder, 13 is a cubic Booth decoder, 15 is a cubic Booth selector,
16 is a multiplication tree, and 17 is a partial product adder.

For input operands X and Y, not only normalized numbers but also non-normalized numbers are allowed. The floating point format is expected to be an IEEE standard format, but other formats may be used. In the case of a formant other than the IEEE standard formant, a circuit for converting the non-normalized number into a normalized number is used instead of the wrap number conversion circuit 11.

[Effect]

When operands X and Y are both IEEE denormalized numbers, the product z=x−y underflows and is not subject to calculation. Further, if both operands X and Y are normalized numbers, wrap number conversion is not necessary. Therefore, a wrap number conversion circuit is required if one of the operands X and Y is an IEEE denormalized number.
The present invention applies only when the other is an IEEE normalized number.The present invention adds one of the denormalized numbers (DNN) to the wrap number conversion circuit 11, and adds the other normalized number (NN) to the triple generators 14 and 3.
Add it to selector 15 in the next booth. The selector 18 performs this distribution. The rest is the same as in FIG. 3, and the mantissa part Mo and exponent part eo of product 2 are obtained from the partial product adder 17 and the exponent part adder 12.

In this circuit, operand X is a normalized number and operand Y
If is a non-normalized number, use X as shown in the figure.

However, if operand X is a non-normalized number and operand Y is a normalized number, then X and Y are assigned, contrary to what is shown in the figure. This means that in the former case, multiplication by X and Y is performed, and in the latter case, multiplication by Y-X is performed, but
-Y=Y-X, so there is no problem.

Also, since it is necessary to check whether the input operand is a normalized number or a non-normalized number at the time of input, a flag indicating which operand is a non-normalized number can be obtained, and this flag is set as the flag FLG. be able to.

In this circuit, triple generation and wrap number conversion are performed at the same time, so in Fig. 3, the sum of these processing times is the required delay time, but in the present invention, the required delay time is The larger of each delay time will be used.

In the case of multiplication between normalized numbers, wrap number conversion is not necessary and the conversion circuit 11 is in a through state.

However, since the cycle time of the multiplier is determined by the maximum delay time, it is the same as that in the case of normalized number x non-normalized number.

〔Example〕

FIG. 2 shows an embodiment of the present invention.As a recent trend, floating-point multipliers are often configured in a pipeline configuration in order to improve the throughput of operations (and the present invention also has a Benefits can be obtained.

In this embodiment, the first pipeline stage includes a wrap number conversion circuit 11 and a triple generator 14, and the second pipeline stage includes a multiplication tree 16 and a Booth decoder 1.
3. This is a case where the pipeline is cut off using the selector 15 or the like. Conventionally, a second-order Booth algorithm was used or pipelined using a third-order Booth configuration as shown in Figure 3, but compared to this embodiment, the second-order Booth multiplier is Second stage delay is small (conventional 3
The first stage delay is reduced for the next Booth multiplier. Pipeline processing is performed by transferring data between registers using a clock, and the slowest processing stage determines the speed. In FIG. 2, stage 2 of the arithmetic unit is speeded up, so stage 1 of the preprocessing unit becomes rate-determining, and this is also faster than the conventional system, so that the overall speed can be further increased.

The delay time of stage 1 in this embodiment is the larger of the delays of the triple generation circuit and the wrap number conversion circuit, but if the operand length is about 64 bits, the delays of these circuits are almost the same ( Therefore, it is about 1 compared to the conventional example.
It is thought that the value will be /2. Also, the delay in the second stage is the delay of the tertiary booth decoder + tertiary booth selector + tertiary booth multiplication tree, which is approximately 2/3 of the delay compared to the 2nd booth multiplier in boat fishing terms. It's time.

The present invention can also be applied to floating point multipliers that use Booth's algorithm of order three or higher. For example, when using the 4th order and 15th order Booth algorithm, the multiples must be 0 to 8 times and 10 to 16 times, respectively. Of these, the numbers that cannot be generated by shift processing are 3x, 5x, and 7x/3x, respectively.

The numbers are 5 times, 7 times, 9 times, 11 times, 13 times, and 15 times, and these are the same as 3 times, shift processing + multiplicand (X)
It can be obtained by adding . Therefore, for example, when using a 4th order booth, it can be implemented by connecting ×5 and ×7 generators in parallel with ×3 generator 14 in Fig. 1 and selecting the output with selector 15. can. In this case, ×5
．． The delay time of the x7 generator is approximately the same as the delay of the x3 generator.

〔Effect of the invention〕

As described above, according to the present invention, since the triple generator and the circuit for converting into normalized numbers operate in parallel, the delay time of the multiplier using the multi-order Booth algorithm can be shortened.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the principle of the present invention, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is an explanatory diagram of a conventional example. In Figure 1, X and Y are input operands, 18 is a selector, and 1
1 is a circuit for converting a non-normalized number into a normalized number, and 14 is a multiple generator.

Claims (1)

[Claims] 1. A circuit for converting a denormalized number into a normalized number in a floating point multiplier that takes a normalized number and a denormalized number as input operands and uses Booth's algorithm of degree 3 or higher (11 ) and a multiple generator (14) containing triples are installed in parallel, and if the input operands (X, Y) are normalized numbers, they are sent to the multiple generator (14).
) side, or if it is a non-normalized number, convert it to the conversion circuit (11
) A floating point multiplier characterized in that it is provided with a selector (18) for inputting to the input signal.