JPH01251384A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To solve nonconformity when a writing operation and a reading operation compete with each other by connecting the node of a memory cell connected to the drain of a transistor for the driving of reading to the gate of this transistor. CONSTITUTION:The memory cell has an information storing circuit composed of a 4-transistor type static cell having polycrystal silicon load resistance and a read only circuit composed of two serially connected transistors Q16 and Q17. Here, one of two nodes N10 and N11 to store information about a 4-transistor type dynamic cell is connected to the gate of the first transistor of the two serially connected transistors Q16 and Q17, a read only word selecting line RW is connected to a second transistor gate, and the drain of a second transistor is connected to a read only bit RB. Thus, a defect that correct information is not written to the memory cell when the writing operation and the reading operation compete with each other can be solved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device such as a MOS type circuit that can perform a write operation and a read operation simultaneously and asynchronously.

[Conventional technology]

Conventionally, a memory cell of this type of semiconductor memory device has two nodes (N20 and N20) that store information, as shown in FIG.
21), transfer transistors (Q22 and Q23) whose gates are connected to the write term selection line WW and transfer transistors (Q24 and Q25) whose gates are connected to the read term selection line RW are connected in parallel. W.B.
WB is a write-only bit line, WW is a write-only word selection line, RB - RB is a read-only bit line, RW is a read-only word selection line, Q22 and Q23 are write-only transfer transistors, Q24 and Q25 are read-only transfer transistors, Q26 and Q27 are flip-flop driving transistors, and R28 and R29 are polycrystalline silicon for load.

FIG. 4 shows an example of a circuit using conventional memory cells. W.B.
-WB is a write-only bit line, WW is a write-only selection line, RB -RB is a read-only bit line, RW is a read-only word selection line, S, A.

is a sense-up circuit.

[Problem to be solved by the invention]

In the conventional memory cell described above, when a write operation and a read operation are performed at the same time, the write bit and the read bit line are electrically connected. If an attempt is made to write reverse information, the potential of the node that stores information in the memory cell will become unstable, and there is a possibility that correct information will not be written.

FIG. 3 shows an example of timing when a problem occurs.

Here the two nodes of the flip-flop N20 and N2
1 has n H” and “L” in the initial state 1 (to), respectively.
Suppose that it was. At tl, read selection line R
W changes from "'L" to "l H1" in Figure 2 Q24 and Q
When the bit lines RB and RB are turned on, "H" and "L" are read out to the read bit lines RB and RB, respectively. In this state, in order to write reverse information to the memory cell, write bit lines WB-W are set to II L" and H" respectively, and write selection line WW is changed from II L" to "H" at tl.
``°'', Q22 and Q23 are turned on, and the write bit line, the node that stores memory cell information, and the read bit line are connected. Therefore, the node 20 that stores memory cell information is connected to Q22 and Q24. Further, the node 21 has an intermediate potential determined by the ratio of the internal resistances of Q2B and Q25.

Also, after this, at time t3, first write term selection line w
If w is °°H°゛→II L II, then Q22 and Q
23 is turned off, and then at time t4, the read term selection line RW is changed from II H" to IT L", Q24 and Q25 are turned off, and the node that stores information in the semory cell is connected to the write bit line and the read bit line. separated.

At this time, nodes N20 and N2 that store information in memory cells
1 becomes H" and "L" as shown in FIG. 3, and the data on the write bit line is not written and the data before writing is held.

In other words, when a write operation and a read operation conflict,
This has the disadvantage that correct information may not be written to the memory cells.

[Means to solve the problem]

The memory cell of the present invention has a polycrystalline silicon load resistance.
It has an information storage circuit consisting of a transistor-type static cell and a read-only circuit consisting of two series-connected transistors. Here, one of the two nodes for storing information of the four-transistor type dynamic cell is connected to the gate of the first transistor of the two transistors connected in series, and a read-only word is connected to the second transistor gate. The selection line is connected and the drain of the second transistor is connected to a read-only bit.

〔Example〕

FIG. 1 is a circuit diagram of an embodiment of the present invention. WB/WB is a write bit line, RB is a read bit line, WW
is the writing term selection line, RW is the reading term selection line, Q
12・QlB is a write transfer transistor, Q14・
Q15 is a driving transistor for forming a flip-flop, Q16 is a read transfer transistor, and Q17
is a read drive transistor.

Here, the operation of the memory cell shown in FIG. 1 will be explained with reference to FIG.

WB-WB in the initial state (tO), respectively.

H", "L", WW as IT L", N10 and N11 as "H", "L", RW as 'L', RB
When RW changes from "L" to +l Hl+ to perform a read operation at time tl, the read drive transistor Q17 is in the on state, so the read transfer transistor Q16 changes to onl and RB. The “IT L” state is read.

In this state, in order to perform a write operation at t2, WW
When it changes from “L” to nH, write transfer transistors Q12 and Q13 become on state fi, and NIO and N
ll is “H”→IT L IT・”L”→”
In the memory cell shown in FIG. 1, unlike conventional memory cells, the read bit line of the internal node of the memory cell is isolated by a gate, so the New information can be written regardless of the state of R18.
R19 is polycrystalline silicon for load, but this may be omitted.

〔Effect of the invention〕

As explained above, the present invention solves the problems encountered in conventional memory cells by connecting the node of the memory cell, which was connected to the drain of the read drive transistor in the conventional memory cell, to the gate of the read drive transistor. This makes it possible to eliminate problems caused by conflict between write and read operations.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram of an embodiment of the present invention. 4 is a conventional circuit diagram, FIG. 3 is a timing diagram showing the operation of FIG. 2, and FIG. 5 is a timing diagram showing the operation of FIG. 1. WB - WB, ... write-only bit line, WW
...Write-only selection line, RB/old...Read-only bit line, RW...Read-only word selection line, NIO/Nil...Node that stores information, Q12 -Q13...Write-only transfer transistor, Q14/Q15...Drive transistor, Q16...Read-only transfer transistor, Q17...Read-only drive transistor.

Claims (1)

[Claims] A semiconductor memory device having a memory cell in which a read operation can be performed asynchronously with respect to a write operation, wherein the memory cell is a 4-transistor type static cell having a polycrystalline silicon load resistance, and a read-only bit line. Of the two nodes that store information of the four-transistor static cell having the polycrystalline silicon load resistor, the node is composed of a read-only circuit consisting of two transistors connected in series between
A semiconductor memory device, wherein one of the two transistors connected in series is connected to the gate of the first transistor, and a read-only word selection line is connected to the gate of the second transistor.