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JPH01256161A - Printed wiring board device - Google Patents

Printed wiring board device

Info

Publication number
JPH01256161A
JPH01256161A JP63084885A JP8488588A JPH01256161A JP H01256161 A JPH01256161 A JP H01256161A JP 63084885 A JP63084885 A JP 63084885A JP 8488588 A JP8488588 A JP 8488588A JP H01256161 A JPH01256161 A JP H01256161A
Authority
JP
Japan
Prior art keywords
frame
copper foil
electronic module
conductor
electronic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63084885A
Other languages
Japanese (ja)
Inventor
Shinpei Yoshioka
心平 吉岡
Masao Segawa
雅雄 瀬川
Yasuto Saito
康人 斎藤
Toshiaki Sato
佐藤　聡明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba AVE Co Ltd
Original Assignee
Toshiba Corp
Toshiba Audio Video Engineering Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Audio Video Engineering Co Ltd filed Critical Toshiba Corp
Priority to JP63084885A priority Critical patent/JPH01256161A/en
Priority to FR8904421A priority patent/FR2629667A1/en
Publication of JPH01256161A publication Critical patent/JPH01256161A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5388—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates for flat cards, e.g. credit cards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H05K1/095—Dispersed materials, e.g. conductive pastes or inks for polymer thick films, i.e. having a permanent organic polymeric binder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10727—Leadless chip carrier [LCC], e.g. chip-modules for cards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1305—Moulding and encapsulation
    • H05K2203/1316—Moulded encapsulation of mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
    • H05K2203/1469—Circuit made after mounting or encapsulation of the components

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Theoretical Computer Science (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To contrive the improvement of the mounting density of electronic components by a method wherein an electronic module, in which a plurality of the electronic components are electrically connected with a copper foil conductor, is fixed by a surface mounting on a main surface utilizing the copper foil conductor formed on a frame. CONSTITUTION:A copper foil conductor 12 is formed on the upper surface of a frame part 11b on the outer periphery of a frame 11, chip components 13 are buried in a recessed part 11c on the inner side of the frame and electrode pads 13a of these components or the pads 13a and the conductor 12 are electrically connected to one another by wiring conductors 15. In a module body with the conductors 15 formed thereon in such a way, a protective coat layer 16 is coated on an upper layer on the conductors 15 to complete an electronic module (printed-wiring board device) 17. This module 17 is mounted on a main substrate 21 through a solder paste 24. Thereby, the mounting density of the chip components can be improved.

Description

【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） この発明は多数の電子回路部品をモジュール化して成る
印刷配線板装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a printed wiring board device comprising a large number of electronic circuit components modularized.

（従来の技術） 近年、メモリカード、ＩＣカード等のカード形電子機器
の開発により、メモリ容最が高く、かつ小形化、１形化
されたより実装密度の高い印刷配線板の構造が望まれて
いる。(Prior Art) In recent years, with the development of card-type electronic devices such as memory cards and IC cards, there has been a desire for a printed wiring board structure that has a high memory capacity, is smaller in size, has a single shape, and has a higher packaging density. There is.

第８図はこの種の電子機器に使用されている従来の印刷
配線板装置を示す断面図である。FIG. 8 is a sectional view showing a conventional printed wiring board device used in this type of electronic equipment.

第８図に示す印刷配線板装置は、樹脂製基板の上に配線
導体層と絶縁層とを順次重ねて形成したものである。即
ち、５１は樹脂製基板（以下基板と称する）、５２はＮ
極バッド５２ａを有する電子回路部品（以下チップ部品
と称する）　、５３．５５は配線導体層、５５は絶縁層
である。チップ部品５２は基板５１に穿設した四部５１
ａに埋設されている。但し、電極パッド部５１ａは基板
表面にと一致して露出している。また、配線導体５３．
５５は、ビアフィル導体５４を介して互いに接続されて
いる。The printed wiring board device shown in FIG. 8 is formed by sequentially stacking a wiring conductor layer and an insulating layer on a resin substrate. That is, 51 is a resin substrate (hereinafter referred to as a substrate), 52 is N
An electronic circuit component (hereinafter referred to as a chip component) having a pole pad 52a, 53.55 is a wiring conductor layer, and 55 is an insulating layer. The chip component 52 has four parts 51 bored in the substrate 51.
It is buried in a. However, the electrode pad portion 51a is exposed along the substrate surface. Further, the wiring conductor 53.
55 are connected to each other via a via fill conductor 54.

以上のような印刷配線板装置は、基板５１の表面及びチ
ップ部品５２の表面に配線導体５３を導体性樹脂ベース
トを用いたスクリーン印刷により形成して、Ｔｉ極パッ
ド５２ａ間を接続する。更に、回路を多層化するため、
絶縁層５６を形成する。絶縁層５６は、感光製ドライフ
ィルムを熱圧着によって貼着して形成されている。この
際、ビアフィル導体５４を形成する。即ち、ビアフィル
導体５４は、上記感光製ドライフィルムを露光、現像し
て間口を形成し、この開口に導電性樹脂ペーストを充填
して成る。そして、更に上層導体として配線導体５５を
導電性樹脂ペーストを用いて形成する。こうして従来の
印刷配線板装置が構成される。In the printed wiring board device as described above, wiring conductors 53 are formed on the surface of the substrate 51 and the surface of the chip component 52 by screen printing using a conductive resin base, and the Ti electrode pads 52a are connected. Furthermore, in order to make the circuit multilayer,
An insulating layer 56 is formed. The insulating layer 56 is formed by pasting a photosensitive dry film by thermocompression bonding. At this time, a via fill conductor 54 is formed. That is, the via fill conductor 54 is formed by exposing and developing the photosensitive dry film to form an opening, and filling this opening with a conductive resin paste. Then, a wiring conductor 55 is further formed as an upper layer conductor using a conductive resin paste. In this way, a conventional printed wiring board device is constructed.

しかし、上記のような印刷配線板装置は、以下のような
点で小形化、Ｎ形化には適さない。However, the above-described printed wiring board device is not suitable for miniaturization and N-shape design due to the following points.

先ず、第１は配線密度が＾いと、配線導体を幾層も形成
しなければ成らず、製造工程が複雑化してしまう。First, if the wiring density is high, many layers of wiring conductors must be formed, which complicates the manufacturing process.

第２に導電性樹脂ペーストによる配線導体５３゜５５は
機械的、或は化学的に生成した銅箔導体より導電性が劣
ることがある。これは実装密度向上のため導体幅を狭く
すると特に顕著となるため、回路に要求される特性によ
っては使用に制限を受ける。Second, the wiring conductors 53, 55 made of conductive resin paste may have poorer conductivity than mechanically or chemically produced copper foil conductors. This becomes particularly noticeable when the conductor width is narrowed in order to improve packaging density, so its use is limited depending on the characteristics required for the circuit.

第３に、チップ部品５２上に配線導体５５を設けるため
、チップ部品５５が実装後に不良と判明した場合に、部
品の交換が困難である。特にチップ部品は極めて小形で
あり、バーンインテスト等の信頼性試験に４３いて検査
電極との接続が困ｎで、直接に信頼性試験を行うことが
できない。このため実装後にテストした場合、不良の発
生によって印１’１配線板装置全体を交換することにな
り、歩留まりが低下し、信頼性も低下する。Third, since the wiring conductor 55 is provided on the chip component 52, if the chip component 55 is found to be defective after being mounted, it is difficult to replace the component. In particular, chip components are extremely small, making it difficult to connect them to test electrodes during reliability tests such as burn-in tests, and it is not possible to conduct reliability tests directly. For this reason, when a test is performed after mounting, the entire wiring board device marked 1'1 must be replaced due to the occurrence of a defect, resulting in lower yield and lower reliability.

（発明が解決しようとする課題） 従来の印刷配線板は、個々のチップ部品を印刷配線板に
直接マウントし、更にその上から導電性樹脂ペーストよ
る配線り休を形成している。このような印刷配線板装置
は配線導体の導電性が低く、かつチップ部品の交換が困
難であるため、不良基板が検出された場合、印刷配線板
装置自体を交換しなければならず、この種の印刷配線板
装置を利用したＩ幾層における歩留まり低下の一因を形
成していた。(Problems to be Solved by the Invention) In conventional printed wiring boards, individual chip components are directly mounted on the printed wiring board, and wiring holes are further formed thereon using conductive resin paste. In such printed wiring board devices, the conductivity of the wiring conductors is low and it is difficult to replace the chip parts, so if a defective board is detected, the printed wiring board device itself must be replaced. This was one of the reasons for the decrease in yield in I layers using printed wiring board equipment.

この発明は上記問題点を除去し、小形化、薄形化を推進
して実装密度の向上を図ると共に、電子ｍ器の歩留まり
低下を回避し、信頼性を高めるようにした印刷配線板装
置の促供を目的とする。This invention eliminates the above-mentioned problems, promotes miniaturization and thinning, improves packaging density, avoids a decrease in the yield of electronic devices, and improves reliability of a printed wiring board device. The purpose is to promote.

［発明の構成］ （課題を解決するための手段） この発明は、フレーム部に銅箔導体を形成し該フレーム
部の内側に埋設された複数の電子部品が前記銅箔導体と
電気的に接続されて成る電子モジュールを用い、この電
子モジュールを前記フレームに形成した銅箔導体を利用
してメイン基板に面付は固定するようにしたものである
。[Structure of the Invention] (Means for Solving the Problems) This invention provides a method in which a copper foil conductor is formed in a frame portion, and a plurality of electronic components embedded inside the frame portion are electrically connected to the copper foil conductor. This electronic module is mounted and fixed to the main board using a copper foil conductor formed on the frame.

（作用） このような構成によれば、複数の電子部品より成る電子
モジュールを単位として信頼性試験が可能となり、歩留
まり低下防止、信頼性が向上する等の利点を有する。ま
た、電子モジュールは実装密度が高く、このような部品
をメイン基板に面付は可能に構成することで、製造工数
が簡素化され、従来の印刷配線板より更に小形化、薄形
化を進めることが可能となる。(Function) According to such a configuration, it becomes possible to perform a reliability test on a unit of electronic module made up of a plurality of electronic components, which has advantages such as preventing a decrease in yield and improving reliability. In addition, electronic modules have a high packaging density, and by configuring such components to be surface-mounted on the main board, the manufacturing process is simplified, making them even smaller and thinner than conventional printed wiring boards. becomes possible.

（実施例） 以下、この発明の一実施例を第１図に基づいて説明する
。(Example) Hereinafter, an example of the present invention will be described based on FIG. 1.

第１図はこの発明に係る印刷配線板装置の一実施例を制
作工程順に示した工程図、第２図は第１図の実施例に用
いる電子モジュールの制作工程を示す工程図、第３図は
その斜視図である。FIG. 1 is a process diagram showing an embodiment of the printed wiring board device according to the present invention in the order of production steps, FIG. 2 is a process diagram showing the production process of an electronic module used in the embodiment of FIG. 1, and FIG. is a perspective view thereof.

本実施例に係る印刷配線板装置は、第２図に示すように
作成した電子モジュールを、第１図に示ηメイン基板に
面付は可能に、構成したものである。The printed wiring board device according to the present embodiment is configured such that the electronic module produced as shown in FIG. 2 can be attached to the main board shown in FIG. 1.

先ず、電子モジュールの作成手順を説明する。First, the procedure for creating an electronic module will be explained.

第２図において、ａに示すようなフレーム１１を用意す
る。このフレーム１１は、外周のフレーム部１１ｂの上
面に銅箔導体１２を形成し、内側の凹部１１ｃがチップ
部品埋設用に貫通された枠体である。このようなフレー
ム１１は、例えばガラスエポキシ等の銅張り樹脂基板を
エツチング、機械加工することにより作成することがで
きる。In FIG. 2, a frame 11 as shown in a is prepared. This frame 11 is a frame body in which a copper foil conductor 12 is formed on the upper surface of a frame portion 11b on the outer periphery, and an inner recessed portion 11c is penetrated for embedding chip components. Such a frame 11 can be created, for example, by etching and machining a copper-clad resin substrate such as glass epoxy.

次に、上記フレーム１１の凹部１１ｃに、第１図すに示
すように、固定用樹脂１４を充填して、集積回路、能動
木子、コンデンサ、抵抗等のチップ部品１３を埋設づる
。このような電子モジュール部品は、通常のチップ部品
と同様に、サーフェイスマウントが可能と／、蒙るよう
に、各チップ部品１３の電極バラド１３ａ　、　１３ａ
が、フレーム部１１ｂの上面と略同−平面になるように
調整する。Next, as shown in FIG. 1, the recess 11c of the frame 11 is filled with a fixing resin 14, and chip components 13 such as integrated circuits, active chips, capacitors, and resistors are buried therein. Such electronic module components can/are surface mounted like normal chip components, so that the electrode pads 13a, 13a of each chip component 13 can be surface mounted.
is adjusted so that it is approximately on the same plane as the upper surface of the frame portion 11b.

上記電子モジュール化の後、第１図Ｃに示づように、チ
ップ部品１３の各電極パッド１３ａ間、或は電極バッド
１３ａと銅箔導体１２間を、配線導体１５によって電気
的に接続する。配線導体１５は、例えばη電性樹脂ペー
ストを用いたスクリーン印刷により形成する。After the electronic modularization, as shown in FIG. 1C, the wiring conductors 15 are used to electrically connect the electrode pads 13a of the chip component 13 or between the electrode pads 13a and the copper foil conductor 12. The wiring conductor 15 is formed, for example, by screen printing using η-conductive resin paste.

上記のごとく配線導体１５を形成したモジュール体に対
し、第１図ｄに示すように、配ｍｓ体１５の上層に保ｙ
！］−ト層１６を塗布して、第３図に示すような、電子
モジュール１７を完成するものである。For the module body in which the wiring conductor 15 is formed as described above, as shown in FIG.
! ]-T layer 16 is applied to complete an electronic module 17 as shown in FIG.

次に、第２図ｄ（第３図）に示す電子モジュール１７は
、第１図に示寸ようにメイン基板２１にマウントする。Next, the electronic module 17 shown in FIG. 2d (FIG. 3) is mounted on the main board 21 as shown in FIG.

第１図ａはメイン基板２１を示す。この図に示すメイン
基板２１は、ガラスエポキシ等の銅張り樹脂基板をエツ
チング処理して得られ、上面に形成した銅箔導体２２を
ソルダーレジスト２３で被覆し、かつソルダレジスト２
３を塗布しない銅箔導体部に半田ペースト２４が印刷さ
れている。電子モジュール１７は、第１図ａに示すよう
な状態のメイン基板２１に、半田ペースト２４を介して
銅箔導体１２と銅箔導体２２とを接続する。つまり、通
常のチップ部品と同様の面付は手法により固定するわけ
である。電子モジュール１１が仮固定されたメイン基板
２１は、リフロー半１０法又はペーパーフェーズ法等で
半田ペースト２４を融解する。これにより、電子モジュ
ール１７の銅箔導体１２と２２とが半田付は固定され、
第３図すに示すように、電子モジュール１７をメイン基
板２１に取付けることができる。FIG. 1a shows the main board 21. FIG. The main board 21 shown in this figure is obtained by etching a copper-clad resin board such as glass epoxy, and the copper foil conductor 22 formed on the top surface is covered with a solder resist 23.
Solder paste 24 is printed on the copper foil conductor portions to which No. 3 is not applied. The electronic module 17 connects the copper foil conductor 12 and the copper foil conductor 22 via the solder paste 24 to the main board 21 in the state shown in FIG. 1A. In other words, the imposition is fixed using a method similar to that of ordinary chip components. On the main board 21 to which the electronic module 11 is temporarily fixed, the solder paste 24 is melted by a reflow method, a paper phase method, or the like. As a result, the soldering of the copper foil conductors 12 and 22 of the electronic module 17 is fixed.
As shown in FIG. 3, the electronic module 17 can be attached to the main board 21.

なお、上記実施例は一例であり、電子モジュール１７は
、第４図に示すように構成しても良い。Note that the above embodiment is just an example, and the electronic module 17 may be configured as shown in FIG. 4.

即ち、第４図ａ、ｂ、ｃは電子モジュール１７に用いた
フレームの構成を示す。先ず、ａに示すフレーム１１′
は、凹部１１ｃを有底の凹部１１Ｃ′　にしたものであ
る。また、このような構成の変型として、凹部１１Ｃ′
　に底面を各チップ部品の高さに合わせて凹凸化するこ
とで電極面とフレーム外周表面との高さ調整が不要にな
る利点もある。　第４図すに示すフレーム１１゛はフレ
ーム部１１ｂにスルーホール接続部３１を形成したもの
である。このようにスルーホール接続部３１を設けるこ
とで、フレーム部１１ｂは両面に銅箔導体１２を形成す
ることができ、メイン基板２１に対し電子モジュール１
７をいずれの面からでも面付けすることができる。第４
図Ｃはフレーム１１ｂの外周を回って銅箔導体１２′を
形成したものである。このようなフレーム１１′。That is, FIGS. 4a, 4b, and 4c show the structure of the frame used for the electronic module 17. FIG. First, frame 11' shown in a
In this case, the recess 11c is changed to a recess 11C' with a bottom. Further, as a modification of such a configuration, the recess 11C'
Another advantage is that by making the bottom surface uneven to match the height of each chip component, there is no need to adjust the height between the electrode surface and the outer peripheral surface of the frame. The frame 11'' shown in FIG. 4 has a through-hole connection portion 31 formed in the frame portion 11b. By providing the through-hole connection part 31 in this way, the frame part 11b can form the copper foil conductor 12 on both sides, and the electronic module 12 can be connected to the main board 21.
7 can be imposed from any side. Fourth
In Figure C, a copper foil conductor 12' is formed around the outer periphery of the frame 11b. Such a frame 11'.

“もスルーホール３１を設けた場合と同様な選択的な面
付けが可能となる。Also, selective imposition similar to the case where the through hole 31 is provided is possible.

第５図は第４図Ｃのフレーム１１°゛°を例にしたこの
発明の他の実施例を示す断面図である。この実施例では
、第１図すとは異なり、チップ部品電極面１８を外側（
上向き）にしてメイン基板２１に取付【プている。この
ような取付構造によれば、電掩面１８が第１図の場合と
異なり外側に向き、メイン基板２１への搭載後に、電子
モジュール１７の検査を行うことができる。又、チップ
部品の交換も容易である。FIG. 5 is a sectional view showing another embodiment of the present invention, taking the frame 11° of FIG. 4C as an example. In this embodiment, unlike the one shown in FIG. 1, the chip component electrode surface 18 is placed on the outside (
(upward) and attach it to the main board 21. According to such a mounting structure, the electronic module 17 can be inspected after being mounted on the main board 21 because the electronic cover surface 18 faces outward, unlike the case shown in FIG. Furthermore, chip parts can be easily replaced.

上記実施例はメイン基板として、片面印哨配線板を用い
ているので、配線密度が高く要求されるときは、両面印
刷配線板或は第６図に示すように構成しても良い。第６
図はこの発明の更に他の実施例を示している。この実施
例は、メイン基板として３層から成る多層基板４１．４
２．４３に電子モジュール１７をマウントしたものであ
る。第６図において、各基板４１．４２．４３はスルー
ホール接続部４５によって、内層の基板４２の両面配線
導体４４．４４と、各外側基板４１．４３の外層に形成
した配線導体４６とが接続されている。また、各外側の
基板４１．４３は、凹部４７が形成され、電子モジュー
ル１７はこれら凹部４７に埋設されている。そして、電
子モジュール１１は、フレームｌｌｂの銅箔導体１２′
が、それぞれ内層基板４２の配線導体４４と外側基板４
１．４３の配線導体４６と接続されている。Since the above embodiment uses a single-sided printed wiring board as the main board, if a high wiring density is required, a double-sided printed wiring board or a configuration as shown in FIG. 6 may be used. 6th
The figure shows yet another embodiment of the invention. In this embodiment, a multilayer board 41.4 consisting of three layers is used as the main board.
2.43 with an electronic module 17 mounted on it. In FIG. 6, each board 41, 42, 43 is connected by a through-hole connection portion 45 to a double-sided wiring conductor 44, 44 of the inner layer board 42 and a wiring conductor 46 formed on the outer layer of each outer board 41, 43. has been done. Further, each outer substrate 41 , 43 is formed with recesses 47 , and the electronic module 17 is embedded in these recesses 47 . Then, the electronic module 11 includes a copper foil conductor 12' of the frame llb.
However, the wiring conductor 44 of the inner layer board 42 and the outer board 4
It is connected to the wiring conductor 46 of 1.43.

このような構成によれば、配線密度が高い場合に適し、
実装密度も高めることができる。This configuration is suitable for cases with high wiring density;
Packaging density can also be increased.

また、第７図はこの発明の更に別の実施例を説明する電
子モジュールを示し、電子モジュール自体を多層配線し
たものである。第７図において、第１図ｄど同一の部分
には同じ符号を付す。第７図の電子モジュール１７′　
は、チップ部品１３の電極パッド１３ａ聞及び銅箔導体
１２と電極バッド１３ａを接続する配線導体１５の上層
に絶縁層１９を形成し、更にその上に配線導体２０を形
成している。このように、電子モジュール自体に多層配
線を施すことで、第６図の実施例と同様の高密度配線を
行うことができる。Further, FIG. 7 shows an electronic module illustrating still another embodiment of the present invention, in which the electronic module itself has multilayer wiring. In FIG. 7, the same parts as in FIG. 1d are given the same reference numerals. Electronic module 17' in FIG.
In this method, an insulating layer 19 is formed between the electrode pads 13a of the chip component 13 and above the wiring conductor 15 connecting the copper foil conductor 12 and the electrode pad 13a, and a wiring conductor 20 is further formed thereon. By providing multilayer wiring in the electronic module itself in this manner, high-density wiring similar to the embodiment shown in FIG. 6 can be achieved.

上記実施例による電子モジュールは、メイン基板との接
続が、通常のチップ部品と同様に面付けによる仮固定が
可能となり、リフロー半田法等を利用することができる
。従って、極めて作業工程が簡素となり、従来のように
配線導体を繰返し多層印刷形成づることなく、高密度の
実装を行うことができる。The electronic module according to the above embodiment can be temporarily fixed to the main board by surface mounting in the same manner as ordinary chip components, and reflow soldering or the like can be used. Therefore, the work process becomes extremely simple, and high-density packaging can be performed without repeatedly printing and forming wiring conductors in multiple layers as in the conventional method.

［発明の効果］ 以上説明したようにこの発明によれば、チップ部品を電
子モジュール化し、メイン基板へのマウントが容易で、
実装密度が高いという効果がある。[Effects of the Invention] As explained above, according to the present invention, chip components can be made into electronic modules, which can be easily mounted on a main board.
This has the effect of high packaging density.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの発明に係る印刷配線板装置の一実施例を示
寸断面図、第２図はこの発明に用いる電子モジュールの
製造工程を示す工程図、第３図は第２図の電子モジュー
ルの斜視図、第４図は伯の構成の電子モジュールを説明
するための説明図、第５図はこの発明の他の実施例を示
す断面図、第６図は更に他の実施例を示１断面図、第７
図は多層配線化した電子計ジュールの断面図、第８図は
従来の印刷配線板装置を示す断面図である。 １１・・・フレーム、１１ｂ・・・フレーム部、１１ｃ
・・・凹部、１２・・・銅箔導体、１３・・・チップ部
品、１４・・・絶縁製樹脂、１５・・・絶縁層、１Ｇ・
・・保護］−ト層、１７・・・電子モジュール、２１・
・・メイン基板。 第５図 第８図FIG. 1 is a sectional view showing an embodiment of the printed wiring board device according to the present invention, FIG. 2 is a process diagram showing the manufacturing process of an electronic module used in the present invention, and FIG. 3 is a diagram showing the electronic module of FIG. 2. FIG. 4 is an explanatory diagram for explaining an electronic module having the configuration described above, FIG. 5 is a cross-sectional view showing another embodiment of the present invention, and FIG. 6 shows still another embodiment. Cross section, 7th
The figure is a sectional view of an electronic meter with multilayer wiring, and FIG. 8 is a sectional view of a conventional printed wiring board device. 11...Frame, 11b...Frame part, 11c
... recess, 12 ... copper foil conductor, 13 ... chip component, 14 ... insulating resin, 15 ... insulating layer, 1G.
・・protection]-to layer, 17 ・・electronic module, 21・
・Main board. Figure 5 Figure 8

Claims (1)

【特許請求の範囲】[Claims] 　フレーム部に銅箔導体を形成し、該フレーム部の内側
に埋設された複数の電子部品が前記銅箔導体と電気的に
接続されて成る電子モジュールと、前記フレーム部に形
成した銅箔導体を利用して前記電子モジュールを面付け
固定するメイン基板とを具備して成る印刷配線板装置。An electronic module including a copper foil conductor formed in a frame portion, and a plurality of electronic components buried inside the frame portion electrically connected to the copper foil conductor, and a copper foil conductor formed in the frame portion. and a main board on which the electronic module is mounted and fixed.
JP63084885A 1988-04-05 1988-04-05 Printed wiring board device Pending JPH01256161A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP63084885A JPH01256161A (en) 1988-04-05 1988-04-05 Printed wiring board device
FR8904421A FR2629667A1 (en) 1988-04-05 1989-04-04 Printed-circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63084885A JPH01256161A (en) 1988-04-05 1988-04-05 Printed wiring board device

Publications (1)

Publication Number Publication Date
JPH01256161A true JPH01256161A (en) 1989-10-12

Family

ID=13843216

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63084885A Pending JPH01256161A (en) 1988-04-05 1988-04-05 Printed wiring board device

Country Status (2)

Country Link
JP (1) JPH01256161A (en)
FR (1) FR2629667A1 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07260669A (en) * 1995-03-28 1995-10-13 Shimadzu Corp Particle size distribution measuring device
KR100434201B1 (en) * 2001-06-15 2004-06-04 동부전자 주식회사 Semiconductor package and fabrication method
JP2010232333A (en) * 2009-03-26 2010-10-14 Shinko Electric Ind Co Ltd Semiconductor device, manufacturing method thereof, and electronic device
WO2020075715A1 (en) 2018-10-12 2020-04-16 富士フイルム株式会社 Material for pearl culturing, nucleus-inserting method, and composition of material for pearl culturing

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2671417B1 (en) * 1991-01-04 1995-03-24 Solaic Sa PROCESS FOR THE MANUFACTURE OF A MEMORY CARD AND MEMORY CARD THUS OBTAINED.
FR2740887B1 (en) * 1995-11-08 1997-12-12 Solaic Sa ARTICLE WITH INTEGRATED CIRCUIT
FR2750232B1 (en) * 1996-06-20 1998-10-09 Solaic Sa CARD-SHAPED SUPPORT FOR AN INTEGRATED CIRCUIT PAD AND ASSOCIATED CONDUCTORS
US6239980B1 (en) * 1998-08-31 2001-05-29 General Electric Company Multimodule interconnect structure and process
KR101084525B1 (en) 1999-09-02 2011-11-18 이비덴 가부시키가이샤 Printed wiring board and manufacturing method thereof
CN101232775B (en) 1999-09-02 2010-06-09 伊比登株式会社 Printed circuit board and method for producing the printed circuit board

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07260669A (en) * 1995-03-28 1995-10-13 Shimadzu Corp Particle size distribution measuring device
KR100434201B1 (en) * 2001-06-15 2004-06-04 동부전자 주식회사 Semiconductor package and fabrication method
JP2010232333A (en) * 2009-03-26 2010-10-14 Shinko Electric Ind Co Ltd Semiconductor device, manufacturing method thereof, and electronic device
WO2020075715A1 (en) 2018-10-12 2020-04-16 富士フイルム株式会社 Material for pearl culturing, nucleus-inserting method, and composition of material for pearl culturing

Also Published As

Publication number Publication date
FR2629667A1 (en) 1989-10-06

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