JPH012432A - Digital frame synchronizer and synchronization method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a digital transmission method, and more particularly to a method for reducing queuing jitter.

Description of the Prior Art In the transmission of digital signals, bit stuff synchronization has become a common method of synchronization for transmitting lower bit rate signals at higher bit rate signals. Some bit stuff synchronization methods have two bit stuff synchronization methods within each channel frame.
This method is referred to as normal pressure and negative stuff synchronization. Such a channel frame with positive and negative stuff synchronization is shown in FIG. 1 and includes two stuff synchronization bit positions S1 and S2. The generation of such channel frames is described in U.S. Patent Application No. 769.427.
No. (filed August 25, 1985).

When the input data bit transmission rate is its rated transmission rate, one of the stuff sync bit positions contains a data bit and the other contains a stuff sync bit. If the input data bit transmission rate is greater than the rated transmission rate, then both stuff synchronization bit positions S1, S2 contain data bits, as is often necessary.

This is commonly referred to as negative stuff synchronization. On the other hand, if the input data bit transmission rate is less than the rated transmission rate, then both stuff sync bit positions contain stuff sync bits, as is often necessary. This is called normal pressure stuff synchronization.

A significant problem with such positive and negative stuffing synchronization methods is that the so-called appointment jitter introduced by the bit stuffing synchronization is too large. bit·
Waiting jitter resulting from staff synchronization is rTran
smith system f'or C.

"Communication Transmission Systems," 5th edition, 1982, published by Bell Telephone Laboratories, 89.
It is disclosed on pages 2-699. Also, the literature r Waiti
ng Time Jitter (D, L, Duttvei)
1er), Bell System Technology Journal (Bel
l System Technical Journal
l), Volume 51, No. 1, January 1972, 185-
207 pages and references rJitter Character
ristics of'Pulse 5tuff'i
ng 5ynchronization (jitter characteristics of pulse-stuff synchronization) JIEEE Communications International Conference Proceedings
l Conference on Communica
ttons), June 1968, pp. 259-284.

In the positive and negative stuffing synchronization methods, the nominal stuffing ratio is 1 when each of the stuffing synchronization bit positions contains one stuffing synchronization bit as the rating. Therefore, as described in the above-mentioned document, the so-called queuing jitter value becomes extremely large, which is extremely undesirable.

It is known that positive stuffing synchronization methods, such as stuffing ratios greater than zero and less than one, significantly reduce queuing jitter.

It is also known that the asynchronous state stuff synchronization method does not introduce queuing jitter.

SUMMARY OF THE INVENTION The problem of queuing jitter associated with so-called positive and negative bit stuffing synchronization methods is overcome by aspects of the present invention, in which digital
In a frame synchronizer, the solution is to controllably adjust the number of input data bits accepted within each frame so that a predetermined stuffing ratio greater than zero and less than one is reasonably achieved.

More particularly, the fractional stuff rate includes controllably increasing the duration of a first set number of intervals in which data bits are written into the synchronizer; and controllably reducing the duration of a second set number of intervals that are included. one data bit is controllably included in one of the stuff sync bit positions occurring during each of the first set number of intervals, and the stuff sync occurring during the second set number of intervals; One non-data bit is forced into one of the bit positions.

In one embodiment of the invention, the predetermined fractional stuffing rate to obtain an acceptable value of queuing jitter is achieved by employing a so-called two-stage stuffing synchronization method. The first stuff synchronization phase includes an asynchronous stuff synchronization method to generate so-called intermediate frames. The second stuff synchronization stage includes a synchronized stuff synchronization method to generate a predetermined output frame. Set number of intermediate frames,
q, forms an intermediate multi-frame. For the first set number, p%, of intermediate frames within a multi-frame, one of the two stuff sync bit positions is always 1.
data bits are forced to be included. The other stuff synchronization bit position may or may not be stuff synchronized. The second set number, q-p,
For intermediate frames, one of the two stuff sync bit positions is deleted, thereby reducing the frame's data carrying capacity by one bit. The other stuff synchronization bit position may or may not be stuff synchronized. Therefore, the stuffing rate for p intermediate frames is 1, and the stuffing rate for qp intermediate frames is 0.

A predetermined fractional stuffing ratio, p/q, for each frame in a two-stage synchronization embodiment is determined according to aspects of the present invention such that the input data bits are accepted for a first set number of intermediate frames of the intermediate multi-frame. controllably increasing the nominal number of input data bits accepted for a second set number of intermediate frames of the intermediate multi-frame; It is obtained by

Increasing and decreasing the nominal number of data bits accepted within a frame of an intermediate multi-frame forces the inclusion of one data bit in one of the stuff synchronization bit positions in a first set number of intermediate frames. That, second
removing one of the stuff synchronization bit positions in a set number of intermediate frames, and generating intermediate frames such that the interval of the intermediate frame is equal to the interval of the output multi-frame, which also has a total number of frames, q. This is achieved by using an intermediate clock frequency that is smaller than a predetermined output clock frequency in a defined manner to achieve this. the predetermined output frame inserting non-data bits into one of the stuff bit positions in the second set number of intermediate frames deleted in the intermediate multi-frames from the second stuffing synchronization stage; , and tU is obtained.

In other embodiments of the invention, buffer storage is advantageously used to obtain a fractional stuffing ratio that provides an acceptable 1, ¥ alignment jitter value.

A predetermined fractional stuffing rate is obtained in part by using a multi-frame format with a set total number of frames, q. This multi-frame format is the same as the output multi-frame format described above and is generated by a two-step stuff synchronization method. For frames with the first set number, pl, in a multi-frame, one of the two stuff synchronization bit positions is 1
data bits are forced to be included. The other stuff synchronization bit position may or may not be stuff synchronized. The second set number, q-p,
For frames, one of the two stuff sync bit positions is forced to contain one non-data bit, thereby reducing the frame's data carrying capacity by one bit.

The other stuff synchronization bit position may or may not be stuff synchronized.

The predetermined fractional stuff rate then increases in a predetermined manner the number of input data bits written into the buffer storage within a frame period of the first set number of multi-frames, pl, according to aspects of the present invention. and reducing in a prescribed manner the number of input data bits written into the buffer register during a frame period of a second set number of multi-frames, q-p. . Therefore,
A predetermined fractional stuffing rate of plq is obtained.

The increment and decrement of data written into the buffer store for each frame is determined by embodiments of the present invention relative to the buffer store read address latch time.
This is achieved by controllably adjusting the buffer storage write address latch time. The latched write address and latched read address in the buffer store for a frame are used to determine whether to stuff synchronize the frame. For the first set number of frames, the latching of the write address is delayed relative to the latching of the read address, thereby providing an interval at which data is written for each of the first set number of frames. is increased. Second
The reduction of the write data to the buffer storage in a set number of frame periods is achieved by returning the delayed latched occurrence of the write address to the initial undelayed position relative to the latched occurrence of the read address. .

At the end of a multi-frame, the read address
The true delay of the write address latch time relative to the latch time disappears, and then the write address latch time delay and advance cycle can be reinitialized for the next subsequent multi-frame.

DESCRIPTION OF THE EMBODIMENTS FIG. 1 shows a so-called channel frame format that includes two stuff synchronization bit positions: 81 and S2 for positive and negative stuff synchronization. The present invention aims at i) eliminating the so-called forced stuffing ratio in such channel frame formats, and is not limited to the particular format shown in Figure '31.

In order to make the explanation simple and easy to understand, here, 1.54
An example is described for the well-known DS1 pulse code modulation (PCM) digital format transmitted at a nominal bit rate of 4 Mbps. The output bit rate in this example is 1.864 Mbps with a channel frame rate of 2K)Iz. Thus, in the channel frame format of FIG. 1, the total number of bits per frame, including overhead bits, is N-832 bits, and the nominal number of input data bits per frame is M-772 bits. However, it should be understood that this unique invention is equally applicable to other bit rates and frame formats.

FIG. 2 illustrates in simplified block diagram form one embodiment of this unique invention for obtaining a predetermined fractional pressure stuffing rate in a so-called pulse-stuff synchronizer. It will also be appreciated that such synchronizers are typically used to synchronize digital signals at a lower bit rate for transmission at a higher bit rate. Accordingly, an asynchronous stuff synchronizer 201 is shown that provides a first stage of stuffing synchronization and provides a predetermined fractional stuffing rate to generate so-called intermediate frames. The sync state stuff synchronizer 202 then performs a second stuff synchronization process to generate an output frame having a predetermined format.
Provide stages. Clock converter 2 that generates the intermediate clock (CLKINT) signal used in embodiments of the invention
03, an intermediate frame format generator 204,
Also shown is an output frame formatter 205.

Thus, in this embodiment, the DSL input to the DATA IN input of the asynchronous stuff synchronizer 201 is
PCM signal is provided and the asynchronous state stuff synchronizer 2
DSII to CLK IN input of 01.

The 544 MHz clock signal (CLKINT) has a frequency of 1.683 MHz in this example and is used to generate intermediate frames in accordance with aspects of the present invention, as described below. The CLKINT clock signal is also provided to intermediate frame format generator 204, which controls asynchronous state stuff synchronizer 201 to generate an intermediate frame format, also described below. Such asynchronous state stuffing synchronizers, which are advantageously used in embodiments of the present invention to generate the unique intermediate frame τ-format of the present invention, are known to those skilled in the art. For example, rWait
ingTime Jitter J and rJitter
rCharacterisNcof'Pulse
Stuffing 5ynchronization
See the aforementioned document entitled J.

Generating an output frame having a predetermined format and a predetermined fractional stuff rate under the control of the output frame formatter 205, the output from the intermediate frame formatter 204, and the output clock (CLKOUT) signal. To do this, the synchronous stuff synchronizer 202 is supplied with the intermediate frame output of the asynchronous stuff synchronizer 201 and CLKINT. Such sync state stuff synchronizers are also known to those skilled in the art.

In this example, the 1.684MHz CLKOUT
A clock converter 203 is used to generate CLKINT of 1.683 MHz from .

The frame synchronizer shown in FIG. 2 produces a predetermined out-of-sync stuff rate of approximately p/q. The predetermined stuffing rate changes the input DS1 data signal to a predetermined output frequency, CLKOUT
, the asynchronous stuffing synchronizer 201 under the control of the CLKINT and intermediate frame format generator 204 to asynchronously stuff synchronize the intermediate frame format of CLKINT, at a reduced frequency compared to CLKINT, . By using it, a predetermined staffing rate can be obtained. The output from the asynchronous state stuff synchronizer 201 in the intermediate frame format shown in simplified form in FIG. Frame format generator 204 and CLKOUT
output frame φ format generator 20 combined with
5 is stuffed to the synchronous state within the synchronous state stuffing synchronizer 202. Output frame formatter 205 responds to the output from intermediate frame formatter 204 by placing non-data bits in appropriate stuff sync bit positions within the so-called X-frames of the output frame format of FIG. Insert controllably.

The operation of the asynchronous state stuff synchronizer 201 and the synchronous state stuff synchronizer 202 is to combine the effects of p frames containing a data bit in one of the stuff synchronization bit positions onto q frames of the multi-frame. distribution evenly.

The overall spacing of the intermediate multi-frames is equal to the overall spacing of the output multi-frames. However, the individual frame intervals within the intermediate frame are longer in time for a first predetermined number of frames and shorter in time for a second predetermined number of frames than in the output multi-frame.

As shown in Figure 3, p frames or long frames have a data carrying capacity of M+1 bits because one of the stuff synchronization bit positions, D (Figure 3), is forced to support a data bit. The q-pH frame or ring frame, on the other hand, has a data carrying capacity of M bits because one of the meta2 synchronization bit positions has been deleted. Similarly, p frames each have a total of N bits, while q
-p(fJl frames each have a total of N-1 bits.

An output multi-frame containing q frames is then generated by the synchronous stuff synchronizer 202 at a predetermined output clock frequency CLKOUT, as shown in FIG. The d-frames of the output multi-frames correspond to frames where the stuff sync bit positions include data bits D in FIG. 4, while the X frames correspond to frames where the stuff sync bit positions include non-data bits in FIG. X
Corresponds to the frame containing the .

-i, for the embodiment of the invention shown in FIG.
), where CLKINT is the intermediate clock frequency,
CLKOUT is the output clock frequency, p is the number of long or d-frames, q is the total number of frames in the multi-frame, and FR is the output frame rate.

Therefore, in this embodiment, CLKOUT-1,68
Since they are 4 MHz Sp -1, Q-2 and FR-2 KHz, CLKINT -1,883 MHz.

The interval between long frames as shown in FIG. , and N
is the total number of bits in the output frame.

The spacing of the ring frames as shown in FIG.
) hooms).

For each long frame, the data carrying capacity is M+1
The nominal input data for each long frame is MR, bit. At this time, the direct stuffing rate Sl for the long frame is S −1−M (R, −1
) (6) becomes.

For each of the mute frames, the data carrying capacity is M bits, and the rated input data rate for each of the ring frames is MR5. In this case, the direct stuffing rate S for the ring frame is 58-M (I R3>
(7) becomes. It can be seen that the average stuffing rate for the entire intermediate multi-frame is S or Ss, both of which are close to Sav, but not exactly S.

v To accept asynchronous DS1 for synchronous output at an output clock frequency CLKOUT of 1.684 MHz,
Consider an example where a staff ratio of 1/2 is preferable. At this time, p/q-1/2, N-832 (Fig. 1), M-77
2 (Figure 1), and CLK INT-1,663M11
z (Equation 1).

The asynchronous state stuff synchronizer 201 (FIG. 2)
Under the control of KINT and intermediate formatter 204, an intermediate multi-frame format having two frames (FIG. 3) is created.
Generate a frame. One of the intermediate frames is a long (p) frame with 832 bits, and the other is a short frame with 831 bits.

The stuffing rate for a frame can be defined as the difference between the data bit carrying capacity for that frame and the actual number of data provided for that frame. For each long frame, the data carrying capacity (FIG. 3) is M+1 or 773 bits, while the actual number of data bits provided during each long frame is 772.
It is 484. Therefore, the actual stuffing rate for long frames is S, -0,484 from Equation 6. Therefore, the average stuffing rate for the entire intermediate multi-frame is S −0
, 5, which is a predetermined stuffing ratio p/q=1/2.

FIG. 5 shows, in simplified block diagram form, details of another embodiment of the invention for obtaining a predetermined fractional stuffing ratio for the frame format of FIG. This example also assumes that the input data is 1.degree. 544 MHz and the input clock frequency CLKOUT is 1.664 MHz. Therefore, the buffer storage to which data is written is indicated via DATA IN, and the data is
Read via OUT. Buffer record 2 device 501
The writing of data within t\ is performed using input clock signal CLKI.
is controlled by the write address generated by write counter 502 in response to N. Also in this embodiment, the predetermined rated value of CLKIN is 1.544 MHz. Write address latch 504 is also written 502
The write address latch 504 is supplied with the write address from the counter 5 at a specific time in response to the signal WALT.
Used to latch or store the write address from 02. That is, the write address stored in write address latch 504 is at a particular write address latch time (WALT). Similarly, reading data from buffer store 501 is controlled by a read read address generated by read counter 503 in response to output clock signal CLKOUT. In the second embodiment, CLKOUT is also 1.664MII
It is z. Read address latch 505 is also supplied with read power, read read address from counter 503, and 1.
Read address latch 505 is used to latch or store the read address from counter 503 at a particular time in response to signal RALT. That is, the read read address stored in read read address latch 505 is at a particular read read address latch time (RALT). The addresses stored in write address latch 504 and read address latch 505 are compared in stuff synchronization decision unit 50B to determine whether a bit should be stuffed (stuff synchronization).

Output from stuff synchronization determiner 506 is provided to read counter 503 to control stuff synchronization. Buffer storage 5 suitable for cooperating with frame assembler 509 to form a predetermined output frame.
Read counter 503 is also responsive to the output from frame formatter 508 to control the data output from frame formatter 508.

Delay controller 507 determines the write address latch time (WALT) based on the delay reference signal and under control of the read address latch time (RALT) signal and the delay select signal from frame formatter 508.
Generate a signal. The delay reference signal is the input clock CLKI
It may be N or the output clock CLKOUT. When a delay line is used within delay controller 507, a delay reference signal is not required.

The decision whether to perform stuff synchronization is made by the stuff synchronization determining device 506 within each frame. Until now, stuff synchronization decisions have been made by latching the write and read addresses simultaneously at a fixed time every frame.
This was then done by comparing them. Simultaneously latching the write and read addresses at fixed times within each frame ensures that, for each frame, the interval at which data is written into the buffer storage is equal to the interval at which data is read from the buffer storage. means.

If the address gap between the write address and the read address is below a predetermined threshold, a decision is made to perform a stuff synchronization, otherwise no stuff synchronization occurs.

Predetermined output frames are generated by frame assembler 509. For this purpose, frame assembler 509 is provided with overhead bits (OH) and data output from buffer storage 501. Assembler 509, under the control of frame formatter 508 and CLKOUT, generates output frames as shown in simplified form in FIG. 4 and, in particular embodiments, as shown in simplified form in FIG. .

In the embodiment of FIG. 5, the predetermined asynchronous state stuffing rate is determined by buffer storage 501 for reading data such that an output multi-frame format as shown in simplified form in FIG. 4 is obtained from assembler 509. obtained by controlling the

If the write address and read read address are latched simultaneously at a fixed time as before, then the d-frame and the
The direct stuffing ratios for the frame are 1 and 0, respectively. However, in accordance with one aspect of the present invention, if the write address latch time (WAL T) is adjustable with respect to the read address latch time (RA L T'), A change in writing interval is obtained. Therefore, it is written to buffer storage 501. The number of input data bits changes from frame to frame. This change in the number of data bits written to buffer storage 501 is utilized in accordance with one aspect of the present invention to obtain a predetermined fractional stuffing rate.

Generally, WALT and RALT times are aligned at the end of the previous last multi♦ frame cycle.

Next, for the first d-frame in the multi-frame, WALT outputs the asynchronous state human clock CLKIN (1-
p/q) UI is delayed, while RALT is not changed. The interval between writes into buffer storage 501 is therefore increased. UI is a unit interval corresponding to one clock pulse. Then, the nominal input data rate written into buffer store 501 during the incremental write interval is M+
(1-p/c+) bits, while the number of data bits read from the buffer store 5 remains fixed at M+1 bits.

Therefore, the direct stuffing rate Sd for the d-frame is p
/q becomes. For the next d-frame, WALT is R
delayed by 2 (1-p/q) UI relative to ALT;
This provides a net increase in (1-p/q) UI write interval. In this way, WaVt, WALT for the pth d-frame is p (1-p/
q) Delayed by UI. For the (p+1)th frame, i.e. the first X-frame, p (1-p/q)
The WALT is advanced by p/qUI with respect to the previous or pth WALT to generate a total delay of -p/qUI. Therefore, for this X-frame, the write interval is reduced by p/QUI relative to the read interval, and the nominal number of human data bits written to buffer store 501 is M-p/q bits. The data read from storage 501 into the buffer for this X-frame.
The number of bits is M bits. Therefore, the direct stuffing ratio Sx for the X-frame is p/q. Advancing WALT by p/q U I for each X-frame continues until the q@th frame. In the qth frame, any time difference between the occurrence of WALT and RALT disappears, and at the beginning of another multi-frame cycle, WALT and RALT are made coincident in time.

As a specific example, if CLKOUT is used as the WALT delay/advance criterion, the d-frame stuffing rate Sd and the X-frame stuffing rate Sx are respectively Sd-1-M/N (1-p /q) (9) and Sx-CM/N)-(p/q) (to). Since one UI of the output clock signal CLKOUT is equal to M/NUI of the input clock signal CLKIN,
It goes like this. The operation of the embodiment shown in FIG. 5 where the average stuffing rate across multiple frames then obtains a predetermined fractional asynchronous stuffing rate for the frame format of FIG. 1 can be best illustrated by a specific example. Therefore,
Consider again the DSI PCM signal acceptance example with an asynchronous state fractional stuff rate of p/q-1. A data bit inserted in one stuffing sync bit position for q d-frames and a non-data bit inserted in one stuffing sync bit position for qp X-frames. The predetermined relationship between WALT and RALT for the output multi-frame containing is shown in FIG. Therefore, under the control of frame formatter 508 and delay controller 507, WALT is matched with RAL T at the end of the last previous multi-frame cycle.

Also in this embodiment, the delay reference provided to delay controller 507 is output clock signal CLKOUT. Then, for a d-frame, the data bit is forced into one of the stuff sync bit positions, D (FIG. 6), and into the other stuff sync bit position, Sl
is staff synchronized and is independent of decisions made in the staff synchronization determiner 506. RALT causes the read address generated by read counter 503 to be latched in read address latch 505 at a fixed time. R.A.
A delay controller 507, responsive to LT and a delay selection signal from frame format shaper 508, and responsive to CLKOUT, sets WALT to 3/4UI, or CLKOUT.
Delay by 3p/QUI of OUT. Therefore, the write interval for d-frames is 3/4 UI of CLKOUT.
only increased. Therefore, the direct stuff rate Sd for the d-frame is 0.304 from equation (9). For the next frame in the multi-frame, i.e. the first
4UI, or 2p/qUI of CLKOUT, under the control of frame format shaper 508 and CLKOUT. Therefore, the write interval is 1/4 U I with respect to the read interval, that is, p/of CLKOUT.
reduced by qU I. Similarly, for the next
You will be re-proceeded to be in the UI. Again the writing interval is l
/4 U I, i.e. p/q U of CLKOUT
It was decreased by 1. For the last X-frame, R
The delay of WALT with respect to ALT is WALT and RALT
The process will proceed again so that there will be no delay between the two. Here again the write interval has been reduced by 1/4 UI of CLKOUT. For the beginning of other multi-frame cycles,
The times of WALT and RALT are made to match again. Therefore, the direct stuffing rate Sx for the X-frame is calculated by the formula (
10) to 0°232. The average stuffing rate S for the multi-competition frame is 0.25 or 1 from equation (11).
)/'Q-1 Hatev Yes.

[Brief explanation of the drawing]

FIG. 1 shows a conventional channel frame format including stuff synchronization bit positions to perform positive and negative stuff synchronization; FIG. FIG. 3 is a block diagram in simplified form detailing an embodiment of the present invention including two-stage stuff synchronization; FIG. 3 shows an intermediate multi-frame in simplified form used to describe the embodiment of FIG. FIG. 4 is a simplified form of the output multi-frame used to explain the embodiments of FIGS. 2 and 5; FIG. FIG. 6 is a block diagram in simplified form of details of another embodiment of the invention including a buffer storage for obtaining a 114 predetermined fractional stuffing rate; and FIG. 5 shows the relationship between write address latch time and read address latch time in the embodiment of FIG. 5 of FIG. Applicant: American Telephone AND0B ≧ Mi FIG, 3 FIG, 4 Mei ← Mi Go

Claims (10)

[Claims] (1) A digital signal at a first bit rate is transferred to a second higher bit rate using bit stuffing synchronization for transmission within an output frame format with a set fractional stuff rate. In a digital frame synchronizer to be synchronized: comprising varying means for controllably varying the interval at which data bits are input to said synchronizer in a predetermined manner so as to obtain a fractional stuffing ratio; A digital frame synchronization device characterized by: (2) The changing means includes increasing means for increasing in a first defined manner the duration of a first set number of intervals at which data bits are input into the synchronizer. A digital frame synchronizer according to claim 1. (3) The changing means further includes reducing means for reducing the duration of a second predetermined number of intervals during which data bits are input into the synchronizer in a second prescribed manner. A digital frame synchronization device according to claim 2. (4) The digital frame synchronizer according to claim 3, further comprising adjusting means for adjusting the data carrying capacity of the output frame from the synchronizer. (5) said adjusting means includes inserting means for inserting one data bit into a predetermined one of stuff synchronization bit positions occurring during each of said first set number of intervals; A digital frame synchronization device as claimed in claim 4. (6) The adjusting means further includes inserting means for inserting one non-data bit into a predetermined one of the stuff synchronization bit positions occurring during each of the second set number of intervals. A digital frame synchronization device according to claim 5, characterized in that: (7) The interval is a frame interval, and the interval of the first set number and the interval of the second set number are multi-frame frames having a total number of set frames equal to the sum of the first and second set numbers. 7. The digital frame synchronization device according to claim 6, wherein the digital frame synchronization device forms a frame. (8) The fractional stuffing rate is obtained for the multi-frame, and the fractional stuffing rate is equal to the first set number divided by the set total number. A digital frame synchronizer according to scope 7. (9) A method of synchronizing a digital signal at a first bit rate to a second higher bit rate using bit stuffing synchronization for transmission within an output frame format; - increasing the duration of a first set number of intervals during which bits are written into the bit stuff synchronizer; and a second set number of intervals during which input data bits are written into said bit stuff synchronizer. A method for digital frame synchronization, characterized in that: reducing the duration of the interval, where a fractional stuffing rate is determined; (10) inserting data bits into stuff synchronization bit positions that occur during each of said first set number of intervals; and stuff synchronization that occurs during each of said second set number of intervals. 10. The digital frame synchronization method of claim 9, further comprising: inserting non-data bits within the bit positions.