JPH01246874A - Bipolar transistor and manufacture thereof - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a bipolar transistor and a method for manufacturing the bipolar transistor, in particular, the so-called graft base and emitter region, which are the base electrode extraction regions, are made of an impurity-containing semiconductor layer, such as polycrystalline silicon. The present invention relates to a bipolar transistor which is commonly used and suitable for a so-called double polysilicon type transistor formed by diffusion of impurities, and a method for manufacturing a similar bipolar transistor.

[Summary of the invention]

The present invention provides a bipolar transistor whose base region has at least a graft base and an intrinsic base,
The depth of the intrinsic base formed directly below the emitter region in the base region, especially between the graft base and the intrinsic base, with a deep connection region on the graft base side and a shallow connection region on the intrinsic base side. Avoid direct contact of the diffusion suppression area with the graft base,
The present invention provides a bipolar transistor that avoids a reduction in breakdown voltage and an increase in junction capacitance due to direct contact between the diffusion region and the graft base, and further improves high-speed performance, and a method for manufacturing the bipolar transistor.

[Conventional technology]

Recently, by introducing impurities into a semiconductor substrate from first and second semiconductor layers, for example, a polycrystalline silicon layer, which serve as a base extraction electrode and an emitter extraction electrode, respectively, the base electrode extraction region of the base region, that is, the graft base and the emitter region, are For example, a self-line (
The so-called double polysilicon type bipolar transistor, which is designed to achieve self-alignment (self-alignment), has been attracting attention because of its ability to reduce the area and achieve high speed.

In this case, the base active region surrounding the emitter region, that is, the base operating region, the so-called intrinsic base, is formed by implanting impurity ions through an opening (window) in which the first semiconductor layer serving for the formation of the graft is removed. conduct.

[Problem to be solved by the invention]

However, in the so-called double polysilicon bipolar transistor mentioned above, the intrinsic base is formed by ion implantation, and this intrinsic base is damaged during the ion implantation, causing accelerated diffusion in the intrinsic base itself. For this reason, or because it is difficult to make the depth stable and sufficiently shallow due to channeling tails, etc., the distance between the emitter region and the collector region, that is, the base width WB, is relatively high, and the emitter common current amplification factor hFE is not sufficiently increased. There are problems such as not being able to increase the temperature or causing instability in its characteristics.

In order to solve these problems, the present applicant previously proposed in Japanese Patent Application No. 62-75096 a method in which, for example, an intrinsic base is first formed from the second semiconductor layer forming the emitter region before forming the emitter region. We have proposed a method in which an emitter region is formed by introducing an impurity into the semiconductor layer, followed by introducing an impurity of a different conductivity type through a similar second semiconductor layer. In this case, a connection base region is formed to connect the intrinsic base and the graft base, and this connection base region is formed by implanting impurity ions. However, with this method,
When ion-implanting the connection base region, channeling tails and the like occur due to damage during ion implantation as described above, and this connection region also enters under the intrinsic base, making it virtually impossible to sufficiently reduce the base width WB. Challenges arise.

In order to deal with this, the present applicant has proposed a method for controlling the depth of the base region under the base region in a patent application entitled "Bipolar Transistor and Method for Manufacturing the Same" dated February 16, 1988. We have proposed a bipolar transistor in which a type diffusion suppression region is provided.

FIG. 2 is a cross-sectional view of an example of this bipolar transistor applied to an npn type transistor. In this case, a p-type silicon semiconductor substrate (11) faces the entire surface and an n-type collector buried region (11) with a high impurity concentration.
After selectively forming a channel stopper region 2) and a p-type high concentration channel stopper region (3), a semiconductor substrate (5) is obtained by epitaxially growing a silicon semiconductor layer (4) which will become an n-type collector region. It will be prepared. Then, an isolation insulating layer (7) is formed by local oxidation across the semiconductor layer (4) at the element isolation part and the isolation part between the high concentration collector electrode extraction region (6) and the base region forming part. The collector electrode extraction region (6) is formed to a depth that reaches, for example, the collector buried region (2) by introducing n-type impurities at a high concentration by ion implantation or the like. On the other hand, the semiconductor layer (
4) An impurity-containing first semiconductor layer (8), such as a polycrystalline silicon layer, which will become a base extraction electrode is deposited on the upper transistor formation part, and a surface insulating layer (16) such as 5i02 is deposited on top of this. be done. In the first semiconductor layer (8) and the insulating layer (16) thereon, a window (22) is formed above the transistor forming part, as shown in FIG. 3A, which is a cross-sectional view of the main part thereof. Then, a buffer layer (23) made of a thin 5i (h oxide film) is deposited inside this window (22), and then a first semiconductor layer is formed by penetrating through this buffer layer (23) and under the window (22). Using (8) and the insulating layer as a mask, p-type impurity ions such as B'' and BF2+ are implanted shallowly into the connection region between the graft base and the intrinsic base (see FIG. 2).
An impurity implantation region (241) forming the region (24) is formed, and then n-type impurity ions such as P" (phosphorous ions) are similarly implanted through the window (22) to form the region (24).
4s) Diffusion suppression region (10
) an impurity implanted region (101) is formed. After that, insulate N such as 5i02 including the inside of the window (22).
(16) is formed on the entire surface.

Thereafter, an annealing treatment is performed to form a graft base (9) by introducing impurities from the impurity-containing first semiconductor layer, and to activate regions (1 (h) and (24t), respectively). As shown in FIG. 3B, a diffusion suppression region (10) and a connection region (24) are formed.

Next, the insulating layer (16) is etched over the entire surface, for example, the upper insulating layer (16) is removed and the window (22) is removed.
) Sidewall (11) due to the portion left unetched due to the large substantial thickness of the side surface inside
form.

Then, as shown in FIG. 2, a second semiconductor layer (for example, a polycrystalline silicon layer) (13) is deposited on the inside of the window (12) surrounded by the sidewall (11),
An n-type impurity is ion-implanted into this, and an intrinsic base (14) is formed by diffusion of the impurity, and further an n-type impurity, for example, A
An emitter region ('15) is formed by ion implantation of s0 and subsequent diffusion. The insulating layer (16) is formed on the collector electrode extraction region (6) and on the base extraction electrode (17) made of the first semiconductor layer (8) containing impurities and having low resistance, respectively. An electrode window is formed, and a collector salt i (18) and a base electrode (19) each consisting of a metal electrode are ohmically deposited, and at the same time, a second impurity-containing semiconductor layer is formed. (13) Al metal emitter electrode (21) on the emitter extraction electrode (20)
It is constructed by being coated with

A transistor with such a configuration has a diffusion suppression region (
The existence of the intrinsic base (14)
) and the connection region (24), even if a channeling tail or the like occurs during ion implantation, the conversion to n-type is prevented by cancellation by the p-type impurity in the diffusion suppression region (10), so that the intrinsic base (14) and the problem that the depth of the connection region (24) becomes large is avoided. However, in the bipolar transistor obtained by such a method, the diffusion suppressing region (10) tends to be formed in direct contact with the highly concentrated graft base (9), which leads to a decrease in breakdown voltage and junction failure. The issue of increasing capacity arises.

In order to avoid such inconvenience, for example, the fourth
As shown in FIG. A, an ion implantation region (241) for forming a connection region (24) is first formed by the same method as explained in FIG. 3A, and then as shown in FIG. 4B. A side wall (11) is formed, and then p-type impurity ions are implanted to form a diffusion suppressing region (10), and an annealing treatment is performed to form a graft base (9) in the same manner as described in FIG. 3B. It is also conceivable to form a connection region (24) and a diffusion inhibition region (10) so that the diffusion inhibition region (10) exists apart from the graft base region (11). In FIG. 4, parts corresponding to those in FIGS. 2 and 3 are designated by the same reference numerals, and redundant explanation will be omitted.

However, in this case, carriers are injected from the emitter in the connection region (24) as shown by the arrow in FIG. An increase in WB occurs resulting in a decrease in hFt.

The present invention provides bipolar transistors and bipolar transistors that solve the problem of a decrease in <hrg based on the existence of an operating region around the emitter without causing a decrease in breakdown voltage or an increase in junction capacitance as described above. Provide manufacturing method.

[Means to solve the problem]

As shown in the cross-sectional view in the first figure, the present invention provides a first conductivity type semiconductor region, for example, a semiconductor layer (4), a second conductivity type graft base (9) and an intrinsic base (14), and a first conductivity type semiconductor region, for example, a semiconductor layer (4). In a bipolar transistor having a conductivity type emitter region (15), the graft base (9) and the intrinsic base (14) are connected to a first connection region (41) formed deeply on the graft base (9) side. , a second connection region (42) formed shallowly on the intrinsic base (14) side,
And these regions (41) (42) are graft base (
9) and the intrinsic base (14) through a connection region (40) consisting of a second conductivity type low concentration impurity region having a lower concentration than the intrinsic base (14).

Further, the present invention provides a first conductivity type semiconductor region, for example, a semiconductor N
(4) includes a step of forming a first second conductivity type high concentration impurity region, that is, a graft base (9); and a step of forming a first second conductivity type high concentration impurity region (graft base (9)). Step 2 of forming a second conductivity type low concentration impurity region (first connection region (41)) and forming a second conductivity type low concentration impurity region (first connection region (41)) In the vicinity of the junction with the region (4), a first conductivity type impurity is introduced into a region separated from the first second conductivity type high concentration impurity region (graft base (9)) to form a diffusion suppression region (10). a third second conductivity type low concentration impurity region (second connection region (42)) shallower than a second second conductivity type low concentration impurity region (first connection region (41)); ) and forming an intrinsic base of the second conductivity type in the third low concentration impurity region of the second conductivity type (the second connection region (42)).
A bipolar transistor is obtained through a step of forming a conductive type emitter region.

[Effect]

According to the present invention described above, by arranging the diffusion suppressing region (10) at a position apart from the highly concentrated graft base (9), the problem of a decrease in breakdown voltage and an increase in parasitic capacitance based on junction capacitance are solved. In addition to solving the problem of lowering, since the emitter region (15) side of the connection region (40) is configured with a shallow second connection region (42), Substantial base width increases are avoided and hFE decreases are avoided.

〔Example〕

An example of a bipolar transistor, particularly an npn type bipolar transistor, according to the present invention and a manufacturing method according to the present invention will be explained in detail with reference to FIG. In FIG. 1, parts corresponding to those in FIG. 2 are designated by the same reference numerals, and redundant explanation will be omitted.

As shown in FIG. 1A, for example, a p-type silicon semiconductor substrate (1) is prepared in the same manner as explained in FIG. ) and p-type high concentration channel stopper region (3
) is selectively formed, and on this substrate t1), an n-type semiconductor layer, that is, a semiconductor region (4) having a conductivity type different from that of the substrate (1) is epitaxially grown to form a semiconductor substrate (5). Next, although not shown, for example, silane nitride 5iNxlQ is deposited in a desired pattern, and this is used as a mask to divide the field area around the element formation area and finally the area that separates the base area and collector electrode extraction area of the bipolar transistor. Then, local oxidation is performed to form an isolation insulating layer (7) made of a thick SiO2 oxide film. Thereafter, the SiNx film that serves as a mask for the selective diffusion described above is removed, and an ion implantation mask layer (not shown) made of photoresist, for example, is formed in the area other than where the collector electrode extraction region is formed, and n-type impurity ions are implanted. is performed from the surface of the semiconductor layer (4) to form a low resistivity collector electrode extraction region (6).

Thereafter, the ion implantation mask is removed, and a first semiconductor layer (8) containing a nonwoven fabric, such as a polycrystalline silicon layer (8), is formed on the entire surface by, for example, the CVD method, and the portions other than the base region and emitter region forming portion are etched away. Next, a surface insulating layer (16) of 5i02 etc. is formed on the entire surface by CVD method etc., and this 5i (h insulating layer (16)
) and the first impurity-containing semiconductor layer (8).
2).

The semiconductor layer (4) exposed through this window (22)
), a thin buffer FA (23) of SiO2 or the like is formed, and p-type impurity ions such as B+ or BF2+ are implanted through this to form an impurity implantation region (40) that will finally form the connection region (40). 401).

Next, a similar 5i (h) insulating layer is formed on the entire surface of the insulating layer (16) by CVD or the like, and then annealing is performed to activate the implanted impurity in the region (401). , as shown in FIG. 1B, the connection area (40)
A graft base (9) is formed by forming and diffusing impurities from the first semiconductor layer (8).

Then, since the insulating layer remains on the inner peripheral surface of the window (22), which has been etched back by, for example, RTE (reactive ion etching) and has become substantially thicker, the first side A wall (lll) is formed, and a first window (121) surrounded by this side wall (llt) is formed. And this window (l
h) A buffer layer (23) consisting of a thin insulating layer of SiO2
) is formed again, and through this, n-type impurity ions are implanted to form an impurity implantation region (101) for finally forming a diffusion suppressing region. In this case, the region (101) is formed at a position separated from the graft base (9) by a required distance due to the presence of the sidewall (llr).

As shown in FIG. 1C, a second sidewall (112) is formed again by the same method, and a second window (122) surrounded by this second sidewall (112) is formed.
), and the entire second area including the inside of this window (122)
depositing a semiconductor layer, for example a polycrystalline silicon layer (13);
Through this, p-type impurity is ion-implanted to form an impurity implantation region (141) that forms an intrinsic base, and p-type impurity As+ is then ion-implanted to form an emitter electrode (15). do.

Thereafter, as shown in the first diagram, a collector electrode (18) is ohmically formed in the collector electrode extraction region (6), and a base electrode (18) is formed on the base extraction electrode (17), that is, the first impurity-containing semiconductor layer (8). 11 electrodes (19) and an emitter electrode (21) on the emitter extraction electrode (20) made of the second semiconductor N (13).
The desired npn transistor is obtained by simultaneous deposition of a metal layer over the entire surface and its patterning.

In the thus obtained bipolar transistor, the graft base (9) and the diffusion suppressing region (10) are separated from each other by a distance d between them. Also, the intrinsic base (14
) and the graft base (9) for connection area (40)
is the diffusion suppression region (10) on the graft base (9) side.
The region is deep due to the absence of region (10), and shallow on the intrinsic base (14) side due to the presence of region (10). In other words, the connection area (40) is the deep first connection area (41)
and a shallow second connection region (42).

Note that the present invention is not limited to the above-mentioned npn type bipolar transistor, but can also be applied to pnp transistors, and various modifications and changes can be made.

〔Effect of the invention〕

According to the present invention, the diffusion suppressing region (10) is placed at a position apart from the highly concentrated graft base 9), which solves the problem of a decrease in breakdown voltage, an increase in parasitic capacitance based on junction capacitance, and a decrease in high speed performance. In addition to solving the problem, since the emitter region (15) side of the connection region (4o) is configured with a shallow second connection region (42), the effect of providing the connection region is An increase in target base width is avoided, and a decrease in hFE is avoided.

[Brief explanation of the drawing]

Figures 1A-D are process diagrams of an example of the manufacturing method of the present invention, Figure 2 is a sectional view of a comparative example of the present invention, Figures 3A and B are manufacturing process diagrams, and Figures 4A-C are It is a comparative manufacturing process diagram. (4) is a semiconductor region, (5) is a semiconductor substrate, (m) is a graft base, (14) is an intrinsic base, (40) is a connection region, (41) and (42) are the first and second connection area, (15) is the emitter area, (8) and (13)
) are the first and second semiconductor layers, (11+) and (112
) are the first and second sidewalls.

Claims (1)

[Claims] 1. A bipolar transistor having a graft base and an intrinsic base of a second conductivity type in a semiconductor region of a first conductivity type, and an emitter region of a first conductivity type, wherein the graft base and the intrinsic base is formed deep on the graft base side and shallow on the intrinsic base side,
A bipolar transistor characterized in that the graft base and the intrinsic base are connected via a second conductivity type impurity region having a lower concentration than the intrinsic base. 2. Forming a first second conductivity type high concentration impurity region in the first conductivity type semiconductor region; and forming a second second conductivity type low concentration impurity region in contact with the first second conductivity type high concentration impurity region. forming an impurity region; and forming a first impurity region in the vicinity of the junction surface of the second low concentration impurity region of the second conductivity type with the semiconductor region and away from the first high concentration impurity region of the second conductivity type. A conductivity type impurity is introduced to form a third second conductivity type impurity region shallower than the second second conductivity type low concentration impurity region.
forming a conductivity type low concentration impurity region; and forming a second conductivity type intrinsic base and a first conductivity type emitter region in the third second conductivity type low concentration impurity region. Characteristic bipolar transistor manufacturing method.