JPH012363A - semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit having a heterojunction bipolar transistor.

[Summary of the invention]

The present invention provides a semiconductor integrated circuit having a heterojunction bipolar transistor, in which an emitter region and an external base region are formed in side contact with each other, and a region including a boundary between the emitter region and the external base region. A collector top type heterojunction bipolar transistor with a new structure is used, in which an intrinsic base region is formed on top of the transistor, and a collector region is formed on this intrinsic base region. By forming a load resistor with a material layer, high speed is promoted and it is easy to convert it into an IC.

[Conventional technology]

A heterojunction bipolar transistor is a transistor that can overcome the drawbacks of a homojunction bipolar transistor made of silicon or the like. That is, if we take a heterojunction bipolar transistor using N2GaAs for the emitter (E) and GaAs for the base (B) and collector (C) as an example, the holes, which are the majority carriers in the base, are Band gap difference between (ΔEg
) cannot diffuse into the emitter due to the energy barrier, the base current decreases and the efficiency of electron injection from the emitter to the base increases. Therefore, even if the base concentration is increased and the emitter concentration is decreased, the degree of enhancement (β-1c
/ I B ) can be increased.

This means that the base resistance and E-B junction capacitance, which are related to high speed performance, can be reduced, and it has been shown both theoretically and experimentally that the transistor is faster than a silicon bipolar transistor.

FIG. 5 shows a typical structure of an MI GaAs layer GaAs planar type heterojunction bipolar transistor that makes full use of ion implantation technology and metal embedding technology. An example of a method for manufacturing a collector top type heterojunction bipolar transistor (17) according to this structure will be briefly described.

A semi-insulating GaAs substrate (11) includes an n''-GaAs layer that becomes the emitter electrode extraction rfI (18), a NA12 GaAs layer that becomes the emitter region (5), and a pGaAs layer that becomes the base region (i.e., intrinsic base region) (4). Finally, an n-GaAs layer and a cap layer (which will become the collector region (3)
19) After epitaxially growing the n+-GaAs layer, first, the n"-GaAs layer is grown so as to leave the collector region.
The cap layer (19) of s is removed by etching, and 5jO2
After ion-implanting Mg using as a mask, an external base region (7) is formed by annealing. Next, an element isolation region (8) and a base/emitter isolation region (9) are formed by ion implantation of boron or Formation of trench (11), this trench (1)
A transistor (17) is manufactured by embedding gold Jm (12) in 1). (14) is the base electrode, (
15) is an emitter electrode, and (16) is a collector electrode.

The switching time τS of a heterojunction bipolar transistor is given by: However, Rb is the two-base resistance, cc is the base-collector capacitance, RL is the load resistance, CL is the load capacitance, and τb is the base passage time. Therefore, to reduce τS, Rb! : Reduction of CC is required. -For boat fishing, collector-top type heterojunction bipolar transistors are considered to have higher speeds because they are more advantageous in reducing Cc than emitter-top type heterojunction bipolar transistors. That is, (i) the collector-top type heterojunction bipolar transistor has a small collector area, so the collector-base junction capacitance is small, and it is advantageous for high speed performance. On the other hand, since the emitter area increases, the emitter-base capacitance increases. This is a disadvantage, however, since the emitter-base is a heterojunction, which is smaller than a homojunction. Furthermore, since the emitter concentration is small, the emitter junction capacitance can be made small and does not pose a major problem. The advantages of reducing collector capacitance are far greater, and published simulations show that the collector top type is faster.

(ii) From a circuit perspective, in the case of ECL (emitter coupled logic), the emitters of several transistors are connected in common to form a gate, so n
+ By using a common emitter layer without isolation, the device area can be reduced.

[Problem that the invention seeks to solve]

By the way, in the above-mentioned conventional heterojunction bipolar transistor, as the area of the device is reduced, the capacitance around the active region, that is, the periphery between the collector and the external base and between the emitter and the external base, becomes relatively large. come.

In the collector-top type heterojunction bipolar transistor shown in Fig. 5, when calculating the case where the collector area is l×lμ-, the intrinsic partial capacitance is the emitter-base capacitance Ceb'l; 2.7 fF, collector-base capacitance. capacity i1 Cbe”; 0.27fF (depletion layer 4000
Although the external capacitance (assuming a human being) is small, the external capacitance, that is, the capacitance of only the peripheral portion (11ceb' and Cbc') is Ceb' = 3.2f.
It can be seen that it is quite large at 0.5 fF. Therefore, it is desirable to have a structure in which the contribution of the peripheral area does not become large as the device area is reduced.In fact, such a device has been devised in the St-based bipolar transistor. There is.

In the heterojunction bipolar transistor having the configuration shown in FIG. 5, if an attempt is made to reduce the external capacitance, the base contact region becomes smaller, which increases the base contact resistance and limits the speed of the device.

In addition to the above-mentioned points, conventional heterojunction bipolar transistors in which an external base is formed by ion implantation have the following drawbacks.

(i) The concentration of the external base region cannot be increased.

(ii) A displacement of the junction position occurs due to the diffusion of implanted impurities into the emitter region and the diffusion of impurities in the intrinsic base region during activation annealing.

(iii) The external capacitance of the periphery generated between the emitter external base and the collector external base becomes relatively large as the device area becomes smaller. In particular, the collector capacity of the periphery cannot be eliminated.

(iv) Extracting the emitter electrode requires the formation of a deep trench and metal embedding technology.

(v) The base and emitter contact areas cannot be increased without increasing the capacitance.

(vi) Among the electrons injected from the emitter region to the intrinsic base region, electrons in the periphery diffuse into the extrinsic base region by the diffusion length (several μm) and recombine with holes, increasing the reactive base current. Due to the so-called periphery effect, when the element is made smaller, the current increase rate lJ decreases.

In view of the above-mentioned points, the present invention constructs a collector-top type heterojunction bipolar transistor that has excellent high-speed performance by reducing the collector capacitance and emitter capacitance, and also facilitates IC integration including load resistance. The system uses semiconductor integrated circuits that have been developed.

[Means for solving problems]

In a semiconductor integrated circuit including a heterojunction bipolar transistor, an emitter region and an external base region are formed so as to be in contact with each other at their sides, and the emitter region and the external base region A collector top type in which an intrinsic base region is formed on a region including a boundary between a part of an emitter region and a part of an external base region, and a collector region is formed on this intrinsic base region. constitutes a heterojunction bipolar transistor.

Then, a negative Vr resistor is formed in the same material layer as the emitter region or base region of this heterojunction bipolar transistor.

[Effect]

Looking at heterojunction bipolar transistors,
Since the collector region on the intrinsic base region is hardly in contact with the external base region, the collector capacitance is only the capacitance of the intrinsic portion and is small. Further, since the emitter region and the external base region are in contact with each other, for example, only on one side, the emitter capacitance is also reduced. That is, even if the device area is reduced, the capacitance at the periphery (external capacitance) becomes smaller. Also, the extrinsic base region hardly contacts the collector region, and only contacts the emitter region on the sides. Therefore, the external base area can be increased without increasing the capacitance, and the base contact resistance is reduced. On the other hand, during manufacturing, the intrinsic base region is formed by epitaxial growth after the external base region is formed, so that the thickness of the intrinsic base region can be made extremely thin.

Also, the final epitaxial growth (thermal process ~700℃)
Since an intrinsic base region is formed in this step, no displacement of the bond occurs.

In the present invention, especially when constructing a semiconductor integrated circuit, by forming a load resistor using the same material layer that constitutes the emitter region or base region of the transistor,
There is less wiring and the configuration is simpler.

〔Example〕

An embodiment of a collector-top type heterojunction bipolar transistor according to the present invention will be described with reference to FIG. 1, together with its manufacturing method.

First, as shown in IA, the semi-insulating GaAs base!
Fj, barrier layer (32) for the emitter on (31)
High resistance wide punt gap JFi, that is, thickness 0.3
μm semi-insulating M;! 0.5 Gao,s As
(Undoped) layer, emitter region thickness: 0.5μ
m-, impurity concentration due to Si doping 2 x 1018c
, m-' degree N-8Q O,3Gao,t Asjn
(33) and a gradient composition layer (34) formed by sequentially changing the Aff composition ratio X of N -Al2 x Ga1-x As from 0.3 to 0 by MOCVD (metal-organic chemical vapor deposition) method. . Incline ♀ ;) The composition layer (34) has a thickness of 0.0
It is formed with a thickness of 3 μm and an impurity concentration of 5×10 17 cm −3 so that X gradually changes from 0.3 to 0 from the bottom. Further, on the gradient composition layer (34), a thickness of 0.1μ is applied.
A silicon nitride (SiN) layer (35) of m thickness is deposited.

Next, as shown in Figure 1, the silicon nitride layer (35) is selectively etched so as to leave a portion corresponding to the emitter region, and the remaining silicon nitride layer (35) is used as a mask to perform wet etching to form a gradient composition. Layer (34) and N
An emitter region (33E) is formed by selectively etching sJW (33) onto Al2o3Gao,v.

Next, as shown in FIG. 1C, using the silicon nitride layer (35) as a mask, a p + -GaAs layer (
36) is selectively grown to the same height as the silicon nitride layer (35).

Next, as shown in the first diagram, after removing the silicon nitride layer (35), a 0.01 μm thick spacer layer (not shown) made of undoped GaAs, a 0.1 μm thick spacer layer that will become the intrinsic base region, Impurity concentration 2 x 10”cffl-
3 p" GaAs layer (3B), collector region with a thickness of 0.4 μm, impurity concentration of about 10'cm-" n-GaAsrEi (39), collector cap layer with a thickness of 0.1 μm, impurity concentration 5×1018C
The n''-GaAs layer (40) of about I11-3 is sequentially MO
Grown by CVD method. Here, undoped GaAs
The p-type impurity (for example, Zn) in the p''-GaAs layer (3B) is
It is possible to prevent As from being diffused into the emitter region (33E).

Next, as shown in FIG. 1E, an n''-GaAs layer (40) is etched by RIE (reactive ion etching), leaving the portions corresponding to the collector region and the external base region.
n-GaAsrti (39), p +
- Selectively etching away the GaAs layers (38) and (36). This forms an external base region (36b). Since A12GaAs is not etched by RIE, the surface of the graded composition layer (34) constituting a part of the emitter region is exposed and the elements are isolated by this RIE.

The selected etching pattern at this time is the first one when viewed two-dimensionally.
The pattern is as shown in Figure G. That is, the emitter region (33I) is located at the center of the − side of the rectangular emitter region (33E).
A region (51) that overlaps with a width W2 smaller than the width W1 of the region (that is, corresponds to the area of the intrinsic part described later) (51) is connected to an extension of this region (51) extending outside the emitter region (33E). Then, the area portion (corresponding to the area of the external base area described later) (corresponding to the area of the external base area described later) is larger than the width W2 of the area portion (51).
52) is selectively etched with a pattern.

Next, n”-GaA on the external base region (36b)
srfA (40), n-GaAsrji (39)
and the p'' GaAs layer (38) are selectively removed by RIE to form a collector cap layer (40c), a collector region (39C) and an intrinsic base region (38B'').
form. Next, silicon oxide (Si02) layer (4
After forming 1) on the entire surface, it is flattened to expose the collector cap layer (40c) to the surface. Then, after opening a window for extracting the base electrode and the emitter electrode in the silicon oxide H (41), the emitter region made of N-Al2GaAs, that is, the gradient composition Jiif (34
) and a cap 54 (40c
), an emitter electrode (42) and a collector electrode (43) made of AuGe/Au are formed, and I)"Ga
TI/Pt in the external base region (36b) with As
/Au to form the base salt 17iS (44).

Thus, as shown in FIGS. 1F and H, the external pace fi
The region (36b) and the emitter region (33E) are formed in contact with the side surfaces of the − side, and a semi-insulating Aj2GaA layer is formed below the external base region (3[3h) and the emitter region (331).
A barrier layer (32) consisting of s is formed, and a part of the emitter region (33E) is formed so as to include the boundary between the emitter region (331E) and the external base region (36b), that is, to partially touch the external base region (36b). An intrinsic base region (38B) and a collector region (39C) having a width W2 smaller than the extrinsic base width W3 and the width w1 of the emitter region are formed on the part, so that the extrinsic base region (36b) and the intrinsic base region (38B) is in contact with the − edge and is the intrinsic base region (
38B) is smaller than rj]w3 of the external space region l13i (36b).

FIG. 2 shows another embodiment of the collector-top type heterojunction bipolar transistor according to the present invention.

In this example, first, as shown in FIG. 2A, a semi-insulating G
On the aAs substrate (31), a barrier layer (
32) Semi-insulating A12 with a thickness of 0.3 μm
o, s Gao5As (undoped) N-Δ(l o3G
ao, r^sR (33), N -A12 X Ga5
-z Thickness 0.03 μm, impurity concentration 5 x 1017 cm, made by sequentially changing the M composition ratio X of As from 0.3 to O.
A gradient composition layer (34) of about -3, and a thickness of 0.5 to become an emitter cap layer. crm, impurity concentration 5 x 1
n''-GaAs layer (46) of about 0.018 cm-3, thickness of 0.02 μm, impurity concentration 5×1018c
N -A12 o3 Gao, v As layer (about m-3)
47) are sequentially grown using the MOCVrl method. This N
A silicon nitride (SiN) layer (35
) is deposited and formed.

Next, as shown in FIG. 2B, after selectively etching the silicon nitride layer (35) so as to leave a portion corresponding to the emitter region, N Al2 o3 G ao, v is etched using the silicon nitride fi (35) as a mask. HesJa (47)
, n''-GaAsM (46), graded composition layer (34), and N-Al21], 1 Gaot As layer (33) are selectively etched away to form an emitter region (33B).

Next, as shown in FIG. 2C, using the silicon nitride layer (35) as a mask, a p + -GaAs layer (
36) is selectively grown to the same height as the silicon nitride layer (35).

Next, as shown in the second diagram, after removing the silicon nitride layer (35), the N-MO, 3Gao, tAs layer (47) in the region including the portion corresponding to the collector region is removed by wet etching. At the same time, p
"-GaAs layer (36) and n"-GaAsM
(46) to include the boundary with n”-GaAs1i
(46) and p + -GaAs layer (36) with n”-GaAs
The thickness of sM (46) is selectively removed by etching.

Next, as shown in FIG. 2E, a spacer layer (not shown) made of undoped GaAs with a thickness of 0.01 μm, a thickness of 0.1 μl and an impurity concentration of 2×1 to form an intrinsic base region is formed.
I)"-GaAs layer (38) of about 0110l9", thickness 0.4μ serving as collector region, impurity concentration 10"
n''-GaAs layer (39) of about cm-3 and collector cap layer with a thickness of 0.1 μm1 impurity concentration 5X
An n4''-GaAs layer (40) of about 1018 cm-3 is grown by MOCVD.

Next, as shown in Figure 2F, °ζ
n”-GaAslW (40), n-GaAsjM
(39), RIE p“-GaAsM (36) leaving parts corresponding to its collector region and external base region.
Selectively etch with . This forms an external base region (36b) and an emitter camp Jet (46e). At this time, N2GaA5T6 is not etched by RIE. Therefore, the emitter cap jM(
Emitter cap F# (46e) is not etched due to the Al2GaAs layer (47) provided on top of 46e).

Next, as shown in FIG. 2G, the external base region (36b
) on n ”-GaAsM (40) and n-Ga
As1M (39) is selectively etched away. As a result, a collector camp R (40c), a collector region (39C) and an intrinsic base region (38B) are formed.

Next, silicon oxide (SiO2) is applied to the entire surface using the CV L method.
) A layer (41) is deposited and planarized to expose the surfaces of the external base region (36b), the collector cap H (40c) and the emitter cap layer (46e).

After that, a collector capacitor (43) consisting of Ge/U and an emitter electrode (42) are placed on the collector cap IN (40c) and the emitter cap rM (46e).
and also the external base region (36b) - to T
A base electrode (44) made of i/PL/^U is formed to obtain the desired collector-top type heterojunction bipolar transistor (49), not shown in FIG. 2H. FIG. 2 is a plan view of this Peter junction bipolar transistor (49).

The collector-top type heterojunction bipolar transistor having such a configuration has the following advantages.

Since the collector region (39C) is formed in a mesa shape and the side surfaces are covered with silicon oxide Jil (41), no collector capacitance is generated at the periphery and only the intrinsic collector capacitance is included.

Therefore, the collector capacitance becomes extremely small.

The external base region (36b) is formed of Evitacal IH with a thickness of 0.5 μm and an impurity concentration of 2 × 10' cm-3 or more, and is made of N -Al1 GaAs 1M of the conventional structure.
The impurity concentration can be improved by about an order of magnitude and the mobility can be improved compared to when formed by ion implantation, and the external base resistance can be reduced. In addition to increasing the impurity concentration of the external base region (36b), the base contact resistance can be reduced by increasing the contact area. However, the conventional structure is accompanied by an increase in collector capacitance. In contrast, in this configuration, the external base area (3
6b) hardly contacts the collector region (39C) and only contacts the emitter region (33E) with the width W2 of one side, so the external base region (36b) can be expanded without increasing the external capacitance. It becomes possible to form a large area, and the base contact resistance can be reduced.

As shown in FIG. 1 and FIG. 2, the emitter region (3
3E, ) and the external base region (36b) are in contact only within the width W2 of one side, and therefore the emic capacitance is also small.

With this configuration, the capacitance of the periphery generated between the emitter external base and the collector external base does not increase relatively as the device area is reduced, and the base contact resistance can also be reduced, resulting in excellent high-speed performance. , and a heterojunction bipolar transistor that can be easily integrated into an IC can be obtained.

Since the emitter region (33B) and the external base region (36B) are in contact only at the - side, the electrons injected from the emitter region (33B) into the intrinsic base 't1 region (38B) are transferred to the external base region. Diffusion to (36b) is small. This means that the loss of electrons in the periphery is reduced (that is, the periphery effect is reduced in principle), and even when the active region is reduced to 1 × 1 μd, and even in the low current region. A high current amplification rate can be obtained.

Semi-insulating GaAs substrate (31) and emitter region (33E)
) and the extrinsic base region (36b) with a wide bandgap semi-insulating Af2GaA3 barrier layer (32
),,.

, it is possible to prevent leakage current through the substrate (31) between the p'' GaAs external base region (36b) and the N-/u2GaAs emitter region (33B). 33E) and the intrinsic base region (38B).
, -x By providing the gradient composition IS' (34) of As, the flow of electrons is improved, and so-called emitter current is facilitated to flow.

In this configuration, the base, collector, and emitter are formed with a substantially planar structure (a structure in which the electrodes are taken from the top surface), so there is no need to form a trench for taking out the emitter electrode or collector electrode as in the conventional case. Also, element isolation is RI
This is automatically done when the collector region is formed by E.

Ion implantation and annealing techniques are also not required, increasing device reproducibility.

After forming the thick extrinsic base region (36b), a final epitaxial growth forms the intrinsic base region (38B). Therefore, the thickness of the intrinsic base region (38B) can be extremely thin, for example, even if it is 2 to 300 people thick, it can be manufactured with high precision. At the same time, no displacement occurs in the bonding position.

Although the above embodiment is applied to an N2 GaAs/GaAs-based heterojunction bipolar transistor, it can also be applied to other types, such as GaAs/InGaAs-based ones.

CML is generally used as a high-speed bipolar circuit, but in the collector-top type heterojunction bipolar transistor structure according to the present invention, since the emitter can be shared between transistors, the CML structure can be easily manufactured. FIG. 3 shows a configuration example (plan view) of a three-man power NOR/OR circuit 2-gauge 4 using collector-top type heterojunction bipolar transistors according to the present invention. FIG. 4 shows an equivalent circuit diagram of the upper half of this semiconductor integrated circuit (the lower half is omitted because it is the same as the -F half). In this example, a load resistor R1 and a transistor Q are commonly connected to the collectors of transistors Ql, Q2 and Q3.

Load resistor R2 connected to the collector of transistor Q5 and load resistor R3 connected to the emitter of transistor Q5 are each formed by an N-8t2 GaAs layer (33) constituting an emitter region (330). Transistor Q1'+ Q
The load resistors R1'2R2/ on the 2', Qz' and Q4' sides are similarly formed of the A12GaAs layer (33). *t4
t1 (50) is a metal wiring. Note that each load resistance Rs.

R2+ R3, R1' and R2' are, for example, the p''-GaAs layer (36) constituting the external base region (36b).
) can also be formed. In this figure, ``jf'' in Figure 3, the load resistance of the conductor circuit product is N-A12GaAs (33)
Alternatively, it can be easily realized using p + -GaAsrii (36), and the structure is simpler because there is no need for wiring, especially compared to the conventional emitter top type.

〔Effect of the invention〕

According to the present invention, a collector-top type heterojunction bipolar transistor with small collector capacitance, small emitter capacitance, low base contact resistance, and excellent high speed performance can be obtained. When constructing a semiconductor integrated circuit using this heterojunction bipolar transistor, the structure can be simplified by forming the load resistor with the same material layer as the emitter region or base region of the transistor.

Therefore, the present invention is suitable for application to high-speed bipolar circuit devices such as CML.

[Brief explanation of the drawing]

1A to 1F are cross-sectional views showing an example of a collector top type heterojunction bipolar transistor according to the present invention in the order of steps; FIGS. 1G and 11 are plan views of FIGS. 1E and F, respectively; Figures A to 1 are cross-sectional views showing other examples of collector-top type heterojunction bipolar transistors according to the present invention in the order of steps, Figure 2 1 is a plan view of Figure 2 II, and Figure 3 is a plan view of the present invention. A semiconductor integrated circuit using a collector-top type heterojunction bipolar transistor, that is, a three-man power NO.
A plan view showing an example of a two-gate R,OR circuit, FIG. 4 is as follows:
) The equivalent circuit diagram in the upper half of the figure, Figure 5 shows the conventional collector.
FIG. 2 is a cross-sectional view of a top-type heterojunction bipolar transistor. (31) is a semi-insulating GaAs substrate, (33) is N-A1
2GaAs layer, (33B) is an emitter region, (34) is a graded composition layer, (36) is p''-GaAsr#iI,
(36b) is the external base region, (38B) is the intrinsic base region, (39C) is the collector region, R1, R2, R
1, IZR2' is negative (:1 resistance. Figure 1 table ``5''!y74k''i Figure 1 Figure 2 Figure 2

Claims (1)

[Claims] An emitter region and an extrinsic base region are formed in side contact with each other, an intrinsic base region is formed on a region including a boundary between the emitter region and the extrinsic base region, and an intrinsic base region is formed on the intrinsic base region. 1. A semiconductor integrated circuit comprising a collector top type heterojunction bipolar transistor having a collector region formed therein, and a load resistor formed of the same material layer as the emitter region or base region of the bipolar transistor.