JPH0122300Y2 - - Google Patents

Description

[Detailed description of the invention] This invention is a time division multiplex transmission system in which one base unit and multiple terminals are connected via signal lines, and each terminal can be remotely monitored and controlled from the base unit. It is related to.

FIG. 1 is a block diagram showing a schematic configuration of a conventional general time division multiplex transmission system. In the figure, 1 is a base unit, 2 is a signal line, 3 is a terminal device,
A local system 4 is controlled and monitored by the base unit 1 via the terminal 3. In such systems, in order to ensure reliable data transmission, data is generally sent and received using a handshake method, and in the system shown in FIG. 7 and data output lines OD0 to 7,
Ready signal line for use in handshake system
It has RDY, strobe signal line STB, etc. However, in such conventional systems, if the handshake timing is disrupted due to noise, etc., both the terminal device 3 and the local system 4 enter a state of waiting for data, or both enter a state of data output, causing the data to be lost. There was a possibility that communication would become impossible.

The present invention was developed to solve these problems of the conventional system, and when data communication becomes unstable, a buffer memory is set that stores flags for determining handshake timing. It is an object of the present invention to provide a time division multiplex transmission system in which the system can be returned to its initial state by performing the following steps.

The configuration of the present invention will be described below with reference to illustrated embodiments. FIG. 2 shows an embodiment of the present invention, in which a master device 1 and a plurality of terminal devices 3 are connected to each other via a pair of signal lines 2, and each terminal device 3 has an address. A unique address is assigned to each by the switch 5. A transmission signal in the format shown in FIG. 3 is sequentially transmitted from the base unit 1 to each terminal 3 in a cyclic manner for each address. This transmission signal includes a start signal ST indicating the start of signal transmission, a mode signal MD selecting the control mode of the terminal device 3, an address signal AD used to identify each terminal device 3, and a base device 1.
A control data signal CD containing control data sent from the terminal device 3 to each terminal device 3, and a return standby signal RT indicating a waiting period for the return of the monitoring signal from the terminal device 3 to the base device 1.
It consists of The terminal device 3 transfers the address data set by the address switch 5 to the signal line 2.
When it matches with the address signal AD above, the content of the control data signal CD is output to the data output terminals OD0 to OD7 of the terminal device 3, and the terminal device 3
The data of the monitoring signal input terminals IN0 to IN7 are returned to the base unit 1 during the period of the return standby signal RT.
Next, reference numeral 4 denotes a local system which is a monitored and controlled device, and is remotely controlled by the base unit 1 via the terminal device 3. This local system 4 has a built-in parallel input/output interface 6 for transmitting and receiving data with the terminal device 3 using a handshake method. However, in Fig. 2, the terminal device 3
receives control data CD from base unit 1, ready signal RDY of parallel input/output interface 6
If it is in the ready state, the data of the data output terminals OD0 to OD7 is latched in the buffer memory _R5 at the timing of clock _CK0 , and then the strobe signal _STB is read through the buffer memory R6. ₄ to the parallel input/output interface 6, the contents of the buffer memory _R5 are input to the data input terminals IN0 to IN7 of the parallel input/output interface 6.
Enter. Furthermore, when the parallel input/output interface 6 is not in the ready state, the terminal device 3 does not output the clock CK ₀ or the strobe signal STB.
This is to notify the base unit 1 that the parallel input/output interface 6 is not in the ready state during the period of the return standby signal RT. Similarly, when data is sent from the parallel input/output interface 6 to the terminal 3, the data is sent using a handshake method using the ready signal RDY, strobe signal STB, and clock CKi. 7 is a clear mode detection circuit, which detects when the mode signal MD of the signals transmitted on the signal line 2 matches a preset clear mode signal and the address signal AD matches the address of the terminal device 3. When the controller is in use, the stored contents of each buffer memory R ₁ to _{R 6} used for data transmission and reception using the handshake method are cleared and returned to the initial state. Therefore, even if the data content of each buffer memory R ₁ to _{R 6} becomes unstable when the power is turned on or noise is mixed in, and data transmission and reception using the handshake method becomes impossible, the output of the clear mode detection circuit 7 allows each buffer memory to be By setting the contents of the buffer memories _R1 to _R6 to the initial state, data can be transmitted and received normally. Note that as the parallel input/output interface 6 capable of transmitting and receiving data using the handshake method as described in the description of this embodiment, for example, Intel's 8255 can be used.

The present invention is configured as described above, in which a base unit and multiple terminals are connected to each other via a pair of signal lines, and the base unit transmits address signals and control data signals to each terminal. In a time-division multiplex transmission system in which signals including a return standby signal are transmitted, and each terminal is provided with a control data output terminal and a supervisory signal input terminal, a signal including a return standby signal is transmitted through the terminal, which is monitored and controlled by the base unit. A buffer memory is provided between the parallel input/output interface of the supervisory control equipment and the terminal device to temporarily store signals that control the timing of data transmission and reception using the handshake method. Since it is equipped with a clear mode detection circuit that clears the memory contents of the buffer memory, it can be cleared even if the data contents of each buffer memory become unstable when the power is turned on or noise is mixed in, making data transmission and reception impossible. There is an advantage that the contents of each buffer memory can be set to an initial state by the output of the mode detection circuit, and data can be transmitted and received normally.

[Brief explanation of the drawing]

FIG. 1 is a conventional block diagram, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a diagram showing the format of the transmission waveform. 1 is a base unit, 2 is a signal line, 3 is a terminal device, 4 is a local system, 6 is a parallel input/output interface, 7 is a clear mode detection circuit, and R ₁ to _{R 6} are buffer memories.

Claims (1)

[Scope of utility model registration request] A base unit and multiple terminals are connected to each other via a pair of signal lines, and signals including an address signal, a control data signal, and a return standby signal are transmitted from the base unit to each terminal, and each The terminal device has a control data output terminal that generates a control output according to the control data signal when the address signal on the signal line matches its own address, and a control data output terminal that outputs a control output according to the control data signal when the address signal on the signal line matches the own address. In a time division multiplex transmission system comprising a supervisory signal input terminal for inputting a supervisory signal to be sent back to In between, a buffer memory is provided that temporarily stores signals that control the timing of data transmission and reception using the handshake method, and a clear mode detection circuit is provided that clears the memory contents of the buffer memory when a clear mode signal transmitted from the base unit is detected. A time division multiplex transmission system consisting of