JPH01212471A - MOS type transistor and its manufacturing method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to improving the performance and reliability of a MOS transistor.

[Conventional technology]

Conventionally, a Lightly Doped Drain having a drain-source structure as shown in FIG. 6 has been used to alleviate the electric field at the drain portion of a short channel transistor.
(LDD)) transistors have been announced by TWANG and others. (IEEE Transaction Ele
ctron Devices VOL, DE-2919
82), Figure 6 shows N chi'r ne/L/L DDM
OS) transistor, the drain is connected to a high concentration of N.
Type impurity diffusion layer (6) and 10'/d to 1o18/d
It consists of an N-type impurity layer (4) with a medium concentration, and a part of the N-type impurity diffusion layer (6) is a gate electrode (8) made of polysilicon.
) below and several hundred inside from the edge of the gate electrode (8).

Next, a method of manufacturing this N-channel LDDMOS transistor will be explained with reference to FIG. P-type semiconductor substrate (
1) Form a gate oxide film (2) and a gate electrode (8) made of polysilicon on the semiconductor substrate (Figure 7-1). 1) Ion implantation at a dose of Ic-10"/d (see Figure 7-2), followed by CVD (chemical
The oxide film (6) is formed by Vapo Deposition method (Figure 7-3), and the oxide film (6) is left only on the side wall of the gate electrode (8) by anisotropic etching to form the sidewall (6'). In Figure 7-4), a high concentration of N-type impurity is implanted using the oxide film (6γ) remaining on the gate electrode (8) and the sidewalls of the gate electrode (8) as a mask.After this, heat treatment is applied to implant the implanted impurity. (4) p(6
) is activated to finally obtain an impurity profile as shown in Figure 7-5.

Next, the principle of the conventional LDD structure will be explained.

The source (5a) and substrate (1) of the transistor are grounded to the potential Ov, and the drain (5b) is connected to the power supply voltage (
For example, 5V) is given. Therefore, the P between the N-type drain parts (4b), (5b) and the P-type semiconductor substrate (1) is
A reverse bias is applied to the N junction and a high electric field is generated.

If the width of the depletion layer is increased, this drain electric field becomes N
A is the acceptor concentration of the substrate, and No is the Don of the N-type diffusion layer.
In the concentration of or, ε8 is the dielectric constant of the semiconductor, t is the amount of charge, and W
is the width of the depletion layer.

If the N-type impurity concentration is significantly higher than the P-type semiconductor impurity concentration, that is, No)) the width of the NA time depletion layer is W=
P1, and when the N-type impurity concentration and the P-type half-fN conductor substrate concentration are equal, that is, when NA = No, the width of the time depletion layer is W = ρ! So, even the low concentration N− layer)N
The more A, the lower the electric field at the PN junction. In the conventional LDD transistor shown in Figure 6, the electric field is relaxed by providing a medium-concentration impurity region (4) between the PN junction between the substrate (1) and the high-concentration N-type impurity diffusion layer (5). A MO+3 structure has been realized.

[Problem to be solved by the invention]

Since the conventional LDDMOEI) transistor is configured as described above, a medium concentration N-type impurity layer (4a) is also formed between the sources, increasing the parasitic resistance in the source region of the Mo8) transistor, and reducing the current driving ability. There was a problem with it falling.

In addition, in the structure of the drain of a conventional LDDMOS transistor, hot carriers having an energy higher than that in the thermal equilibrium state are generated on the surface of the medium-concentration N-type impurity diffusion layer (4b), and the generated hot carriers are transferred to the gate electrode of the Mo8) transistor. (8) is formed on the side wall of the N-layer (4b), and as a result, the surface of the N-layer' (4b) is depleted, the resistance of the N part increases, and the drain characteristics of the MoS transistor deteriorate, etc. There were reliability problems.

This invention was made to solve the above-mentioned problems, and it can alleviate the electric field at the drain part of MoS transistors and significantly reduce the deterioration of elements caused by hot carriers without reducing the current drive ability of KMOS transistors. The purpose is to obtain an improved LDDMOS) transistor that can suppress

[Means to solve the problem]

In the improved LDDMOS transistor according to the present invention, ions are implanted obliquely into the semiconductor substrate using the gate electrode as a mask, so that the medium concentration impurity layer overlaps with the gate electrode, and the side walls formed on the side walls of the gate electrode are formed. By using ion implantation as a mask and implanting ions obliquely into the semiconductor substrate, a structure is created in which the end of the high concentration impurity layer is aligned with the end of the gate electrode.

[Effect]

In this invention, the medium concentration impurity layer overlaps the gate electrode, and the edge of the high concentration impurity layer coincides with the edge of the gate electrode, so the medium concentration impurity layer is completely covered by the gate electrode. Therefore, the carrier concentration at the surface of the medium concentration impurity layer increases due to the voltage applied to the gate, and an increase in parasitic resistance in the source region is suppressed.

In addition, since the region where a high electric field is generated on the drain side is not directly under the sidewall but directly under the gate electrode, hot carriers are not injected into the sidewall, and the surface of the medium concentration impurity layer is depleted. Reliability problems such as deterioration of the current driving ability of the transistor are avoided.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (1) is a semiconductor substrate, (2) is a gate insulating film, (8) is a gate electrode, and (4) is a medium concentration impurity Ill.
, (5) is a high concentration impurity layer, (6Y is a side wall provided at the end of the gate electrode.

Since the M08 transistor of the present invention is configured as shown in FIG. 1, the medium concentration impurity layer (4a) C4b) completely covers the gate electrode (8), and the high concentration impurity layer (5a) completely covers the gate electrode (8). The end of (5b) coincides with the end of the gate electrode (8). Therefore, the carrier concentration at the surface of the medium concentration impurity layers (4a) (4b) increases due to the positive voltage applied to the gate electrode. FIG. 2 is an analysis of this situation using a device simulator, and shows the concentration of carriers on the silicon substrate surface near the source end. Medium concentration impurity layer N' (4a
) has a surface impurity concentration of about 10''/d.

In the conventional LDDMOS transistor, the gate electrode
Even if V is applied, the carrier concentration at the surface increases only to about 10" because the N"" layer is not covered by the gate electrode, and the carrier concentration in the channel region (about 10"/ff
The concentration is about an order of magnitude lower than (l). This region with low carrier concentration acts as a resistance, causing a decrease in the drain current driving ability. On the other hand, in the embodiment of the present invention, the N'''' layer is covered with the gate electrode, so when 5V is applied to the gate electrode, the carrier concentration is approximately xO
The carrier concentration rises to approximately 1/d, which is almost equal to the carrier concentration in the channel region. In this way, the N-layer no longer acts as a resistance, and the drain current driving ability is greatly improved. Figure 3 shows the drain current Driving capacity is gate length L
= 0.5 m - Gate width W = 10) 1 m -
Oxide film thickness = 10. The conventional method and the present invention are compared for am transistors, and the drain voltage Vo
= 5V and gate voltage VG = 5V, the drain current ZD was 3.3mA in the conventional method, but has increased to 4InA in the present invention.

Furthermore, due to the high electric field at the drain end, carriers are generated due to collision ionization. As shown in Figure 4, in the conventional method, the carrier generation region is directly under the sidewall provided at the end of the gate electrode, and the generated carriers are injected into the sidewall, causing depletion of the N layer. However, there was a reliability problem in that the current drive ability was further deteriorated.

On the other hand, in the present invention, the carrier generation region shifts from directly under the sidewall to directly under the gate, so the above-mentioned problem is eliminated and reliability is dramatically improved.

Next, a manufacturing method for realizing the structure of the present invention will be described. FIG. 5 is a process sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. A gate oxide film (2) and a gate electrode (8) made of polysilicon are formed on a P-type semiconductor substrate (1) (FIG. 5(A)).

To form the N- layer, phosphorus is ion-implanted using the gate electrode (8) as a mask. At this time, the ion beam is implanted with the incident angle of the ion beam tilted, for example, by 50" with respect to the normal direction of the substrate. (Figure 5 (B)).The wafer is also rotated around its central axis so that the impurity distribution in the source and drain becomes symmetrical.In this way, a structure in which the lower KN- layer at both ends of the gate electrode is loosened is created. The length of overlap between the N-layer and the gate electrode can be determined by the phosphorus ion implantation energy and the incident angle of the ion beam. -For example, the energy of the phosphorus ions is set to lQ. When Q KeV and the incident angle are set to 50@, the overlapping length is approximately 0.19 mem.

Next, OVD (Chemical Vapo D
The oxide film (6) is deposited by anisotropic etching (Fig. 5 (O)).
By etching 6), a sidewall (6') is formed on the side wall of the gate electrode (8) (FIG. 5(D)).

To form the N layer, high concentration trap ions of, for example, arsenic are implanted using the gate electrode (8) and sidewalls (6') as masks. At this time, as in the case of forming the N'''' layer, by implanting ions from an oblique direction while rotating the wafer (Fig. 5 (E)), the N layer is formed by a length corresponding to the width of the sidewall. It can be made into a structure with a loose structure. After this, heat treatment is applied at a temperature and time that does not cause the implanted impurities to thermally diffuse, activating the implanted impurities, and finally forming the N
- an LDDMOS transistor having layers (4a) (4b) and N layers (5a) (5b) can be manufactured.

In the above embodiment, an N-channel type MOS) transistor was explained, but by changing the conductivity type, a P
A similar effect is achieved for transistors (channel type MOS), and 0M transistors having N-channel type and P-channel type
A similar manufacturing method can be used for the 0a type semiconductor device.

This invention can be implemented in the following embodiments (1) to (6).

(1) In a MOS transistor that has a gate insulating film and a gate electrode on a semiconductor substrate, and a source and drain are formed on the surface of the semiconductor substrate in a self-aligned manner with respect to the gate electrode, the source and drain regions have high concentration. It consists of two regions: an impurity layer and a medium concentration impurity layer, and the medium concentration impurity layer is
A MOS transistor, which completely overlaps a gate electrode, and has a boundary between a high concentration impurity layer and a medium concentration impurity layer that coincides with an edge of the gate electrode.

(2) When forming the medium concentration impurity layer, the gate electrode is used as an ion implantation mask, and the ion beam is implanted at an angle of incidence with respect to the normal direction of the semiconductor substrate, and the tip of the medium concentration impurity layer is In addition to forming a side wall of an insulating film on both ends of the gate electrode, this side wall is used as an ion implantation mask to adjust the incident angle of the ion beam to the semiconductor substrate. 2. The semiconductor device according to claim 1, wherein ions are implanted at an angle with respect to the normal direction of the semiconductor device to form an MOa transistor having a structure in which the tip of the highly concentrated impurity layer coincides with the edge of the gate electrode, and the semiconductor device thereof. Manufacturing method.

(8) When forming the medium concentration impurity layer and the high concentration impurity layer, the incident angle of ion implantation is set at an arbitrary angle between 20 and 80'' with respect to the normal direction of the semiconductor substrate, and 2. The semiconductor according to item 2, wherein the wafer is rotated around the central axis of the wafer during ion implantation to make the impurity distribution in the source/drain region at the end of the gate electrode bilaterally symmetrical. Device and method of manufacturing it.

(4) A first feature characterized in that the amount of overlap between the medium concentration impurity layer and the gate electrode is set to 0.1 to 0.4 m.
The semiconductor device and the manufacturing method thereof according to item 1 or 2.

(5) By making the amount by which the high-concentration impurity layer overlaps the side walls of the insulating film formed at both ends of the gate electrode equal to the width of the side 6-all, the tip of the high-concentration impurity layer will overlap the gate electrode. MO with edge-matched structure
3. The semiconductor device and method for manufacturing the same according to claim 1 or 2, characterized in that a B-type transistor is formed.

(6) Phosphorus as an impurity forming a medium concentration impurity layer,
The semiconductor device according to item 1 or 2, wherein arsenic is used as an impurity to form the high concentration impurity layer.

〔Effect of the invention〕

As described above, according to the present invention, since the rotational oblique ion implantation method is used to form the N'' layer and the N layer, the N layer overlaps with the gate electrode by about O,I~0.3 m. , the seventh layer is an LDDMOS with a structure aligned with the gate electrode end.
) A transistor can be formed, which has the effect of significantly improving current drive capability and improving reliability.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a diagram showing a comparison of the carrier concentration of the N'''' layer according to the conventional method and the present invention, and FIG. 3 is a diagram showing the comparison between the conventional method and the present invention. A current-voltage characteristic diagram of a transistor according to the invention, FIG. 4 is a diagram showing locations where carriers are generated due to impact ionization, FIG. 5 is a process cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the invention, and FIG. 6 7 is a cross-sectional view showing a conventional LDDMOS transistor, and FIG. 7 is a process cross-sectional view showing a method of manufacturing a conventional LDDtA081-transistor. (1) is a semiconductor substrate, (2) is a gate insulating film, (8) is a gate electrode, (4) is an N- layer, (6) is an N layer, and (6) is a side wall. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (2)

[Claims] (1) In a MOS transistor that has a gate insulating film and a gate electrode on a semiconductor substrate, and a source and drain are formed on the surface of the semiconductor substrate in a self-aligned manner with respect to the gate electrode, the source and drain regions have high concentration. It consists of two regions: an impurity layer and a medium concentration impurity layer.The medium concentration impurity layer completely overlaps the gate electrode, and the boundary between the high concentration impurity layer and the medium concentration impurity layer coincides with the edge of the gate electrode. A MOS transistor characterized by: (2) When forming a medium concentration impurity layer, the gate electrode is used as an ion implantation mask, and the ion implantation is performed with the incident angle of the ion beam tilted with respect to the normal direction of the semiconductor substrate,
After creating a structure in which the tip of the medium concentration impurity layer goes under the gate electrode and forming side walls of an insulating film on both ends of the gate electrode, the side walls are used as a mask for ion implantation, and the ion beam is The ion implantation is performed with the incident angle of the impurity layer tilted with respect to the normal direction of the semiconductor substrate, thereby forming a MOS transistor having a structure in which the tip of the highly concentrated impurity layer coincides with the edge of the gate electrode. A manufacturing method for manufacturing the semiconductor device according to scope 1.