JPH01212025A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To attain high circuit integration by providing an Nchannel MOS transistor(TR) on a P-channel MOS TR at the output stage of a buffer circuit as an auxiliary TR. CONSTITUTION:The output stage of a buffer amplifier consists of a 1st N- channel MOS TR T2 whose drain is connected to an output terminal, whose gate is connected to a 1st input terminal and whose source is connected to a ground point, a 2nd N-channel MOS TR T3 whose drain is connected to, a power supply terminal, whose gate is connected to a 2nd input terminal and whose source is connected to the output terminal, and the P-channel MOS TR T1 whose drain is connected to an input terminal, whose gate is connected to the 2nd input terminal via an inverter and whose source is connected to a power supply terminal. In this case, the N-channel MOS TR T3 whose driving capacity is nearly three times larger than that of the P-channel MOS TR is employed to compensate the leading characteristic of the output signal of the buffer circuit as an auxiliary TR. Thus, the layout area is reduced and the chip area is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor integrated circuit capable of reducing the layout area of a buffer amplifier circuit.

2. Description of the Related Art In recent years, semiconductor integrated circuits have become highly integrated, and there is also a demand for reduction in circuit layout area.

In particular, buffer amplifiers that require current drive capability occupy a large layout area.

A conventional buffer amplifier circuit (hereinafter referred to as a buffer circuit) will be described below.

FIG. 2 shows a buffer circuit designed using a conventional semiconductor integrated circuit. In Figure 2, Din and D i
rt is a signal input terminal, and the signal input to the signal input terminal Din is a signal whose phase is inverted with respect to the signal input terminal D in. C3 is a control signal input terminal, and 0 is an output terminal. A+ and A2 are two-man NAND circuits,
This circuit outputs a low level only when both inputs are at a high level, and for other input levels,
Outputs high level. I, +12 and T3 are inverter circuits that invert the input signal.

T1 is P channel MOS) run lister (hereinafter referred to as PMOST)
, T2 is an N-channel MO1 transistor (hereinafter referred to as NMOST2).

The operation of the buffer circuit configured as above will be explained below.

When the signal input from the control signal input terminal C3 to the NAND circuits A+ and A2 is at high level, the signal input to the signal input terminal Din is high level, and the signal input to the signal input terminal Din is low level. , N
The output of AND circuit A is low level, and the output of NAND circuit A2
output becomes high level. The low level output signal of NAND circuit A1 is connected to inverter circuit ■1! After 2, P
Set the gate voltage of MOST+ to high level. Also, N
The high level output signal of the AND circuit A2 passes through the inverter circuit (3) and sets the gate voltage of the N MOST 2 to a low level. As a result, P MOST + becomes conductive, and N MOST T 2 becomes cut off, so that the level of the output terminal O becomes high. Similarly, when the control signal input terminal C8 is at a high level, the signal input to the signal input terminal Din is at a low level, and when the signal input to the signal input terminal Din is at a high level, the level at the output terminal O is at a low level. .

Next, when the control signal input terminal C8 is at a low level, the signals output to the NAND circuits A+ and A2 are both at a high level, no matter what signals are input to the signal input terminals D in and D in. These signals are then sent to the inverter circuit 1. and I3 to set the gate voltage of P MOST + to low level, and pass through inverter circuit 13 to set the gate voltage of N MOST 2 to high level. As a result, P M OS T r and NMOST2
Both are in a cut-off state, and the output terminal O is in an electrically isolated state and in a high impedance state.

To increase the current drive capability of the buffer amplifier and increase the drive capability of the next stage circuit, PMO3T+ and NMOS
It is necessary to increase the current drive capability IDS of T2.

The current drive capability IDS is generally expressed as shown below.

......(1) Here, μ indicates the hole mobility in PMOS T I, which is approximately 450c+J/V-see at room temperature, and in NMOS T2, it indicates the electron mobility. It is about 1500 cd/V-sec at room temperature. C: ox is MO
S) is the gate oxide film capacitance of the run lister. Wo and L' are the gate width and gate length of the MOS transistor. VQS is the voltage between the gate and source of the MOS transistor; 1. Vt is the threshold voltage of the MOS transistor.

The hole mobility of P MOST + is about one-third of the electron mobility of NMOST2, and in order to equalize the rise and fall characteristics of the output signal of the buffer circuit, P M O
It is necessary to equalize the driving capabilities of S T + and N M OS T 2. For this reason, P which affects the rise characteristics
The gate width of NOST+ was made approximately three times as long as the gate width of NMOST2, which influences the falling characteristics.

Problems to be Solved by the Invention However, in the conventional configuration described above, the gate width of the PMOSTr of the buffer circuit is approximately three times that of the NMOST, and the layout area of the PMOST+ increases. As a result, there was a problem in that the chip area increased.

The present invention solves the above-mentioned conventional problems.
By using NMO3T, which has a current drive capacity approximately three times larger than that of PMOST, to supplement the rise of an output signal due to , a semiconductor integrated circuit of a buffer circuit is provided, which can reduce the layout area and, by extension, the chip area. The purpose is to

Means for Solving the Problems The semiconductor integrated circuit of the present invention includes a first N-channel MOS transistor whose drain is connected to an output terminal, whose gate is connected to a first input terminal, and whose source is connected to a ground point, and whose drain is connected to a power supply terminal. a second N-channel MOS transistor having a gate connected to the second input terminal and a source connected to the output terminal; a second N-channel MOS transistor having a source connected to the power supply terminal and a gate connected to the second input terminal via an inverter; The output stage of the buffer amplifier is composed of a terminal and a P-channel MOS transistor whose drain is connected to the output terminal, and these are integrated on the same semiconductor substrate.

Effect: With this configuration, the layout area can be reduced by using an auxiliary N-channel MOS transistor, which has a rise characteristic of the output signal of the buffer circuit that is approximately three times as large as the drive capability of the P-channel MOS transistor, and thus the chip area. (It is possible to do so. Also, the driving ability of the next stage circuit can be improved with the same area as the conventional one.

Embodiment An embodiment of the semiconductor integrated circuit of the present invention will be described with reference to the circuit diagram of the buffer circuit shown in FIG.

In this circuit, the control signal input terminal C3 is connected to the NAND circuit AI.
and A2, and the signal input terminal DIofJ4 is connected to the other input terminal of NAND circuit A, and the signal input terminal ■ is connected to the other input terminal of NAND circuit A2, and the output terminal of NAND circuit A+ is connected to the gate of a P-channel MOS (P-channel MOS) run lister T+ (PMOST+) whose source is connected to the power supply terminal and drain is connected to the output terminal 0 through the inverter circuit 2 and the NAN
The output terminal of the D circuit A2 is connected via an inverter I3 to the gate of an N-channel MOS (N-channel MOS) run lister T2 (NMOST2) whose drain is connected to the output terminal 0 and whose source is connected to the ground point.
The drain of (NMOS T3) is the power supply terminal, and the gate is the inverter circuit! 1 output terminal, the source is output terminal O
This is a configuration connected to the

The operation of the buffer circuit of the semiconductor integrated circuit configured as described above will be described below.

When the signals input from the control signal input terminal C8 to the NAND circuits AI and A2 are at high level, the signal input to the signal input terminal D in is at a level of 1, and the opposite phase of the signal input terminal D in is input. signal input terminal D
When in is at a low level, the output of the NAND circuit AI is at a low level, and the output of the NAND circuit A2 is at a high level. The low level output signal of the NAND circuit AI changes the gate voltage of NMOS T 3 to high level through the inverter 1, and the high level output signal of the NAND circuit A2 changes the gate voltage of NMOS T 2 through the inverter I3. to low level. As a result, NMO3T3 becomes conductive, NMOST2 becomes cut off, and the potential of output terminal 0 becomes a potential lower than the power supply voltage by the threshold voltage of NMOS T3. The noise level output signal of inverter ■1 passes through inverter I2 to PMOS T
+ gate voltage as low level P M OS T
Make I conductive. PMOS T I serves to raise the potential of the output terminal O from a potential lower than the power supply voltage by the threshold voltage of NMOS T 3 to the power supply voltage auxiliary by NMO3T3. Similarly, when the control signal input terminal C8 is at a high level, the signal input to the signal input terminal Din is at a low level, and when the signal input to the signal input terminal Din is at a high level, the level at the output terminal 0 is at a low level. becomes.

Next, when the control signal input terminal C8 is at a low level, no matter what kind of signals are input to the signal input terminals D in and Din, the signals output to the NAND circuits A and A2 are both high. level. 'NAND circuit A
The high level output signals of I and A2 make the gate voltages of NMOST2 and MO3T3 low level through inverters I and 13, respectively, and the gate voltages of NMOST2 and NMOST2 and NMOST3 become low level.
s is turned off. Furthermore, the low level output signal of the inverter circuit 11 is passed through the inverter circuit I2 to the PMOS
By setting the gate voltage of T to high level, PMOS T
I is also turned off. Since PMO3T+, NMO3T2, and NMOS Ts are all cut off, the output terminal O is electrically isolated from the power supply voltage terminal and the ground terminal, and is in a high impedance state.

Control signal input terminal C3 is at high level, signal input terminal D
When in is high level and signal input terminal D in is low level, the rise characteristics are PMOST and PM
NMOS, which is an auxiliary transistor for OS T+
Determined by the current drive capability of T3.

If the gate widths of P M O S T + and N M O S T 3 are both equal and W, then from equation (1)
If the current drive capability of S T + is log, then NMOS
The current driving capability of T3 is approximately 3×1 os.

As described above, according to this embodiment, the gate widths of PMOSTI and auxiliary transistor NMOST3 are each W.
'', the total is 2W', and the current drive capability of the buffer circuit's rise characteristic is approximately 4XIos.P
If you want to achieve a current drive capability with the rise characteristic equivalent to the above with only MOS Tt, the gate width will be 4W', and by using the auxiliary NMOS T3, you can reduce the gate width of the transistor for output signal rise. can be halved in total, and the layout area of the semiconductor integrated circuit can be reduced.

Effects of the Invention As described above, according to the semiconductor integrated circuit of the present invention, the P-channel MOS transistor in the output stage of the buffer circuit has N
By providing an auxiliary channel MOS transistor, the layout area of the semiconductor integrated circuit can be reduced compared to the case where equivalent current driving capability is achieved only with a P-channel MOS transistor, and the chip area can also be reduced. , high integration can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a buffer circuit showing an embodiment of the semiconductor integrated circuit of the present invention, and FIG. 2 is a circuit diagram of a conventional buffer circuit. Dill + Dill...Signal input terminal, C3...Control signal input terminal, 0...
Output terminal, AI, A2...NAND circuit, I
l~I3...Inverter circuit, TV...
P channel MOS transistor, T2゜T3...
...N-channel MOS transistor.

Claims (1)

[Claims] The drain is the output terminal, the gate is the first input terminal,
First N-channel MOS with source connected to ground
transistor, the drain is the power supply terminal, and the gate is the second
a second one whose source is connected to the input terminal of the second
An output stage of the buffer amplifier is configured by an N-channel MOS transistor having a source connected to the power supply terminal, a gate connected to the second input terminal via an inverter, and a P-channel MOS transistor having a drain connected to the output terminal. and a semiconductor integrated circuit characterized in that these are integrated on the same semiconductor substrate.