JPH01201757A - Access contention avoidance circuit - Google Patents

Abstract

PURPOSE:To avoid the contention of two access requests by means of a miniature circuit scale by selectively making one access request to effective in accordance with the fastness or delay of two access requests by means of a static flip flop. CONSTITUTION:One static flip flop composed by an AND gate AND1, an OR gate OR1 and a couple of inverters INV1 and INV2 is used as an access contention avoidance circuit ABT. The access contention avoidance circuit ABT selectively makes one access request effective in two access requests to be contended by the fastness or delay of the request.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit for avoiding contention for access to a shared resource by a plurality of modules, each of which can be a bus master. The present invention relates to a technology that is effective when applied to miniaturization of circuits to avoid competition and high-speed response.

[Conventional technology]

A circuit that avoids access contention for shared memory, etc. included in a dual processor system or multiprocessor system uses a conventional flip-flop. If this is to be avoided, a pair of D-type flip-flops to which clock signals are provided with mutually opposite phases are supplied with mutually different ac-clock signals, and each of the D-type flip-flops is
The output of the D-type flip-flop is supplied to the clear terminal of the other flip-flop, so that the outputs of the pair of D-type flip-flops can have a complementary relationship.

The bus access contention avoidance technique is described in, for example, "Microcomputer Handbook JP674 to PCl3" published by Ohm Publishing on December 25, 1985.

[Problem to be solved by the invention]

However, the conventional access contention avoidance circuit requires at least one flip-flop for each access request signal, resulting in an increase in circuit scale and further increase in occupied area. However, since the access request is sampled in synchronization with the clock signal, if there is a difference between this sampling timing and the access request timing, the response to the access request will deteriorate.

SUMMARY OF THE INVENTION An object of the present invention is to provide an access contention avoidance circuit that can reduce the circuit scale and achieve high-speed response to access requests.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, it is equipped with a pair of logic gates whose input terminals and output terminals are cross-coupled with each other, and the other input terminal of each logic gate receives an access request signal or an access request signal of a different module (bus master module) that can be a bus master. A signal formed based on the access request signal is supplied, and when one of the access request signals is asserted first,
It is configured to include a static flip-flop that maintains the output state obtained thereby regardless of the asserted state of the other access request signal.

[For production]

According to the above-mentioned means, one static flip-flop resolves access conflicts by selectively validating two competing access requests to a shared resource by a plurality of modules, each of which can be a bus master, depending on whether the request is early or late. To avoid.

One such static flip-flop can directly avoid conflicts between two access requests, thereby reducing the circuit scale or occupying area.
In a semiconductor integrated circuit such as a programmable logic device in which basic cells are configured at the gate level, it becomes extremely easy to configure an access conflict avoidance circuit using unused or empty cells. Furthermore, since this static flip-flop does not require the sampling timing of the access request signal to be determined by a clock signal, etc., it is possible to process a given access request with only a negligible short delay due to several stages of internal gates. This enables fast response of access requests.

〔Example〕

FIG. 2 is a block diagram showing part of a dual processor system to which the access conflict avoidance circuit according to the present invention is applied.

This dual processor system includes two microprocessors MPU a and MPU b,
Both processors MPUa and MPUb share a memory CM, such as SRAM (Static Random Access Memory), as an independently accessible shared resource.

The address input terminal of this memory CM is coupled to the address output terminal of one microprocessor M P tJ a via an address input buffer ABUFa and an address bus ABa, and an address input terminal of the address manual buffer ABU
Fb and an address output terminal of the other microprocessor MPUb via address bus ABb. Furthermore, the data input/output terminal of the memory CM is coupled to the data input/output terminal of one microprocessor MPU a via the data input/output buffer DBUFa and the data bus DBa, and It is coupled to the data input/output terminal of the other microprocessor MPUb via DBUFb and data bus DBb.

The access conflict avoidance circuit ABT receives an access request signal REQa from one microprocessor MPUa, and receives an access request signal REQb from the other microprocessor MPUb.

Although not particularly limited, in this embodiment, both the access request signals REQa and REQb are sent to the microprocessor MPU.
a, output from MPUb. Access conflict avoidance circuit A
The BT selectively validates only one access request made by the microprocessor depending on whether the request signals REQa and REQb are asserted early or late, and the competing access selection signals P S a e P S b are sent to the access controller. Output to ACONT. This access selection signal PSa is set to a low level as an assert level, and is used as a signal for instructing access selection in response to an access request from the microprocessor MPUa. The access selection signal PSb is activated by the microprocessor M P tJ by the low level as the assertion level.
This signal is used to instruct the access selection in response to the access request by b. Therefore, access selection signal PS
a and PSb are not asserted at the same time, but only one of them is selectively asserted.

FIG. 1 is a circuit diagram showing a detailed example of the access conflict avoidance circuit BAT. This access conflict avoidance circuit BAT
is a two-man type OR gate OR1 to which an access request signal REQa is supplied to one input terminal, and an access request signal REQa to one input terminal via an inverter INv1.
The other input terminal of the OR gate AND1 is cross-coupled to the output terminal of the AND gate AND1, and the other input terminal of the AND gate AND1 is connected to the output terminal of the OR gate OR1. They are cross-coupled and configured as a static flip-flop in which the output of the OR gate OR1 is used as one access selection signal PSa, and the output signal of the AND gate AND1 is inverted and formed by an inverter INV2 as the other access selection signal PSb. .

In this access conflict avoidance circuit BAT, when both access request signals REQa and REQb are both negated to high level, both access selection signals PSa
, PSb are negated to high level. In this state,
When one access request signal RE Q a is asserted to low level.

One access selection signal PSa corresponding to this is inverted to low level. In this way, if one of the access request signals is asserted first, due to the nature of the static flip-flop, unless the one access request signal is negated, the resulting output state will be that of the other access request signal. Retained regardless of asserted state. As a result, access conflict avoidance circuit A
BT responds to competing access requests to memory CM by microprocessors MPUa and MPUb with its request signal R.
Only one of the access selection signals PSa and PSb is selectively asserted to avoid conflicting access requests, depending on whether the nasser timing of EQa or REQb is early or late.

The access controller ACONT sends various timing signals or control signals to enable the microprocessor MPU a or MPUb to access the memory CM in response to which access selection signal P S a or PSb is asserted. Form. Next, a detailed example of this access controller ACONT will be explained based on FIG. 3.

This access controller ACONT is a microprocessor MPU whose output operation is enabled when the access selection signal PSa is asserted.
and an address comparator ACOMPb for the microprocessor MPUb whose output operation is enabled when the access selection signal PSb is asserted.

One address comparator A COM P a has address data ADATa corresponding to the address space allocated to the memory CM set as a reference address in advance via an address switch, and is supplied from one microprocessor M P U a. In response to the address strobe signal ASa being asserted to a low level, the address signal ADR8a output from the microprocessor MPUa is taken into the microprocessor and compared with a reference address. If the comparison result is a match, the address buffer selection signal ABSa, which is the output signal of the address comparator ACOMPA, is asserted to a low level, but such output operation is performed when the access selection signal PSa is asserted. This is done only if This address buffer selection signal ABSa is set to address input buffer A B U F a depending on its low level.
control to be operational. Address buffer selection signal ABSa is logically summed with data strobe signal DSa by two-manual OR gate OR2, and the output of this OR gate OR2 is used as data buffer selection signal DBSa. The data buffer selection signal DR8a is asserted to a low level only when the address buffer selection signal ABSa and the data strobe signal DSa are both asserted, and controls the data output buffer DBUFa to be operable.

The other address comparator ACOMPb is connected to memory C.
Address data ADATb corresponding to the address space allocated to M is initialized in advance as a reference address, and in response to the address strobe signal ASb supplied from one microprocessor MPUb being asserted to a low level. The microprocessor MP
The address signal ADR8b output from Ub is taken in and compared with the reference address. If the comparison result is a match, the address buffer selection signal ABSb, which is the output signal of the address comparator ACOMpb, is asserted to low level, but such output operation is performed only when the access selection signal PSb is asserted. . Address buffer selection signal ABSb controls address manual buffer ABUFb to be operable by its low level. Address buffer selection signal ABSb is logically summed with data strobe signal DSb by two-manual OR gate OR3, and the output of this OR gate OR3 is used as data buffer selection signal DBSb. The data buffer selection signal DBSb is asserted to a low level only when the address buffer selection signal ABSb and the data strobe signal DSb are both asserted, and controls the data output buffer DRUFb to be in an operable state.

The data buffer selection signals DBSa and DBSb are supplied to a two-manual AND gate AND2, and the logical product of the plane input signals is used as the chip enable signal CE of the memory CM. This chip enable signal CE is asserted to a low level in response to a request for accessing the memory CM by the microprocessor MPU a or MPUb being validated by the access selection signal PSa or PSb.

The address buffer selection signal ABSa and the read/write signal R/Wa are logically summed by the OR gate OR4, and the address buffer selection signal ABSa and the read/write signal R/Wa are
Sb and read/write signal R/Wb are OR gate OR
The logical sum is determined by 5. OR gate above
The outputs of 4 and OR5 are supplied to a two-manual AND gate AND3, and the logical product of the plane input signals is used as the read/write signal R/W of the memory CM. This read/write signal R/
W is a microprocessor M P U a or M P
When the access request to the memory CM by Ub is made valid by the access selection signal PSa or PSb, it is controlled to be in phase with the read/write signal output from the processor that is made valid.

Next, the operation of the above embodiment will be explained with reference to the time chart of FIG. 4.

FIG. 4 shows an example of a case where the access request by the microprocessor MPUa comes before the access request by the microprocessor MPUb.

For example, when the microprocessor MPU a outputs the address signal ADR8a and the access request signal REQa is asserted at time t, the access contention circuit ABT responds to the assertion of the access request signal REQa. Assert the access selection signal PSa for Ua. This allows access controller AC
The ONT sequentially asserts an address buffer selection signal A RS a and a data buffer selection signal D B S a to select an address manual buffer ABUFa and a data input/output buffer D for the microprocessor MPU a.
The memory CM is controlled by the microprocessor M P U a by controlling each RUFa to be in an operable state and by asserting the chip enable signal GE to the memory CM.
Make it accessible by.

During the access of the memory CM by the microprocessor M P U a, the address signal ADR8b for accessing the memory CM is input to the microprocessor M P t
The access request signal RE outputted from Jb for this purpose
When Qb is asserted at time t1, the access contention avoidance circuit ABT receives the previously asserted access request signal RE.
Control avoids access conflicts in the memory CM by maintaining the output state achieved in synchronization with time t (access selection signal PSa asserted, access selection signal PSb negated) until Qa is negated. do.

When the access request signal REQa is negated at time t3, if the access request signal REQb is maintained in the asserted state by the other microprocessor MPUb, the access selection signal P S a is changed to the negated state in synchronization with this. At the same time, the access selection signal PSb is changed to the asserted state. As a result, the access controller ACONT sequentially asserts the address buffer selection signal ABSb and the data buffer selection signal DBSb to control the address manual buffer ABUFb and the data input/output buffer DBUFb for the microprocessor MPUb to an operable state, respectively. At the same time, the memory CM is made accessible by the microprocessor MPUb by asserting the chip enable signal CE to the memory CM.

According to the above embodiment, the following effects can be obtained.

(1) The access contention avoidance circuit ABT, which functions as one static flip-flop constituted by an AND gate ANDl, an OR gate ORI, and a pair of inverters INVI and INV2, is a memory CM as a shared resource by the microprocessors MPUa and MPUb.
1 depending on whether the request is early or late.
Two static flip-flops directly
Conflicts between two access requests can be avoided, and the circuit scale or occupied area can be reduced. In particular, due to the miniaturization of circuit scale, in semiconductor integrated circuits such as programmable logic devices where basic cells are configured at the gate level, unused or empty cells are used to configure access conflict avoidance circuits. It becomes extremely easy.

(2) Since the static flip-flop that constitutes the access conflict avoidance circuit does not need to specify the sampling timing of the access request signals REQa and REQb using a clock signal, etc., A predetermined access request can be made valid with only a short time delay, thereby achieving high-speed responsiveness of access requests.

Although the invention made by the present inventor has been specifically described above based on examples, the present invention is not limited thereto and can be modified in various ways without departing from the gist thereof.

For example, the access contention avoidance circuit of the above embodiment is configured by an AND gate, an OR gate, and a pair of inverters, but this can be configured in various ways by combining other appropriate logic gates.

Furthermore, although the above embodiment describes the case where no priority is set for access requests by two microprocessors, if priority-based processing is required, the circuit that performs the processing is configured to compete for access. It may be provided before the avoidance circuit. Further, although the two microprocessors in the above embodiment do not share the address bus and data bus with each other, the present invention can also be applied to an access conflict avoidance technique in a configuration in which shared resources provided on a shared bus are accessed. That is, it can be used as a so-called bus arbiter, and in that case, the output signal of the access conflict avoidance circuit is returned to the access request source as an acknowledge signal for the access request. Furthermore, the module that is subject to access conflict avoidance processing and can become a bus master is not limited to a microprocessor, but can be changed to a module such as a direct memory access controller. Furthermore, in the above embodiment, the case where the access request signal is both an output signal of the microprocessor is explained, but such an access request signal is externally output based on the address signal and address strobe signal output from the microprocessor. For example, in that case, the output of the address comparator as shown in FIG. The signal may be configured to be a signal such as the address buffer selection signal of the above embodiment to form the necessary control signals and timing signals.

Furthermore, the access conflict avoidance circuit according to the present invention can be built into a mask processor and used for arbitration between external and internal access requests.

In the above explanation, the invention made by the present inventor was mainly applied to avoidance of two access conflicts in a multiprocessor system, which is the background field of application of the invention, but the present invention is not limited to this, and the present invention is not limited to this. The present invention, which can be applied to arbitrating various access requests such as a system and avoiding access conflicts, selects only one of competing access requests to a shared resource by a plurality of modules, each of which can be a bus master, depending on whether the request is early or late. It can be applied to conditions that avoid access conflicts as being effective.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, a static flip-flop that avoids access conflicts by selectively validating only one of two conflicting access requests to a shared resource depending on whether the request is early or late can directly avoid conflicts between two access requests. By doing so, it is possible to achieve miniaturization of the circuit scale or reduction of the occupied area, and also to reduce unused or empty cells in semiconductor integrated circuits where basic cells are configured at the gate level such as programmable logic devices. This has the effect that it is extremely easy to configure an access conflict avoidance circuit using the .

Furthermore, since the static flip-flop included in the access conflict avoidance circuit does not need to specify the sampling timing of the access request signal using a clock signal, etc., the delay time is as short as several stages of internal gates and can be virtually ignored. This has the advantage that a predetermined access request can be made valid by just the above command, and thereby high-speed response of the access request can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a logic circuit diagram showing a detailed example of the access conflict avoidance circuit according to the present invention; FIG. 2 is a block diagram showing a part of a dual processor system to which the access conflict avoidance circuit according to the present invention is applied; The figure is a logic circuit diagram showing an example of an access controller that controls access to a memory as a shared resource included in a dual processor system, and FIG. 4 is a time chart for explaining access conflict avoidance operation. M PtJ a, M P U b...Microprocessor, CM...Memory, ABUFa, ABUF
b...Address buffer, DBUFa,
D B U F b-data buffer, ABT... access conflict avoidance circuit, ORI... OR gate, AND
l...and gate, INVI. I N V 2-...Inverter, REQa, REQb
--- Access request signal, PSa, PSb... Access selection signal FIG. 1 REQo, REQb --- Access request signal 8 PSo,
PSb---Fukuyare Q! 4J? aaFigure 2Figure 3

Claims (1)

[Scope of Claims] 1. A circuit that avoids access conflicts by selectively validating only one of competing access requests to a shared resource by a plurality of bus master modules depending on whether the request is early or late, wherein one input terminal and a pair of logic gates whose output terminals are cross-coupled with each other, and the other input terminal of each logic gate is supplied with an access request signal of a mutually different bus master module or a signal formed based on the access request signal. An access device comprising a static flip-flop that maintains an output state obtained when one of the access request signals is asserted first, regardless of the asserted state of the other access request signal. Conflict avoidance circuit. 2. The access conflict avoidance circuit according to claim 1, wherein the access conflict avoidance circuit is constituted by empty cells of a programmable logic device in which basic cells are constituted at the gate level.