JPH01196874A - Insulated gate semiconductor device - Google Patents

Abstract

PURPOSE:To increase a latch-up current value largely without elevating ON resistance by making the energy gap of a semiconductor material in a source region smaller than that of a semiconductor material in a base region. CONSTITUTION:The energy gap of a semiconductor material in a base region 23 is made larger than that of a semiconductor material in a source region 24. The greater part of holes (or electrons) flowing into the p base region 23 from n<-> epitaxial 22 are bypassed to the source region 24. Accordingly, the inflow of electrons not controlled by a gate in electrons (or holes) flowing into the base region 23 from the source region 24 is prevented, thus solving the cause of a latch-up.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an insulated gate type semiconductor device that prevents latch-up from occurring even in a large current region.

[Prior Art] Conventionally, D SA (Dirf'usion S el
An insulated gate semiconductor device having an fA lfgna+cnt) structure is known. Compared to power MOS, this insulated gate type semiconductor device generally has the advantage of having a small on-resistance for the same breakdown voltage and same chip size, but it has the advantage of being able to have a small on-resistance when the voltage is the same and the chip size is the same. There was a problem that so-called latch-up occurred, which caused the motor to become uncontrollable.Therefore, the current value at which latch-up occurs
In order to increase the latch-up current value (hereinafter referred to as latch-up current value), the following countermeasures have been proposed.

a) n between the p+ drain layer and the n+ epitaxial layer
A ten-shaped buffer layer is provided to suppress hole injection.

b) Reduce the n+ source width to shorten the length of holes traveling in the transverse force direction within the base.

C) Create recombination centers for number carriers in the n'''' epitaxial layer by irradiating with a high-energy electron beam or the like.

However, methods a) and c) above have a problem in that the on-resistance increases because the hole concentration in the n-epitaxial layer is reduced. In addition, method b) uses photolithography technology, so there is a processing limit of several μm.
There was an upper limit on how much latch-up current could be reduced.

[Problems to be Solved by the Invention] This invention has been made in view of the points mentioned below, and is designed to reduce the latch-up current so that the latch-up phenomenon can be effectively suppressed from occurring in the large current region. The present invention aims to provide an insulated gate semiconductor device that can be set to a significantly higher value and further eliminate the latch-up phenomenon.

[Means for Solving the Problems] That is, in the insulated gate semiconductor device according to the present invention, the energy gap of the semiconductor material forming the source region is particularly smaller than the energy gap of the semiconductor material forming the base region. is set to a small value.

[Function] That is, in this insulated gate semiconductor device, the energy gap of the semiconductor material in the base region is Egs, and the energy gap of the semiconductor material in the source region is Egs.
If gs, Egs<EgB...
・・・・・・・・・・・・・・・This is the relationship shown in (1), and most of the holes (or electrons) flowing into the p base region from the n-epitaxial layer are Among the electrons (or holes) that are bypassed to the source region and flow into the base region, the flow of electrons that are not controlled by the gate is prevented, and the cause of latch-up is resolved. It is.

[Embodiments of the invention] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a cross-sectional configuration of an insulated gate semiconductor device with a V-groove structure, and FIG.
G ate B 1polar T ransls
(referred to as tor)).

That is, in this IGBT, first, as shown in FIG. 2(A), on the surface of the p+ drain layer 21 made of silicon,
An n-epitaxial layer 22 is grown and a p base layer 23 is formed on the surface of the epitaxial layer 22 by a diffusion process as shown in FIG. 2(B).

If the base layer 23 is formed in this way, as shown in cf1 FIG. A small L1n semiconductor material, such as germanium, is epitaxially grown to form the n+ source region 24. Once the source region 24 is formed in this way, as shown in FIG.
A groove 25 is formed, and as shown in FIG. 2(E),
A gate oxide film 26 is formed on the surface of the source region 24 including the source region 5.

Then, as shown in FIG. 2(F), the n+ source region 24
Then, a gate oxide film 26 is formed by etching, and as shown in FIG.
Furthermore, a drain electrode 29 is formed at a predetermined position, and the IGB
This completes the T element.

In the above element, the p base 23 and the n/source region 24 form a junction between silicon and a material other than silicon, such as germanium, and form a heterojunction.

Here, suppose that the IGBT has a V-groove structure, and the p-14 drain layer 21. As a comparative example, the n-type epitaxial layer 22, the p base layer 23, and the n+ source region 24 are each made of silicon.

FIG. 4(A) shows the left half of the element with the configuration of the above comparative example, and FIG. 4(B) shows its equivalent circuit.
When a sufficiently large positive voltage is applied to the gate electrode 27 of this device, the channel 31 becomes open, and an electron current 0 flows from the source electrode 28 to the source region 24, the epitaxial layer 22, and the drain. The liquid flows in the order of layer 21. Due to the flow of this electron current, the pn junction of the drain layer 21 and the epitaxial layer 22 becomes forward biased, and a large amount of hole current 1hl
and Ih2 flows. Here, the hole current 1hl
flows from the drain layer 21 through the epitaxial layer 22 to the base layer 23, where the hole current flows laterally along this layer 23 and reaches the source electrode 28. Further, the hole current Ih2 does not particularly flow laterally in the base layer 23, but instead flows into the source electrode 28.

To explain the flow of the electron current 0 and the hole currents Ihl and Ih2 using an equivalent circuit, the flow of the electron current 10 starts from point a in the source electrode 28 to point a in the n+ source region 24.
Resistance Rch of point b1 channel 31.

The point d of the n'''' epitaxial layer 22 is successively passed through.

Further, the hole current Ihl is at a point d in the epitaxial layer 22.
, flows sequentially through point a in the c1 source electrode 28 in the p base layer 2 layer 3. Here, the above hole current 1 h
When l flows laterally in the p base layer 23, a voltage drop vr3 occurs due to the resistance RD in this portion. and,
This voltage drop VB is VI3<0.6V at room temperature.
If so, the diode D present at the junction between the source region 24 and the base layer 23 is not turned on.

However, when the drain current increases,
The hole current 1h also increases, and “VB>0.6V
“The condition comes to hold true.

Therefore, diode D turns on, and a new flow of electrons Iel is generated toward point C.

This electron flow 1 cl is the IGB shown in Figure 4 (A).
This means that the operation of the pnpn silice structure built in the structure of the T element is induced, and a so-called latch-up phenomenon occurs.

In a state where such a love-throttle phenomenon occurs, as shown in FIG. 5(A), the gate control malfunctions.
The flow of a large amount of electron current 1c and the flow of hole current Ih
The flow of electron current 1e and hole current Ihl! occurs across the four layers p"n'-pn+, and in the equivalent circuit of FIG. 5(B), the flow of electron current 1e and hole current Ihl! This corresponds to the junction diode D being turned on.

Similar to a thyristor, such a latch-up phenomenon of an IGBT element continues until the drain current is lowered to a predetermined value or less. This latch-up phenomenon can be avoided as long as a single semiconductor material of silicon is used.
This is an inherent problem.

IGB of the embodiment explained using FIGS. 1 and 2
The T element solves the above problems, and its operating state is shown in the left half configuration shown in Figure 3 (A) and the equivalent path in Figure 3 (B). I will explain using In the device of this example, the base layer 2 is
3 is constructed by diffusing impurities into the surface of the n-epitaxial layer 22, and the source region 24
is made of a semiconductor material made of germanium, for example, which has a smaller energy band gap Eg than silicon, and the source/base junction is made of a heterojunction.

Therefore, in the structure shown in FIG. 3A, when a sufficient positive voltage is applied to the gate electrode 27, the channel 31 opens and an electron current IO flows. On the other hand, the hole current is 1hl, Ih2.1113 and I
In particular, after the hole current Ihl flows into the p base layer 23, it is divided into a component 1h2 that flows in the lateral direction and a component 1h3 that flows into the n/source region 24. That is, in the equivalent circuit of FIG. 3(B), the hole current 1hl that has flowed from point d to point C is divided into two parts, and a part of the hole current Ih2 is caused by the lateral resistance R of the p base region 23. , a voltage drop vBl occurs and the current flows to point a, and the remaining hole current 1h3 passes through the diode Di and flows to point a. That is, the following relationship holds true.

1 hl -1h2+I h3・・・・・・・・・・・・
・・・・・・・・・・・・・・・(2) Here, Figure 4 (A
) (B) and the case of the comparative example shown in Fig. 3 (A) (B).
Examining the differences in the flow of hole current and electron current from the structure in which the source region 24 is made of a material (e.g., germanium) that satisfies equation (1), which is the example shown in , is as follows. Become.

a) In the state where the hole current Ihl is equal, in the example case I
Since the current is shunted to h2 and Ib3, the voltage drop at the resistor R8 is as shown in the following equation.

VBlkuVB・・・・・・・・・・・・・・・・・・
・・・・・・・・・・・・(3)b) When the voltage drop VD becomes larger than the predetermined value (0.6V), an electron current of 1el flows through the diode D in the case of Fig. 4, whereas hand,
In the embodiment shown in FIG. 3, when the voltage drop V81 across the resistor RB exceeds a predetermined value (varies depending on the material of the n+ source region 24), the diode DI is turned on, and a hole current 1h3 flows therein. A part of the hole current Ihl begins to flow from point C to point C. However, since the electron current is turned on, it does not flow to point C.

C) When the hole current increases further, the latch-up phenomenon begins to occur in the structure of the comparative example as explained in FIG. 5. However, in the example element shown in FIG. 3, even if the hole current 1hl increases in equation (2), only the hole current 1h3 flowing through the diode DI increases, and the hole current 1h2 does not increase. Therefore, the voltage drop Vsl does not increase, there is no flow of electrons from point C to point C, and no latch-up phenomenon occurs. That is, in the example device shown in FIG. 3, the flow of electron current is restricted to the path through the channel 31, and when the gate voltage is lowered, the channel 31 is turned off. and this IG
The BT element is now controlled to be off.

Next, we will explain the principle by which the above b) and C) become true if the above equation (1) is satisfied.

In (A) and (B) of FIG. 3, the following value γ is defined using the hole current 1h3 and electron current Ie flowing through the diode DI corresponding to the heterojunction between the n+ source region 24 and the p base layer 23. do.

γ 1e / (Ih3+Ie) ・・・・・・・
(4) This value γ is the same as the emitter efficiency of a heterojunction bipolar transistor (hereinafter abbreviated as HBT). Then, this emitter efficiency γ is given by the following equation.

γ−1/11 + (PE DE We )/(
ns DB LE ) ・cxp (ΔEg /KT)l ・−(5) However,
P % n' Hole concentration, electron concentration D = Diffusion coefficient WD: Base width LE: Diffusion length of minority carriers in emitter °ΔEg ””Eg E Eg s・・・・・・・・・
・(6) However, K: Boltzmann's constant T: Absolute temperature In the above HBT, in order to make γ as close to "1" as possible, the band gaps Egg and Eg between the emitter and base are
ΔEg (−Eg E−Ev, B), which is the difference in o, is increased. In other words, it is important to make the emitter bandgap larger than the base bandgap.
It is.

On the other hand, equation (1) means an operation opposite to that of HBT. That is, ΔEg in the IGBT element is redefined by the following equation.

ΔEg = Egs −Eg Ll・・・・・・・・・
(7) In this invention, “ΔEgB>Δgs
ΔEg<0 from °, and at room temperature C l ΔEg l > KT '', 23aheV-・--
--.- If (8) is satisfied, the following result is obtained.

0kuγ(1・・・・・・・・・・・・・・・・・・
・・・・・・・・・・・・・・・(9) Therefore, the above (
From equations 9) and 4, ', I c < I
h・・・・・・・・・・・・・・・・・・・・・・・・
(10) Therefore, from the above equations (7) to (10), n+
If a semiconductor material whose KT (energy band gap) is several times to several tens of times smaller than that of silicon is used for the source region 24, the above equation (10) is established, and the diode D1 corresponding to the source-base junction is turned on. It can be seen that only matching current flows in this state, and almost no electron current flows. From this result, the diode D1 shown in FIG.
It is confirmed that a hole current Ih3 flowing through the diode Di is generated, and no electron current flows through the diode Di.

In the above embodiment, the n-channel type IGB
Although the explanation is for a T element, the same applies to a p-channel type in which n and p in the embodiment are replaced. Further, in the embodiment, the effects and the like are explained with respect to the groove structure, but the same can be applied to other structures, such as the DSA structure.

Further, in the embodiment, the base region 23 is made of silicon,
Although the source region 24 has been described as being made of germanium, other materials constituting the source region 24 include a mixed crystal of germanium and silicon, a group 3 and group 5 compound semiconductor (for example, InASsGa Sb, In Sb),
Examples include compound semiconductors of Group 2 and Group 6.

[Effects of the Invention] As described above, in the insulated gate semiconductor device according to the present invention, without sacrificing an increase in on-resistance,
An insulated gate type that can significantly increase the latch-up current value or suppress the occurrence of the latch-up phenomenon, and that reliably improves reliability with low loss. It can be made into a semiconductor device.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional configuration diagram illustrating the configuration of an insulated gate type semiconductor device according to two embodiments of the present invention, and FIG.
F) is a diagram sequentially showing the manufacturing process of the semiconductor device, FIG. 3A is a cross-sectional configuration diagram of the left half of the MO8FET, FIG. Each of the figures (A) is a diagram showing a cross-sectional configuration of an element corresponding to the structure of the example element described above, and similarly (B) is a diagram showing an equivalent circuit of the element shown in Figure (A). 21...p+ drain layer, 22...n""" epitaxial layer 3...p base layer, 24...n+ source layer, 27... gate electrode, 28... source electrode, I
e...Electron current, Ih, Ib1-Ih3...Hole current. Applicant's agent Patent attorney Takehiko Suzue Figure 1 (A) (B) (C)
(D) (E)
(F) Figure 2

Claims (1)

[Scope of Claims] A semiconductor substrate having a second conductivity type region on the main surface side of a first conductivity type layer which is a drain region, and a first conductivity type region formed in a predetermined region on the main surface side of this semiconductor substrate. an insulated gate type semiconductor having a base region, a second conductivity type source region formed so that a channel region remains on the surface of the base region, and a gate electrode formed on the channel region with an insulating film interposed therebetween. An insulated gate type semiconductor device, characterized in that an energy gap of a semiconductor material of the source region is smaller than an energy gap of a semiconductor material of the base region.