JPH01161912A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the clock skew of the entire system employing many circuits by providing a variable delay type clock input buffer whose delay quantity is controlled in response to a control data. CONSTITUTION:An external clock input is given to a master clock input buffer 3 in an LSI chip having plural blocks 2..., and then to variable delay type clock input buffers 4... of each logic block 2 from the input buffer 3 in common. Then, e.g., serial input type shift registers 5... to provide a delay quantity control data are provided corresponding to the variable delay type clock input buffers 4... and a control data inputted from the outside of the LSI is set to the shift registers 5.... Thus, the clock skew of the entire system is reduced by properly adjusting the delay quantity of the variable delay type clock input buffers 4 of each LSI respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention (Industrial Application Field) The present invention relates to a semiconductor integrated circuit, and more particularly to a circuit for preventing skew of a clock used for synchronous operation.

(Prior art) Like large-scale logical systems such as computers, digital The clock signal used in a system that requires digital synchronization serves as a timing reference for the system, and how accurately this reference signal is distributed throughout the system affects the performance of the entire system. It is an important technology that influences recent years.

The development of semiconductor integrated circuit technology has made it possible to implement large-scale digital systems into LSIs (Large-Scale Integrated Circuits), but this has also led to problems such as clock skew within LSIs that require high-speed processing, and clock skew between different LSIs. Cue is a problem.

FIG. 7 shows a case where a clock is commonly supplied from the clock input buffer 75 to the clock buffers 73 and 74 of each logic circuit module 71 and 72 in the LSI chip 70, but as the circuit scale increases, As the chip size increases, clock skew occurs due to differences in characteristics of each clock buffer 73, 74 during manufacturing, load conditions, etc.

Conventional. As a method of reducing clock skies inside an LSI, as shown in Fig. 8 (al.
A dedicated clock line 8 is provided on the clock input buffer 82 to supply the output of the clock input buffer 82.

Alternatively, as shown in FIG. 8(b), the LSI chip 80
A dedicated clock line 8 is provided above to supply the output of the clock capacitor 7a 82, and the clock line 81
A method is known in which the buffer load is distributed by supplying the clock signal from the clock input buffer 84 to the buffer load 84 through a plurality of clock input buffers 83 .

However, although the method shown in FIG. 8(a) reduces clocks and squiggles on the dedicated clock line 81, it also reduces clocks and squiggles when the system becomes large-scale.

The buffer has a hierarchical structure, and the lower layer clock 227
Clock skew in the 7 part is not reduced.

Furthermore, the method shown in FIG. 8(b) involves adding buffer loads 84, which are not originally necessary, to the black input buffers 83, for the purpose of making the load conditions of each buffer the same. This results in a considerable increase in chip area.

Furthermore, the method shown in FIG. As in the system shown, even if clocks are supplied to two LSI chips 91 and 92 from a common main clock buffer 90, the clock buffers 93, 94, and
... and the clock buffer 9 in the other LSI chip 92
As a result of the movements of 5, 96, etc., black and squish will occur in the entire system. The above factors are (
1) Difference in load on clock buffers within each chip,
(2) Differences in process conditions during valley chip manufacturing; (3) Differences in temperature conditions and power supply voltage conditions between the valley chips.

(Problems to be Solved by the Invention) In the present invention, as described above, even if a dedicated clock line is provided in an attempt to reduce clock skew within an LSI, a sufficient effect cannot necessarily be obtained.

The problem is that the chip area increases considerably.

Or in the case of a system using multiple LSI'i
This was done to solve the problem of clock skew occurring between SIs. It is an object of the present invention to provide a semiconductor integrated circuit that can reduce internal clock skew of 1 vA and can reduce clock skew of the entire system even in a system that uses multiple.

[Structure of the Invention (Means for Solving the Problems) The semiconductor integrated circuit of the present invention incorporates a variable delay disk buffer whose delay amount is controlled according to control data. Features.

(Function) By providing a manual buffer for variable delay clocks in each circuit on the LSI chip and appropriately adjusting the amount of delay for each, it is possible to reduce clock discrepancies within the LSI chip. can. Therefore, in a system like Jin that uses multiple LSIs, each LSI
By appropriately adjusting the delay amounts of the SI's variable delay type clock, driver cover, and filter, the clock skew of the entire system can be reduced.

(Example) An example of the present invention will be described in detail below with reference to one drawing.

FIG. 1 shows an LSI chip 1 having a plurality of logic blocks 2, . It is commonly supplied to the variable delay type clock capacitors 7a4, . . . For example, a shift register 5 of a serial human-powered machine is provided for providing delay amount control data in correspondence with the variable delay range clock user cover 4, and this shift register 5... is set with control data input from outside the LSI.

The variable delay board black, rear cover, fa 4, etc. mentioned above are.

Each of them is configured as shown in FIG. 2 or 3, for example. That is, the variable delay type clock buffer 7a shown in FIG. 2 has a plurality of gate chain delay generating elements 23 and multiplexers 24 provided between the input buffer 21 and the waveform shaping output buffer 22. , this multiplexer 24 does not have the corresponding bit data of the control data as a control input, and the '1'' of this bit data
.

``''01, selects the clock signal on the input side or output side of the delay generating element 230 in the previous stage and outputs it to the subsequent stage.
Assuming that each stage of 3... has a corresponding delay amount of 8, 4.2゜l name, the delay is 0 to 15ns@et in units of 1ns@c by the control data of 4 pins and The amount can be set variably.

In addition, the variable delay board clock cover shown in FIG. The load 35 is grounded through a plurality of circuits connected in series in parallel, and the control gate 34 receives the corresponding bit data of the control data as a gate input, and the gate inputs the corresponding bit data of the control data, and Therefore, for example, if the capacitance value ratio of the four capacitors 35 is 8:4:2:1, the switch is controlled to be in the on/off state by the 4-bit control data. The amount of delay can be variably set in units of one step.

According to the LSI shown in FIG. 1 as described above, each logic processor,
Variable delay type clock input buffer for RI2...
It is possible to set each delay amount to an appropriate value, thereby reducing the clock skew between the outputs of the manual buffers 4, . . . .

Note that a register may be used in place of the shift register 5 provided corresponding to each of the manual buffers 4, and the control data may be inputted from outside to this register.

FIG. 4 shows an LSI chip f40tl- having a clock signal automatic synchronization adjustment function as another embodiment, and inside the LSI chip there is a variable delay type clock cover F43; The first phase comparison gate 41 and the second phase comparison gate 42 provided as part of the load of the phase comparison gate 43 and their phase comparison gate) 41.4
Each of the outputs A and B of 2 has an up-count input, a down-count input, and an up-down counter 44 which supplies the count output to the variable delay clock manual buffer 43 as control data. The system clock of the system using this LSI is inputted to the human buffer 43 from the outside, and this system clock is input to the LSI.
The reference black and white signals generated through the external fixed high-precision delay element 45 are input to each of the phase comparison signals 41, 42, and the phase comparison signals 41, 4. ? A part of the branch output of the input buffer 43 (
internal clock) is being input. Phase comparison of @2 above y
- The gate 42 converts the reference clock signal into an inverter 46.
The inverted signal and the internal clock signal are input to the AND gate 47, and as shown in FIG. A high level of noise occurs. On the other hand, the phase comparison gate 41 of il inputs the signal obtained by inverting the internal clock by the inverter 49 and the reference clock signal to the AND gate 50, as shown in FIG. 5(a).
As shown in FIG. 2, a high-level pulse is generated at the output A during a period in which the internal clock signal is ahead of the reference clock signal in phase. Therefore, the contents of the counter 44 and, by extension, the delay amount of the manual buffer 43 are controlled according to the phase difference between the internal clock signal and the reference clock signal, and are automatically adjusted so that the phase difference becomes zero. Become.

FIG. 6 shows, as an application example of the present invention, a configuration for reducing the clock skew of the entire system in a system using a plurality of LSIs each having a variable delay type clock and driver cover 7 as described above. There is. That is, LSI chips, pro 0, etc. each have a variable delay type clock cover, f4, etc., a register 61 for setting a detailed delay setting that gives control data to these, and the above-mentioned manual buffer. A clock output buffer 62 . . . for outputting a part of the branch outputs of 4 . . . for monitoring outside the LSI is included.

A system-wide clock external to the LSI is supplied to the human buffers 4 . The registers 61 are each independently given a register enable signal for latch control of control data input from outside the LSI, and receive parallel control data input from a common path 64 for delay amount setting data outside the LSI. Given.

According to the above system, while monitoring each clock output of each LSI chip, gate 6o, etc., each output is adjusted so that the delay amount of each variable delay type clock manual buffer 4 is appropriate. By setting and controlling the control data, it is possible to dynamically adjust the clock skew of the entire system to be kept low. In this case, each LS
Since it is possible to monitor each clock output of Ichi, Pro O, etc., it is possible to perform the above adjustment with extremely high precision and stability, which has a great effect on improving the performance of the entire system. able to demonstrate.

[Effects of the Invention] As described above, according to the semiconductor integrated circuit of the present invention, a variable delay clock whose delay amount is controlled according to control data;
Since a manual cover and a buffer are built in, clock skew can be reduced by providing this manual buffer at an appropriate location. In this case, there is no need to provide an extra load for a dedicated clock, Klein, clock, or buffer within the chip, so the increase in chip area is mostly due to the delay amount control element and control of the manual buffer for the variable delay type clock. Only the amount corresponding to the data storage unit is required. Furthermore, in a system using a plurality of semiconductor integrated circuits as described above, by appropriately adjusting the delay amount of the variable delay type clock capacitor 7a of each integrated circuit, the clock deviation of the entire system can be reduced. be able to. Therefore, the semiconductor circuit described above is suitable for use in large-scale digital systems such as microprocessors and computer systems that require high-speed logic processing.

[Brief explanation of the drawing]

FIG. 1 is a configuration explanatory diagram showing one embodiment of the semiconductor integrated circuit of the present invention, FIGS. 2 and 3 are circuit diagrams showing different specific examples of the variable delay type clock manual buffer in FIG. 1,
FIG. 4 is a configuration explanatory diagram showing another embodiment of the present invention, FIGS. 5(a) and 5(b) are timing diagrams showing the operation of FIG. 4, and FIG. A configuration explanatory diagram showing a large-scale digital synchronization system. Fig. 7 is a configuration explanatory diagram showing a conventional LSI clock input system. Fig. 8 (a) # (b
) is a diagram shown to explain a conventional method of reducing clock skew in the LSIK shown in FIG. g7, and FIG. 9 is a diagram showing a clock input system in a system using a plurality of LSIs. 4.43...Input buffer for variable delay lock. 5...Shift register, 23...Gate chain. 24... Multiplexer, 34... Control gate, 3
5... Capacity, 41.42... Phase comparison gate, 4
4...A, f down counter, 61...Register,
62...Clock output cover, 7a. Applicant's agent Patent attorney Takehiko Suzue Control data input Fig. 1 Fig. 4 A-2 of the station station

Claims (8)

[Claims] (1) A semiconductor integrated circuit comprising a variable delay clock input buffer whose delay amount is controlled according to control data. (2) The semiconductor integrated circuit according to claim 1, wherein the control data is parallel output data of the shift register obtained by inputting externally input serial data to the shift register. circuit. (3) The semiconductor integrated circuit according to claim 1, wherein the control data is parallel output data of the register obtained by inputting parallel data input from the outside into the register. (4) The semiconductor integrated circuit according to claim 2, wherein the register is latch-controlled by an external control input. (5) The variable delay clock input buffer is formed by connecting a plurality of stages of a delay generating element using a gate chain and a multiplexer that selects an input signal or an output signal of the delay generating element according to bit data of the control data. A semiconductor integrated circuit according to claim 1, characterized in that: (6) The variable delay clock input buffer has a control gate whose switch is controlled according to bit data of control data and a capacitive load for delay generation connected in series between the clock signal transmission path and the ground terminal. Claim 1 characterized in that a plurality of circuits are connected in parallel.
Semiconductor integrated circuit described in Section 1. (7) Detect the phase difference between the output of the variable delay clock input buffer and the externally input reference clock signal, control the contents of the up-down counter up and down according to this phase difference, and 2. The semiconductor integrated circuit according to claim 1, wherein the control data is parallel output data. (8) The semiconductor integrated circuit according to claim 1, further comprising an output buffer for taking out a part of the branch output of the variable delay clock input buffer to the outside.